mthca_main.c 34 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #include <linux/module.h>
  35. #include <linux/init.h>
  36. #include <linux/errno.h>
  37. #include <linux/pci.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/gfp.h>
  40. #include "mthca_dev.h"
  41. #include "mthca_config_reg.h"
  42. #include "mthca_cmd.h"
  43. #include "mthca_profile.h"
  44. #include "mthca_memfree.h"
  45. #include "mthca_wqe.h"
  46. MODULE_AUTHOR("Roland Dreier");
  47. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  48. MODULE_LICENSE("Dual BSD/GPL");
  49. MODULE_VERSION(DRV_VERSION);
  50. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  51. int mthca_debug_level = 0;
  52. module_param_named(debug_level, mthca_debug_level, int, 0644);
  53. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  54. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  55. #ifdef CONFIG_PCI_MSI
  56. static int msi_x = 1;
  57. module_param(msi_x, int, 0444);
  58. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  59. #else /* CONFIG_PCI_MSI */
  60. #define msi_x (0)
  61. #endif /* CONFIG_PCI_MSI */
  62. static int tune_pci = 0;
  63. module_param(tune_pci, int, 0444);
  64. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  65. DEFINE_MUTEX(mthca_device_mutex);
  66. #define MTHCA_DEFAULT_NUM_QP (1 << 16)
  67. #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
  68. #define MTHCA_DEFAULT_NUM_CQ (1 << 16)
  69. #define MTHCA_DEFAULT_NUM_MCG (1 << 13)
  70. #define MTHCA_DEFAULT_NUM_MPT (1 << 17)
  71. #define MTHCA_DEFAULT_NUM_MTT (1 << 20)
  72. #define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
  73. #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
  74. #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
  75. static struct mthca_profile hca_profile = {
  76. .num_qp = MTHCA_DEFAULT_NUM_QP,
  77. .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
  78. .num_cq = MTHCA_DEFAULT_NUM_CQ,
  79. .num_mcg = MTHCA_DEFAULT_NUM_MCG,
  80. .num_mpt = MTHCA_DEFAULT_NUM_MPT,
  81. .num_mtt = MTHCA_DEFAULT_NUM_MTT,
  82. .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
  83. .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
  84. .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
  85. };
  86. module_param_named(num_qp, hca_profile.num_qp, int, 0444);
  87. MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
  88. module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
  89. MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
  90. module_param_named(num_cq, hca_profile.num_cq, int, 0444);
  91. MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
  92. module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
  93. MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
  94. module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
  95. MODULE_PARM_DESC(num_mpt,
  96. "maximum number of memory protection table entries per HCA");
  97. module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
  98. MODULE_PARM_DESC(num_mtt,
  99. "maximum number of memory translation table segments per HCA");
  100. module_param_named(num_udav, hca_profile.num_udav, int, 0444);
  101. MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
  102. module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
  103. MODULE_PARM_DESC(fmr_reserved_mtts,
  104. "number of memory translation table segments reserved for FMR");
  105. static int log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8);
  106. module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
  107. MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)");
  108. static char mthca_version[] =
  109. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  110. DRV_VERSION " (" DRV_RELDATE ")\n";
  111. static int mthca_tune_pci(struct mthca_dev *mdev)
  112. {
  113. if (!tune_pci)
  114. return 0;
  115. /* First try to max out Read Byte Count */
  116. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) {
  117. if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) {
  118. mthca_err(mdev, "Couldn't set PCI-X max read count, "
  119. "aborting.\n");
  120. return -ENODEV;
  121. }
  122. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  123. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  124. if (pci_is_pcie(mdev->pdev)) {
  125. if (pcie_set_readrq(mdev->pdev, 4096)) {
  126. mthca_err(mdev, "Couldn't write PCI Express read request, "
  127. "aborting.\n");
  128. return -ENODEV;
  129. }
  130. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  131. mthca_info(mdev, "No PCI Express capability, "
  132. "not setting Max Read Request Size.\n");
  133. return 0;
  134. }
  135. static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  136. {
  137. int err;
  138. mdev->limits.mtt_seg_size = (1 << log_mtts_per_seg) * 8;
  139. err = mthca_QUERY_DEV_LIM(mdev, dev_lim);
  140. if (err) {
  141. mthca_err(mdev, "QUERY_DEV_LIM command returned %d"
  142. ", aborting.\n", err);
  143. return err;
  144. }
  145. if (dev_lim->min_page_sz > PAGE_SIZE) {
  146. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  147. "kernel PAGE_SIZE of %ld, aborting.\n",
  148. dev_lim->min_page_sz, PAGE_SIZE);
  149. return -ENODEV;
  150. }
  151. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  152. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  153. "aborting.\n",
  154. dev_lim->num_ports, MTHCA_MAX_PORTS);
  155. return -ENODEV;
  156. }
  157. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  158. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  159. "PCI resource 2 size of 0x%llx, aborting.\n",
  160. dev_lim->uar_size,
  161. (unsigned long long)pci_resource_len(mdev->pdev, 2));
  162. return -ENODEV;
  163. }
  164. mdev->limits.num_ports = dev_lim->num_ports;
  165. mdev->limits.vl_cap = dev_lim->max_vl;
  166. mdev->limits.mtu_cap = dev_lim->max_mtu;
  167. mdev->limits.gid_table_len = dev_lim->max_gids;
  168. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  169. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  170. /*
  171. * Need to allow for worst case send WQE overhead and check
  172. * whether max_desc_sz imposes a lower limit than max_sg; UD
  173. * send has the biggest overhead.
  174. */
  175. mdev->limits.max_sg = min_t(int, dev_lim->max_sg,
  176. (dev_lim->max_desc_sz -
  177. sizeof (struct mthca_next_seg) -
  178. (mthca_is_memfree(mdev) ?
  179. sizeof (struct mthca_arbel_ud_seg) :
  180. sizeof (struct mthca_tavor_ud_seg))) /
  181. sizeof (struct mthca_data_seg));
  182. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  183. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  184. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  185. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  186. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  187. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  188. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  189. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  190. /*
  191. * Subtract 1 from the limit because we need to allocate a
  192. * spare CQE so the HCA HW can tell the difference between an
  193. * empty CQ and a full CQ.
  194. */
  195. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  196. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  197. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  198. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  199. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  200. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  201. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  202. mdev->limits.port_width_cap = dev_lim->max_port_width;
  203. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  204. mdev->limits.flags = dev_lim->flags;
  205. /*
  206. * For old FW that doesn't return static rate support, use a
  207. * value of 0x3 (only static rate values of 0 or 1 are handled),
  208. * except on Sinai, where even old FW can handle static rate
  209. * values of 2 and 3.
  210. */
  211. if (dev_lim->stat_rate_support)
  212. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  213. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  214. mdev->limits.stat_rate_support = 0xf;
  215. else
  216. mdev->limits.stat_rate_support = 0x3;
  217. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  218. May be doable since hardware supports it for SRQ.
  219. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  220. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  221. supported by driver. */
  222. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  223. IB_DEVICE_PORT_ACTIVE_EVENT |
  224. IB_DEVICE_SYS_IMAGE_GUID |
  225. IB_DEVICE_RC_RNR_NAK_GEN;
  226. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  227. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  228. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  229. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  230. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  231. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  232. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  233. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  234. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  235. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  236. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  237. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  238. if (mthca_is_memfree(mdev))
  239. if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM)
  240. mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  241. return 0;
  242. }
  243. static int mthca_init_tavor(struct mthca_dev *mdev)
  244. {
  245. s64 size;
  246. int err;
  247. struct mthca_dev_lim dev_lim;
  248. struct mthca_profile profile;
  249. struct mthca_init_hca_param init_hca;
  250. err = mthca_SYS_EN(mdev);
  251. if (err) {
  252. mthca_err(mdev, "SYS_EN command returned %d, aborting.\n", err);
  253. return err;
  254. }
  255. err = mthca_QUERY_FW(mdev);
  256. if (err) {
  257. mthca_err(mdev, "QUERY_FW command returned %d,"
  258. " aborting.\n", err);
  259. goto err_disable;
  260. }
  261. err = mthca_QUERY_DDR(mdev);
  262. if (err) {
  263. mthca_err(mdev, "QUERY_DDR command returned %d, aborting.\n", err);
  264. goto err_disable;
  265. }
  266. err = mthca_dev_lim(mdev, &dev_lim);
  267. if (err) {
  268. mthca_err(mdev, "QUERY_DEV_LIM command returned %d, aborting.\n", err);
  269. goto err_disable;
  270. }
  271. profile = hca_profile;
  272. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  273. profile.uarc_size = 0;
  274. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  275. profile.num_srq = dev_lim.max_srqs;
  276. size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  277. if (size < 0) {
  278. err = size;
  279. goto err_disable;
  280. }
  281. err = mthca_INIT_HCA(mdev, &init_hca);
  282. if (err) {
  283. mthca_err(mdev, "INIT_HCA command returned %d, aborting.\n", err);
  284. goto err_disable;
  285. }
  286. return 0;
  287. err_disable:
  288. mthca_SYS_DIS(mdev);
  289. return err;
  290. }
  291. static int mthca_load_fw(struct mthca_dev *mdev)
  292. {
  293. int err;
  294. /* FIXME: use HCA-attached memory for FW if present */
  295. mdev->fw.arbel.fw_icm =
  296. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  297. GFP_HIGHUSER | __GFP_NOWARN, 0);
  298. if (!mdev->fw.arbel.fw_icm) {
  299. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  300. return -ENOMEM;
  301. }
  302. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm);
  303. if (err) {
  304. mthca_err(mdev, "MAP_FA command returned %d, aborting.\n", err);
  305. goto err_free;
  306. }
  307. err = mthca_RUN_FW(mdev);
  308. if (err) {
  309. mthca_err(mdev, "RUN_FW command returned %d, aborting.\n", err);
  310. goto err_unmap_fa;
  311. }
  312. return 0;
  313. err_unmap_fa:
  314. mthca_UNMAP_FA(mdev);
  315. err_free:
  316. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  317. return err;
  318. }
  319. static int mthca_init_icm(struct mthca_dev *mdev,
  320. struct mthca_dev_lim *dev_lim,
  321. struct mthca_init_hca_param *init_hca,
  322. u64 icm_size)
  323. {
  324. u64 aux_pages;
  325. int err;
  326. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages);
  327. if (err) {
  328. mthca_err(mdev, "SET_ICM_SIZE command returned %d, aborting.\n", err);
  329. return err;
  330. }
  331. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  332. (unsigned long long) icm_size >> 10,
  333. (unsigned long long) aux_pages << 2);
  334. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  335. GFP_HIGHUSER | __GFP_NOWARN, 0);
  336. if (!mdev->fw.arbel.aux_icm) {
  337. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  338. return -ENOMEM;
  339. }
  340. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm);
  341. if (err) {
  342. mthca_err(mdev, "MAP_ICM_AUX returned %d, aborting.\n", err);
  343. goto err_free_aux;
  344. }
  345. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  346. if (err) {
  347. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  348. goto err_unmap_aux;
  349. }
  350. /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
  351. mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * mdev->limits.mtt_seg_size,
  352. dma_get_cache_alignment()) / mdev->limits.mtt_seg_size;
  353. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  354. mdev->limits.mtt_seg_size,
  355. mdev->limits.num_mtt_segs,
  356. mdev->limits.reserved_mtts,
  357. 1, 0);
  358. if (!mdev->mr_table.mtt_table) {
  359. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  360. err = -ENOMEM;
  361. goto err_unmap_eq;
  362. }
  363. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  364. dev_lim->mpt_entry_sz,
  365. mdev->limits.num_mpts,
  366. mdev->limits.reserved_mrws,
  367. 1, 1);
  368. if (!mdev->mr_table.mpt_table) {
  369. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  370. err = -ENOMEM;
  371. goto err_unmap_mtt;
  372. }
  373. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  374. dev_lim->qpc_entry_sz,
  375. mdev->limits.num_qps,
  376. mdev->limits.reserved_qps,
  377. 0, 0);
  378. if (!mdev->qp_table.qp_table) {
  379. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  380. err = -ENOMEM;
  381. goto err_unmap_mpt;
  382. }
  383. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  384. dev_lim->eqpc_entry_sz,
  385. mdev->limits.num_qps,
  386. mdev->limits.reserved_qps,
  387. 0, 0);
  388. if (!mdev->qp_table.eqp_table) {
  389. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  390. err = -ENOMEM;
  391. goto err_unmap_qp;
  392. }
  393. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  394. MTHCA_RDB_ENTRY_SIZE,
  395. mdev->limits.num_qps <<
  396. mdev->qp_table.rdb_shift, 0,
  397. 0, 0);
  398. if (!mdev->qp_table.rdb_table) {
  399. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  400. err = -ENOMEM;
  401. goto err_unmap_eqp;
  402. }
  403. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  404. dev_lim->cqc_entry_sz,
  405. mdev->limits.num_cqs,
  406. mdev->limits.reserved_cqs,
  407. 0, 0);
  408. if (!mdev->cq_table.table) {
  409. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  410. err = -ENOMEM;
  411. goto err_unmap_rdb;
  412. }
  413. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  414. mdev->srq_table.table =
  415. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  416. dev_lim->srq_entry_sz,
  417. mdev->limits.num_srqs,
  418. mdev->limits.reserved_srqs,
  419. 0, 0);
  420. if (!mdev->srq_table.table) {
  421. mthca_err(mdev, "Failed to map SRQ context memory, "
  422. "aborting.\n");
  423. err = -ENOMEM;
  424. goto err_unmap_cq;
  425. }
  426. }
  427. /*
  428. * It's not strictly required, but for simplicity just map the
  429. * whole multicast group table now. The table isn't very big
  430. * and it's a lot easier than trying to track ref counts.
  431. */
  432. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  433. MTHCA_MGM_ENTRY_SIZE,
  434. mdev->limits.num_mgms +
  435. mdev->limits.num_amgms,
  436. mdev->limits.num_mgms +
  437. mdev->limits.num_amgms,
  438. 0, 0);
  439. if (!mdev->mcg_table.table) {
  440. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  441. err = -ENOMEM;
  442. goto err_unmap_srq;
  443. }
  444. return 0;
  445. err_unmap_srq:
  446. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  447. mthca_free_icm_table(mdev, mdev->srq_table.table);
  448. err_unmap_cq:
  449. mthca_free_icm_table(mdev, mdev->cq_table.table);
  450. err_unmap_rdb:
  451. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  452. err_unmap_eqp:
  453. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  454. err_unmap_qp:
  455. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  456. err_unmap_mpt:
  457. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  458. err_unmap_mtt:
  459. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  460. err_unmap_eq:
  461. mthca_unmap_eq_icm(mdev);
  462. err_unmap_aux:
  463. mthca_UNMAP_ICM_AUX(mdev);
  464. err_free_aux:
  465. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  466. return err;
  467. }
  468. static void mthca_free_icms(struct mthca_dev *mdev)
  469. {
  470. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  471. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  472. mthca_free_icm_table(mdev, mdev->srq_table.table);
  473. mthca_free_icm_table(mdev, mdev->cq_table.table);
  474. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  475. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  476. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  477. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  478. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  479. mthca_unmap_eq_icm(mdev);
  480. mthca_UNMAP_ICM_AUX(mdev);
  481. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  482. }
  483. static int mthca_init_arbel(struct mthca_dev *mdev)
  484. {
  485. struct mthca_dev_lim dev_lim;
  486. struct mthca_profile profile;
  487. struct mthca_init_hca_param init_hca;
  488. s64 icm_size;
  489. int err;
  490. err = mthca_QUERY_FW(mdev);
  491. if (err) {
  492. mthca_err(mdev, "QUERY_FW command failed %d, aborting.\n", err);
  493. return err;
  494. }
  495. err = mthca_ENABLE_LAM(mdev);
  496. if (err == -EAGAIN) {
  497. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  498. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  499. } else if (err) {
  500. mthca_err(mdev, "ENABLE_LAM returned %d, aborting.\n", err);
  501. return err;
  502. }
  503. err = mthca_load_fw(mdev);
  504. if (err) {
  505. mthca_err(mdev, "Loading FW returned %d, aborting.\n", err);
  506. goto err_disable;
  507. }
  508. err = mthca_dev_lim(mdev, &dev_lim);
  509. if (err) {
  510. mthca_err(mdev, "QUERY_DEV_LIM returned %d, aborting.\n", err);
  511. goto err_stop_fw;
  512. }
  513. profile = hca_profile;
  514. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  515. profile.num_udav = 0;
  516. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  517. profile.num_srq = dev_lim.max_srqs;
  518. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  519. if (icm_size < 0) {
  520. err = icm_size;
  521. goto err_stop_fw;
  522. }
  523. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  524. if (err)
  525. goto err_stop_fw;
  526. err = mthca_INIT_HCA(mdev, &init_hca);
  527. if (err) {
  528. mthca_err(mdev, "INIT_HCA command returned %d, aborting.\n", err);
  529. goto err_free_icm;
  530. }
  531. return 0;
  532. err_free_icm:
  533. mthca_free_icms(mdev);
  534. err_stop_fw:
  535. mthca_UNMAP_FA(mdev);
  536. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  537. err_disable:
  538. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  539. mthca_DISABLE_LAM(mdev);
  540. return err;
  541. }
  542. static void mthca_close_hca(struct mthca_dev *mdev)
  543. {
  544. mthca_CLOSE_HCA(mdev, 0);
  545. if (mthca_is_memfree(mdev)) {
  546. mthca_free_icms(mdev);
  547. mthca_UNMAP_FA(mdev);
  548. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  549. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  550. mthca_DISABLE_LAM(mdev);
  551. } else
  552. mthca_SYS_DIS(mdev);
  553. }
  554. static int mthca_init_hca(struct mthca_dev *mdev)
  555. {
  556. int err;
  557. struct mthca_adapter adapter;
  558. if (mthca_is_memfree(mdev))
  559. err = mthca_init_arbel(mdev);
  560. else
  561. err = mthca_init_tavor(mdev);
  562. if (err)
  563. return err;
  564. err = mthca_QUERY_ADAPTER(mdev, &adapter);
  565. if (err) {
  566. mthca_err(mdev, "QUERY_ADAPTER command returned %d, aborting.\n", err);
  567. goto err_close;
  568. }
  569. mdev->eq_table.inta_pin = adapter.inta_pin;
  570. if (!mthca_is_memfree(mdev))
  571. mdev->rev_id = adapter.revision_id;
  572. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  573. return 0;
  574. err_close:
  575. mthca_close_hca(mdev);
  576. return err;
  577. }
  578. static int mthca_setup_hca(struct mthca_dev *dev)
  579. {
  580. int err;
  581. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  582. err = mthca_init_uar_table(dev);
  583. if (err) {
  584. mthca_err(dev, "Failed to initialize "
  585. "user access region table, aborting.\n");
  586. return err;
  587. }
  588. err = mthca_uar_alloc(dev, &dev->driver_uar);
  589. if (err) {
  590. mthca_err(dev, "Failed to allocate driver access region, "
  591. "aborting.\n");
  592. goto err_uar_table_free;
  593. }
  594. dev->kar = ioremap((phys_addr_t) dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  595. if (!dev->kar) {
  596. mthca_err(dev, "Couldn't map kernel access region, "
  597. "aborting.\n");
  598. err = -ENOMEM;
  599. goto err_uar_free;
  600. }
  601. err = mthca_init_pd_table(dev);
  602. if (err) {
  603. mthca_err(dev, "Failed to initialize "
  604. "protection domain table, aborting.\n");
  605. goto err_kar_unmap;
  606. }
  607. err = mthca_init_mr_table(dev);
  608. if (err) {
  609. mthca_err(dev, "Failed to initialize "
  610. "memory region table, aborting.\n");
  611. goto err_pd_table_free;
  612. }
  613. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  614. if (err) {
  615. mthca_err(dev, "Failed to create driver PD, "
  616. "aborting.\n");
  617. goto err_mr_table_free;
  618. }
  619. err = mthca_init_eq_table(dev);
  620. if (err) {
  621. mthca_err(dev, "Failed to initialize "
  622. "event queue table, aborting.\n");
  623. goto err_pd_free;
  624. }
  625. err = mthca_cmd_use_events(dev);
  626. if (err) {
  627. mthca_err(dev, "Failed to switch to event-driven "
  628. "firmware commands, aborting.\n");
  629. goto err_eq_table_free;
  630. }
  631. err = mthca_NOP(dev);
  632. if (err) {
  633. if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
  634. mthca_warn(dev, "NOP command failed to generate interrupt "
  635. "(IRQ %d).\n",
  636. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector);
  637. mthca_warn(dev, "Trying again with MSI-X disabled.\n");
  638. } else {
  639. mthca_err(dev, "NOP command failed to generate interrupt "
  640. "(IRQ %d), aborting.\n",
  641. dev->pdev->irq);
  642. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  643. }
  644. goto err_cmd_poll;
  645. }
  646. mthca_dbg(dev, "NOP command IRQ test passed\n");
  647. err = mthca_init_cq_table(dev);
  648. if (err) {
  649. mthca_err(dev, "Failed to initialize "
  650. "completion queue table, aborting.\n");
  651. goto err_cmd_poll;
  652. }
  653. err = mthca_init_srq_table(dev);
  654. if (err) {
  655. mthca_err(dev, "Failed to initialize "
  656. "shared receive queue table, aborting.\n");
  657. goto err_cq_table_free;
  658. }
  659. err = mthca_init_qp_table(dev);
  660. if (err) {
  661. mthca_err(dev, "Failed to initialize "
  662. "queue pair table, aborting.\n");
  663. goto err_srq_table_free;
  664. }
  665. err = mthca_init_av_table(dev);
  666. if (err) {
  667. mthca_err(dev, "Failed to initialize "
  668. "address vector table, aborting.\n");
  669. goto err_qp_table_free;
  670. }
  671. err = mthca_init_mcg_table(dev);
  672. if (err) {
  673. mthca_err(dev, "Failed to initialize "
  674. "multicast group table, aborting.\n");
  675. goto err_av_table_free;
  676. }
  677. return 0;
  678. err_av_table_free:
  679. mthca_cleanup_av_table(dev);
  680. err_qp_table_free:
  681. mthca_cleanup_qp_table(dev);
  682. err_srq_table_free:
  683. mthca_cleanup_srq_table(dev);
  684. err_cq_table_free:
  685. mthca_cleanup_cq_table(dev);
  686. err_cmd_poll:
  687. mthca_cmd_use_polling(dev);
  688. err_eq_table_free:
  689. mthca_cleanup_eq_table(dev);
  690. err_pd_free:
  691. mthca_pd_free(dev, &dev->driver_pd);
  692. err_mr_table_free:
  693. mthca_cleanup_mr_table(dev);
  694. err_pd_table_free:
  695. mthca_cleanup_pd_table(dev);
  696. err_kar_unmap:
  697. iounmap(dev->kar);
  698. err_uar_free:
  699. mthca_uar_free(dev, &dev->driver_uar);
  700. err_uar_table_free:
  701. mthca_cleanup_uar_table(dev);
  702. return err;
  703. }
  704. static int mthca_enable_msi_x(struct mthca_dev *mdev)
  705. {
  706. struct msix_entry entries[3];
  707. int err;
  708. entries[0].entry = 0;
  709. entries[1].entry = 1;
  710. entries[2].entry = 2;
  711. err = pci_enable_msix_exact(mdev->pdev, entries, ARRAY_SIZE(entries));
  712. if (err)
  713. return err;
  714. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  715. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  716. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  717. return 0;
  718. }
  719. /* Types of supported HCA */
  720. enum {
  721. TAVOR, /* MT23108 */
  722. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  723. ARBEL_NATIVE, /* MT25208 with extended features */
  724. SINAI /* MT25204 */
  725. };
  726. #define MTHCA_FW_VER(major, minor, subminor) \
  727. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  728. static struct {
  729. u64 latest_fw;
  730. u32 flags;
  731. } mthca_hca_table[] = {
  732. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
  733. .flags = 0 },
  734. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
  735. .flags = MTHCA_FLAG_PCIE },
  736. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0),
  737. .flags = MTHCA_FLAG_MEMFREE |
  738. MTHCA_FLAG_PCIE },
  739. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
  740. .flags = MTHCA_FLAG_MEMFREE |
  741. MTHCA_FLAG_PCIE |
  742. MTHCA_FLAG_SINAI_OPT }
  743. };
  744. static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
  745. {
  746. int ddr_hidden = 0;
  747. int err;
  748. struct mthca_dev *mdev;
  749. printk(KERN_INFO PFX "Initializing %s\n",
  750. pci_name(pdev));
  751. err = pci_enable_device(pdev);
  752. if (err) {
  753. dev_err(&pdev->dev, "Cannot enable PCI device, "
  754. "aborting.\n");
  755. return err;
  756. }
  757. /*
  758. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  759. * be present)
  760. */
  761. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  762. pci_resource_len(pdev, 0) != 1 << 20) {
  763. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  764. err = -ENODEV;
  765. goto err_disable_pdev;
  766. }
  767. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  768. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  769. err = -ENODEV;
  770. goto err_disable_pdev;
  771. }
  772. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  773. ddr_hidden = 1;
  774. err = pci_request_regions(pdev, DRV_NAME);
  775. if (err) {
  776. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  777. "aborting.\n");
  778. goto err_disable_pdev;
  779. }
  780. pci_set_master(pdev);
  781. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  782. if (err) {
  783. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  784. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  785. if (err) {
  786. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  787. goto err_free_res;
  788. }
  789. }
  790. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  791. if (err) {
  792. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  793. "consistent PCI DMA mask.\n");
  794. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  795. if (err) {
  796. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  797. "aborting.\n");
  798. goto err_free_res;
  799. }
  800. }
  801. /* We can handle large RDMA requests, so allow larger segments. */
  802. dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
  803. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  804. if (!mdev) {
  805. dev_err(&pdev->dev, "Device struct alloc failed, "
  806. "aborting.\n");
  807. err = -ENOMEM;
  808. goto err_free_res;
  809. }
  810. mdev->pdev = pdev;
  811. mdev->mthca_flags = mthca_hca_table[hca_type].flags;
  812. if (ddr_hidden)
  813. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  814. /*
  815. * Now reset the HCA before we touch the PCI capabilities or
  816. * attempt a firmware command, since a boot ROM may have left
  817. * the HCA in an undefined state.
  818. */
  819. err = mthca_reset(mdev);
  820. if (err) {
  821. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  822. goto err_free_dev;
  823. }
  824. if (mthca_cmd_init(mdev)) {
  825. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  826. goto err_free_dev;
  827. }
  828. err = mthca_tune_pci(mdev);
  829. if (err)
  830. goto err_cmd;
  831. err = mthca_init_hca(mdev);
  832. if (err)
  833. goto err_cmd;
  834. if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
  835. mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n",
  836. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  837. (int) (mdev->fw_ver & 0xffff),
  838. (int) (mthca_hca_table[hca_type].latest_fw >> 32),
  839. (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
  840. (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
  841. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  842. }
  843. if (msi_x && !mthca_enable_msi_x(mdev))
  844. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  845. err = mthca_setup_hca(mdev);
  846. if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) {
  847. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  848. pci_disable_msix(pdev);
  849. mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X;
  850. err = mthca_setup_hca(mdev);
  851. }
  852. if (err)
  853. goto err_close;
  854. err = mthca_register_device(mdev);
  855. if (err)
  856. goto err_cleanup;
  857. err = mthca_create_agents(mdev);
  858. if (err)
  859. goto err_unregister;
  860. pci_set_drvdata(pdev, mdev);
  861. mdev->hca_type = hca_type;
  862. mdev->active = true;
  863. return 0;
  864. err_unregister:
  865. mthca_unregister_device(mdev);
  866. err_cleanup:
  867. mthca_cleanup_mcg_table(mdev);
  868. mthca_cleanup_av_table(mdev);
  869. mthca_cleanup_qp_table(mdev);
  870. mthca_cleanup_srq_table(mdev);
  871. mthca_cleanup_cq_table(mdev);
  872. mthca_cmd_use_polling(mdev);
  873. mthca_cleanup_eq_table(mdev);
  874. mthca_pd_free(mdev, &mdev->driver_pd);
  875. mthca_cleanup_mr_table(mdev);
  876. mthca_cleanup_pd_table(mdev);
  877. mthca_cleanup_uar_table(mdev);
  878. err_close:
  879. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  880. pci_disable_msix(pdev);
  881. mthca_close_hca(mdev);
  882. err_cmd:
  883. mthca_cmd_cleanup(mdev);
  884. err_free_dev:
  885. ib_dealloc_device(&mdev->ib_dev);
  886. err_free_res:
  887. pci_release_regions(pdev);
  888. err_disable_pdev:
  889. pci_disable_device(pdev);
  890. pci_set_drvdata(pdev, NULL);
  891. return err;
  892. }
  893. static void __mthca_remove_one(struct pci_dev *pdev)
  894. {
  895. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  896. int p;
  897. if (mdev) {
  898. mthca_free_agents(mdev);
  899. mthca_unregister_device(mdev);
  900. for (p = 1; p <= mdev->limits.num_ports; ++p)
  901. mthca_CLOSE_IB(mdev, p);
  902. mthca_cleanup_mcg_table(mdev);
  903. mthca_cleanup_av_table(mdev);
  904. mthca_cleanup_qp_table(mdev);
  905. mthca_cleanup_srq_table(mdev);
  906. mthca_cleanup_cq_table(mdev);
  907. mthca_cmd_use_polling(mdev);
  908. mthca_cleanup_eq_table(mdev);
  909. mthca_pd_free(mdev, &mdev->driver_pd);
  910. mthca_cleanup_mr_table(mdev);
  911. mthca_cleanup_pd_table(mdev);
  912. iounmap(mdev->kar);
  913. mthca_uar_free(mdev, &mdev->driver_uar);
  914. mthca_cleanup_uar_table(mdev);
  915. mthca_close_hca(mdev);
  916. mthca_cmd_cleanup(mdev);
  917. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  918. pci_disable_msix(pdev);
  919. ib_dealloc_device(&mdev->ib_dev);
  920. pci_release_regions(pdev);
  921. pci_disable_device(pdev);
  922. pci_set_drvdata(pdev, NULL);
  923. }
  924. }
  925. int __mthca_restart_one(struct pci_dev *pdev)
  926. {
  927. struct mthca_dev *mdev;
  928. int hca_type;
  929. mdev = pci_get_drvdata(pdev);
  930. if (!mdev)
  931. return -ENODEV;
  932. hca_type = mdev->hca_type;
  933. __mthca_remove_one(pdev);
  934. return __mthca_init_one(pdev, hca_type);
  935. }
  936. static int mthca_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  937. {
  938. int ret;
  939. mutex_lock(&mthca_device_mutex);
  940. printk_once(KERN_INFO "%s", mthca_version);
  941. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  942. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  943. pci_name(pdev), id->driver_data);
  944. mutex_unlock(&mthca_device_mutex);
  945. return -ENODEV;
  946. }
  947. ret = __mthca_init_one(pdev, id->driver_data);
  948. mutex_unlock(&mthca_device_mutex);
  949. return ret;
  950. }
  951. static void mthca_remove_one(struct pci_dev *pdev)
  952. {
  953. mutex_lock(&mthca_device_mutex);
  954. __mthca_remove_one(pdev);
  955. mutex_unlock(&mthca_device_mutex);
  956. }
  957. static struct pci_device_id mthca_pci_table[] = {
  958. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  959. .driver_data = TAVOR },
  960. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  961. .driver_data = TAVOR },
  962. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  963. .driver_data = ARBEL_COMPAT },
  964. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  965. .driver_data = ARBEL_COMPAT },
  966. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  967. .driver_data = ARBEL_NATIVE },
  968. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  969. .driver_data = ARBEL_NATIVE },
  970. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  971. .driver_data = SINAI },
  972. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  973. .driver_data = SINAI },
  974. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  975. .driver_data = SINAI },
  976. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  977. .driver_data = SINAI },
  978. { 0, }
  979. };
  980. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  981. static struct pci_driver mthca_driver = {
  982. .name = DRV_NAME,
  983. .id_table = mthca_pci_table,
  984. .probe = mthca_init_one,
  985. .remove = mthca_remove_one,
  986. };
  987. static void __init __mthca_check_profile_val(const char *name, int *pval,
  988. int pval_default)
  989. {
  990. /* value must be positive and power of 2 */
  991. int old_pval = *pval;
  992. if (old_pval <= 0)
  993. *pval = pval_default;
  994. else
  995. *pval = roundup_pow_of_two(old_pval);
  996. if (old_pval != *pval) {
  997. printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
  998. old_pval, name);
  999. printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
  1000. }
  1001. }
  1002. #define mthca_check_profile_val(name, default) \
  1003. __mthca_check_profile_val(#name, &hca_profile.name, default)
  1004. static void __init mthca_validate_profile(void)
  1005. {
  1006. mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
  1007. mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
  1008. mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
  1009. mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
  1010. mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
  1011. mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
  1012. mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
  1013. mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
  1014. if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
  1015. printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
  1016. hca_profile.fmr_reserved_mtts);
  1017. printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
  1018. hca_profile.num_mtt);
  1019. hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
  1020. printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
  1021. hca_profile.fmr_reserved_mtts);
  1022. }
  1023. if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) {
  1024. printk(KERN_WARNING PFX "bad log_mtts_per_seg (%d). Using default - %d\n",
  1025. log_mtts_per_seg, ilog2(MTHCA_MTT_SEG_SIZE / 8));
  1026. log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8);
  1027. }
  1028. }
  1029. static int __init mthca_init(void)
  1030. {
  1031. int ret;
  1032. mthca_validate_profile();
  1033. ret = mthca_catas_init();
  1034. if (ret)
  1035. return ret;
  1036. ret = pci_register_driver(&mthca_driver);
  1037. if (ret < 0) {
  1038. mthca_catas_cleanup();
  1039. return ret;
  1040. }
  1041. return 0;
  1042. }
  1043. static void __exit mthca_cleanup(void)
  1044. {
  1045. pci_unregister_driver(&mthca_driver);
  1046. mthca_catas_cleanup();
  1047. }
  1048. module_init(mthca_init);
  1049. module_exit(mthca_cleanup);