solos-pci.c 39 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #include <linux/slab.h>
  42. #define VERSION "1.04"
  43. #define DRIVER_VERSION 0x01
  44. #define PTAG "solos-pci"
  45. #define CONFIG_RAM_SIZE 128
  46. #define FLAGS_ADDR 0x7C
  47. #define IRQ_EN_ADDR 0x78
  48. #define FPGA_VER 0x74
  49. #define IRQ_CLEAR 0x70
  50. #define WRITE_FLASH 0x6C
  51. #define PORTS 0x68
  52. #define FLASH_BLOCK 0x64
  53. #define FLASH_BUSY 0x60
  54. #define FPGA_MODE 0x5C
  55. #define FLASH_MODE 0x58
  56. #define GPIO_STATUS 0x54
  57. #define DRIVER_VER 0x50
  58. #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
  59. #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
  60. #define DATA_RAM_SIZE 32768
  61. #define BUF_SIZE 2048
  62. #define OLD_BUF_SIZE 4096 /* For FPGA versions <= 2*/
  63. /* Old boards use ATMEL AD45DB161D flash */
  64. #define ATMEL_FPGA_PAGE 528 /* FPGA flash page size*/
  65. #define ATMEL_SOLOS_PAGE 512 /* Solos flash page size*/
  66. #define ATMEL_FPGA_BLOCK (ATMEL_FPGA_PAGE * 8) /* FPGA block size*/
  67. #define ATMEL_SOLOS_BLOCK (ATMEL_SOLOS_PAGE * 8) /* Solos block size*/
  68. /* Current boards use M25P/M25PE SPI flash */
  69. #define SPI_FLASH_BLOCK (256 * 64)
  70. #define RX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2)
  71. #define TX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2 + (card->buffer_size))
  72. #define FLASH_BUF ((card->buffers) + 4*(card->buffer_size)*2)
  73. #define RX_DMA_SIZE 2048
  74. #define FPGA_VERSION(a,b) (((a) << 8) + (b))
  75. #define LEGACY_BUFFERS 2
  76. #define DMA_SUPPORTED 4
  77. static int reset = 0;
  78. static int atmdebug = 0;
  79. static int firmware_upgrade = 0;
  80. static int fpga_upgrade = 0;
  81. static int db_firmware_upgrade = 0;
  82. static int db_fpga_upgrade = 0;
  83. struct pkt_hdr {
  84. __le16 size;
  85. __le16 vpi;
  86. __le16 vci;
  87. __le16 type;
  88. };
  89. struct solos_skb_cb {
  90. struct atm_vcc *vcc;
  91. uint32_t dma_addr;
  92. };
  93. #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
  94. #define PKT_DATA 0
  95. #define PKT_COMMAND 1
  96. #define PKT_POPEN 3
  97. #define PKT_PCLOSE 4
  98. #define PKT_STATUS 5
  99. struct solos_card {
  100. void __iomem *config_regs;
  101. void __iomem *buffers;
  102. int nr_ports;
  103. int tx_mask;
  104. struct pci_dev *dev;
  105. struct atm_dev *atmdev[4];
  106. struct tasklet_struct tlet;
  107. spinlock_t tx_lock;
  108. spinlock_t tx_queue_lock;
  109. spinlock_t cli_queue_lock;
  110. spinlock_t param_queue_lock;
  111. struct list_head param_queue;
  112. struct sk_buff_head tx_queue[4];
  113. struct sk_buff_head cli_queue[4];
  114. struct sk_buff *tx_skb[4];
  115. struct sk_buff *rx_skb[4];
  116. unsigned char *dma_bounce;
  117. wait_queue_head_t param_wq;
  118. wait_queue_head_t fw_wq;
  119. int using_dma;
  120. int dma_alignment;
  121. int fpga_version;
  122. int buffer_size;
  123. int atmel_flash;
  124. };
  125. struct solos_param {
  126. struct list_head list;
  127. pid_t pid;
  128. int port;
  129. struct sk_buff *response;
  130. };
  131. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  132. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  133. MODULE_DESCRIPTION("Solos PCI driver");
  134. MODULE_VERSION(VERSION);
  135. MODULE_LICENSE("GPL");
  136. /*(DEBLOBBED)*/
  137. MODULE_PARM_DESC(reset, "Reset Solos chips on startup");
  138. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  139. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  140. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  141. MODULE_PARM_DESC(db_firmware_upgrade, "Initiate daughter board Solos firmware upgrade");
  142. MODULE_PARM_DESC(db_fpga_upgrade, "Initiate daughter board FPGA upgrade");
  143. module_param(reset, int, 0444);
  144. module_param(atmdebug, int, 0644);
  145. module_param(firmware_upgrade, int, 0444);
  146. module_param(fpga_upgrade, int, 0444);
  147. module_param(db_firmware_upgrade, int, 0444);
  148. module_param(db_fpga_upgrade, int, 0444);
  149. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  150. struct atm_vcc *vcc);
  151. static uint32_t fpga_tx(struct solos_card *);
  152. static irqreturn_t solos_irq(int irq, void *dev_id);
  153. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  154. static int atm_init(struct solos_card *, struct device *);
  155. static void atm_remove(struct solos_card *);
  156. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  157. static void solos_bh(unsigned long);
  158. static int print_buffer(struct sk_buff *buf);
  159. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  160. {
  161. if (vcc->pop)
  162. vcc->pop(vcc, skb);
  163. else
  164. dev_kfree_skb_any(skb);
  165. }
  166. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  167. char *buf)
  168. {
  169. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  170. struct solos_card *card = atmdev->dev_data;
  171. struct solos_param prm;
  172. struct sk_buff *skb;
  173. struct pkt_hdr *header;
  174. int buflen;
  175. buflen = strlen(attr->attr.name) + 10;
  176. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  177. if (!skb) {
  178. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  179. return -ENOMEM;
  180. }
  181. header = (void *)skb_put(skb, sizeof(*header));
  182. buflen = snprintf((void *)&header[1], buflen - 1,
  183. "L%05d\n%s\n", current->pid, attr->attr.name);
  184. skb_put(skb, buflen);
  185. header->size = cpu_to_le16(buflen);
  186. header->vpi = cpu_to_le16(0);
  187. header->vci = cpu_to_le16(0);
  188. header->type = cpu_to_le16(PKT_COMMAND);
  189. prm.pid = current->pid;
  190. prm.response = NULL;
  191. prm.port = SOLOS_CHAN(atmdev);
  192. spin_lock_irq(&card->param_queue_lock);
  193. list_add(&prm.list, &card->param_queue);
  194. spin_unlock_irq(&card->param_queue_lock);
  195. fpga_queue(card, prm.port, skb, NULL);
  196. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  197. spin_lock_irq(&card->param_queue_lock);
  198. list_del(&prm.list);
  199. spin_unlock_irq(&card->param_queue_lock);
  200. if (!prm.response)
  201. return -EIO;
  202. buflen = prm.response->len;
  203. memcpy(buf, prm.response->data, buflen);
  204. kfree_skb(prm.response);
  205. return buflen;
  206. }
  207. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  208. const char *buf, size_t count)
  209. {
  210. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  211. struct solos_card *card = atmdev->dev_data;
  212. struct solos_param prm;
  213. struct sk_buff *skb;
  214. struct pkt_hdr *header;
  215. int buflen;
  216. ssize_t ret;
  217. buflen = strlen(attr->attr.name) + 11 + count;
  218. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  219. if (!skb) {
  220. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  221. return -ENOMEM;
  222. }
  223. header = (void *)skb_put(skb, sizeof(*header));
  224. buflen = snprintf((void *)&header[1], buflen - 1,
  225. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  226. skb_put(skb, buflen);
  227. header->size = cpu_to_le16(buflen);
  228. header->vpi = cpu_to_le16(0);
  229. header->vci = cpu_to_le16(0);
  230. header->type = cpu_to_le16(PKT_COMMAND);
  231. prm.pid = current->pid;
  232. prm.response = NULL;
  233. prm.port = SOLOS_CHAN(atmdev);
  234. spin_lock_irq(&card->param_queue_lock);
  235. list_add(&prm.list, &card->param_queue);
  236. spin_unlock_irq(&card->param_queue_lock);
  237. fpga_queue(card, prm.port, skb, NULL);
  238. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  239. spin_lock_irq(&card->param_queue_lock);
  240. list_del(&prm.list);
  241. spin_unlock_irq(&card->param_queue_lock);
  242. skb = prm.response;
  243. if (!skb)
  244. return -EIO;
  245. buflen = skb->len;
  246. /* Sometimes it has a newline, sometimes it doesn't. */
  247. if (skb->data[buflen - 1] == '\n')
  248. buflen--;
  249. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  250. ret = count;
  251. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  252. ret = -EIO;
  253. else {
  254. /* We know we have enough space allocated for this; we allocated
  255. it ourselves */
  256. skb->data[buflen] = 0;
  257. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  258. skb->data);
  259. ret = -EIO;
  260. }
  261. kfree_skb(skb);
  262. return ret;
  263. }
  264. static char *next_string(struct sk_buff *skb)
  265. {
  266. int i = 0;
  267. char *this = skb->data;
  268. for (i = 0; i < skb->len; i++) {
  269. if (this[i] == '\n') {
  270. this[i] = 0;
  271. skb_pull(skb, i + 1);
  272. return this;
  273. }
  274. if (!isprint(this[i]))
  275. return NULL;
  276. }
  277. return NULL;
  278. }
  279. /*
  280. * Status packet has fields separated by \n, starting with a version number
  281. * for the information therein. Fields are....
  282. *
  283. * packet version
  284. * RxBitRate (version >= 1)
  285. * TxBitRate (version >= 1)
  286. * State (version >= 1)
  287. * LocalSNRMargin (version >= 1)
  288. * LocalLineAttn (version >= 1)
  289. */
  290. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  291. {
  292. char *str, *state_str, *snr, *attn;
  293. int ver, rate_up, rate_down, err;
  294. if (!card->atmdev[port])
  295. return -ENODEV;
  296. str = next_string(skb);
  297. if (!str)
  298. return -EIO;
  299. err = kstrtoint(str, 10, &ver);
  300. if (err) {
  301. dev_warn(&card->dev->dev, "Unexpected status interrupt version\n");
  302. return err;
  303. }
  304. if (ver < 1) {
  305. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  306. ver);
  307. return -EIO;
  308. }
  309. str = next_string(skb);
  310. if (!str)
  311. return -EIO;
  312. if (!strcmp(str, "ERROR")) {
  313. dev_dbg(&card->dev->dev, "Status packet indicated Solos error on port %d (starting up?)\n",
  314. port);
  315. return 0;
  316. }
  317. err = kstrtoint(str, 10, &rate_down);
  318. if (err)
  319. return err;
  320. str = next_string(skb);
  321. if (!str)
  322. return -EIO;
  323. err = kstrtoint(str, 10, &rate_up);
  324. if (err)
  325. return err;
  326. state_str = next_string(skb);
  327. if (!state_str)
  328. return -EIO;
  329. /* Anything but 'Showtime' is down */
  330. if (strcmp(state_str, "Showtime")) {
  331. atm_dev_signal_change(card->atmdev[port], ATM_PHY_SIG_LOST);
  332. dev_info(&card->dev->dev, "Port %d: %s\n", port, state_str);
  333. return 0;
  334. }
  335. snr = next_string(skb);
  336. if (!snr)
  337. return -EIO;
  338. attn = next_string(skb);
  339. if (!attn)
  340. return -EIO;
  341. dev_info(&card->dev->dev, "Port %d: %s @%d/%d kb/s%s%s%s%s\n",
  342. port, state_str, rate_down/1000, rate_up/1000,
  343. snr[0]?", SNR ":"", snr, attn[0]?", Attn ":"", attn);
  344. card->atmdev[port]->link_rate = rate_down / 424;
  345. atm_dev_signal_change(card->atmdev[port], ATM_PHY_SIG_FOUND);
  346. return 0;
  347. }
  348. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  349. {
  350. struct solos_param *prm;
  351. unsigned long flags;
  352. int cmdpid;
  353. int found = 0, err;
  354. if (skb->len < 7)
  355. return 0;
  356. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  357. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  358. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  359. skb->data[6] != '\n')
  360. return 0;
  361. err = kstrtoint(&skb->data[1], 10, &cmdpid);
  362. if (err)
  363. return err;
  364. spin_lock_irqsave(&card->param_queue_lock, flags);
  365. list_for_each_entry(prm, &card->param_queue, list) {
  366. if (prm->port == port && prm->pid == cmdpid) {
  367. prm->response = skb;
  368. skb_pull(skb, 7);
  369. wake_up(&card->param_wq);
  370. found = 1;
  371. break;
  372. }
  373. }
  374. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  375. return found;
  376. }
  377. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  378. char *buf)
  379. {
  380. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  381. struct solos_card *card = atmdev->dev_data;
  382. struct sk_buff *skb;
  383. unsigned int len;
  384. spin_lock(&card->cli_queue_lock);
  385. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  386. spin_unlock(&card->cli_queue_lock);
  387. if(skb == NULL)
  388. return sprintf(buf, "No data.\n");
  389. len = skb->len;
  390. memcpy(buf, skb->data, len);
  391. kfree_skb(skb);
  392. return len;
  393. }
  394. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  395. {
  396. struct sk_buff *skb;
  397. struct pkt_hdr *header;
  398. if (size > (BUF_SIZE - sizeof(*header))) {
  399. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  400. return 0;
  401. }
  402. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  403. if (!skb) {
  404. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  405. return 0;
  406. }
  407. header = (void *)skb_put(skb, sizeof(*header));
  408. header->size = cpu_to_le16(size);
  409. header->vpi = cpu_to_le16(0);
  410. header->vci = cpu_to_le16(0);
  411. header->type = cpu_to_le16(PKT_COMMAND);
  412. memcpy(skb_put(skb, size), buf, size);
  413. fpga_queue(card, dev, skb, NULL);
  414. return 0;
  415. }
  416. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  417. const char *buf, size_t count)
  418. {
  419. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  420. struct solos_card *card = atmdev->dev_data;
  421. int err;
  422. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  423. return err?:count;
  424. }
  425. struct geos_gpio_attr {
  426. struct device_attribute attr;
  427. int offset;
  428. };
  429. #define SOLOS_GPIO_ATTR(_name, _mode, _show, _store, _offset) \
  430. struct geos_gpio_attr gpio_attr_##_name = { \
  431. .attr = __ATTR(_name, _mode, _show, _store), \
  432. .offset = _offset }
  433. static ssize_t geos_gpio_store(struct device *dev, struct device_attribute *attr,
  434. const char *buf, size_t count)
  435. {
  436. struct pci_dev *pdev = to_pci_dev(dev);
  437. struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);
  438. struct solos_card *card = pci_get_drvdata(pdev);
  439. uint32_t data32;
  440. if (count != 1 && (count != 2 || buf[1] != '\n'))
  441. return -EINVAL;
  442. spin_lock_irq(&card->param_queue_lock);
  443. data32 = ioread32(card->config_regs + GPIO_STATUS);
  444. if (buf[0] == '1') {
  445. data32 |= 1 << gattr->offset;
  446. iowrite32(data32, card->config_regs + GPIO_STATUS);
  447. } else if (buf[0] == '0') {
  448. data32 &= ~(1 << gattr->offset);
  449. iowrite32(data32, card->config_regs + GPIO_STATUS);
  450. } else {
  451. count = -EINVAL;
  452. }
  453. spin_unlock_irq(&card->param_queue_lock);
  454. return count;
  455. }
  456. static ssize_t geos_gpio_show(struct device *dev, struct device_attribute *attr,
  457. char *buf)
  458. {
  459. struct pci_dev *pdev = to_pci_dev(dev);
  460. struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);
  461. struct solos_card *card = pci_get_drvdata(pdev);
  462. uint32_t data32;
  463. data32 = ioread32(card->config_regs + GPIO_STATUS);
  464. data32 = (data32 >> gattr->offset) & 1;
  465. return sprintf(buf, "%d\n", data32);
  466. }
  467. static ssize_t hardware_show(struct device *dev, struct device_attribute *attr,
  468. char *buf)
  469. {
  470. struct pci_dev *pdev = to_pci_dev(dev);
  471. struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);
  472. struct solos_card *card = pci_get_drvdata(pdev);
  473. uint32_t data32;
  474. data32 = ioread32(card->config_regs + GPIO_STATUS);
  475. switch (gattr->offset) {
  476. case 0:
  477. /* HardwareVersion */
  478. data32 = data32 & 0x1F;
  479. break;
  480. case 1:
  481. /* HardwareVariant */
  482. data32 = (data32 >> 5) & 0x0F;
  483. break;
  484. }
  485. return sprintf(buf, "%d\n", data32);
  486. }
  487. static DEVICE_ATTR(console, 0644, console_show, console_store);
  488. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  489. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  490. #include "solos-attrlist.c"
  491. static SOLOS_GPIO_ATTR(GPIO1, 0644, geos_gpio_show, geos_gpio_store, 9);
  492. static SOLOS_GPIO_ATTR(GPIO2, 0644, geos_gpio_show, geos_gpio_store, 10);
  493. static SOLOS_GPIO_ATTR(GPIO3, 0644, geos_gpio_show, geos_gpio_store, 11);
  494. static SOLOS_GPIO_ATTR(GPIO4, 0644, geos_gpio_show, geos_gpio_store, 12);
  495. static SOLOS_GPIO_ATTR(GPIO5, 0644, geos_gpio_show, geos_gpio_store, 13);
  496. static SOLOS_GPIO_ATTR(PushButton, 0444, geos_gpio_show, NULL, 14);
  497. static SOLOS_GPIO_ATTR(HardwareVersion, 0444, hardware_show, NULL, 0);
  498. static SOLOS_GPIO_ATTR(HardwareVariant, 0444, hardware_show, NULL, 1);
  499. #undef SOLOS_ATTR_RO
  500. #undef SOLOS_ATTR_RW
  501. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  502. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  503. static struct attribute *solos_attrs[] = {
  504. #include "solos-attrlist.c"
  505. NULL
  506. };
  507. static struct attribute_group solos_attr_group = {
  508. .attrs = solos_attrs,
  509. .name = "parameters",
  510. };
  511. static struct attribute *gpio_attrs[] = {
  512. &gpio_attr_GPIO1.attr.attr,
  513. &gpio_attr_GPIO2.attr.attr,
  514. &gpio_attr_GPIO3.attr.attr,
  515. &gpio_attr_GPIO4.attr.attr,
  516. &gpio_attr_GPIO5.attr.attr,
  517. &gpio_attr_PushButton.attr.attr,
  518. &gpio_attr_HardwareVersion.attr.attr,
  519. &gpio_attr_HardwareVariant.attr.attr,
  520. NULL
  521. };
  522. static struct attribute_group gpio_attr_group = {
  523. .attrs = gpio_attrs,
  524. .name = "gpio",
  525. };
  526. static int flash_upgrade(struct solos_card *card, int chip)
  527. {
  528. const struct firmware *fw;
  529. const char *fw_name;
  530. int blocksize = 0;
  531. int numblocks = 0;
  532. int offset;
  533. switch (chip) {
  534. case 0:
  535. fw_name = "/*(DEBLOBBED)*/";
  536. if (card->atmel_flash)
  537. blocksize = ATMEL_FPGA_BLOCK;
  538. else
  539. blocksize = SPI_FLASH_BLOCK;
  540. break;
  541. case 1:
  542. fw_name = "/*(DEBLOBBED)*/";
  543. if (card->atmel_flash)
  544. blocksize = ATMEL_SOLOS_BLOCK;
  545. else
  546. blocksize = SPI_FLASH_BLOCK;
  547. break;
  548. case 2:
  549. if (card->fpga_version > LEGACY_BUFFERS){
  550. fw_name = "/*(DEBLOBBED)*/";
  551. if (card->atmel_flash)
  552. blocksize = ATMEL_FPGA_BLOCK;
  553. else
  554. blocksize = SPI_FLASH_BLOCK;
  555. } else {
  556. dev_info(&card->dev->dev, "FPGA version doesn't support"
  557. " daughter board upgrades\n");
  558. return -EPERM;
  559. }
  560. break;
  561. case 3:
  562. if (card->fpga_version > LEGACY_BUFFERS){
  563. fw_name = "/*(DEBLOBBED)*/";
  564. if (card->atmel_flash)
  565. blocksize = ATMEL_SOLOS_BLOCK;
  566. else
  567. blocksize = SPI_FLASH_BLOCK;
  568. } else {
  569. dev_info(&card->dev->dev, "FPGA version doesn't support"
  570. " daughter board upgrades\n");
  571. return -EPERM;
  572. }
  573. break;
  574. default:
  575. return -ENODEV;
  576. }
  577. if (reject_firmware(&fw, fw_name, &card->dev->dev))
  578. return -ENOENT;
  579. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  580. /* New FPGAs require driver version before permitting flash upgrades */
  581. iowrite32(DRIVER_VERSION, card->config_regs + DRIVER_VER);
  582. numblocks = fw->size / blocksize;
  583. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  584. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  585. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  586. iowrite32(1, card->config_regs + FPGA_MODE);
  587. (void) ioread32(card->config_regs + FPGA_MODE);
  588. /* Set mode to Chip Erase */
  589. if(chip == 0 || chip == 2)
  590. dev_info(&card->dev->dev, "Set FPGA Flash mode to FPGA Chip Erase\n");
  591. if(chip == 1 || chip == 3)
  592. dev_info(&card->dev->dev, "Set FPGA Flash mode to Solos Chip Erase\n");
  593. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  594. iowrite32(1, card->config_regs + WRITE_FLASH);
  595. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  596. for (offset = 0; offset < fw->size; offset += blocksize) {
  597. int i;
  598. /* Clear write flag */
  599. iowrite32(0, card->config_regs + WRITE_FLASH);
  600. /* Set mode to Block Write */
  601. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  602. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  603. /* Copy block to buffer, swapping each 16 bits for Atmel flash */
  604. for(i = 0; i < blocksize; i += 4) {
  605. uint32_t word;
  606. if (card->atmel_flash)
  607. word = swahb32p((uint32_t *)(fw->data + offset + i));
  608. else
  609. word = *(uint32_t *)(fw->data + offset + i);
  610. if(card->fpga_version > LEGACY_BUFFERS)
  611. iowrite32(word, FLASH_BUF + i);
  612. else
  613. iowrite32(word, RX_BUF(card, 3) + i);
  614. }
  615. /* Specify block number and then trigger flash write */
  616. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  617. iowrite32(1, card->config_regs + WRITE_FLASH);
  618. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  619. }
  620. release_firmware(fw);
  621. iowrite32(0, card->config_regs + WRITE_FLASH);
  622. iowrite32(0, card->config_regs + FPGA_MODE);
  623. iowrite32(0, card->config_regs + FLASH_MODE);
  624. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  625. return 0;
  626. }
  627. static irqreturn_t solos_irq(int irq, void *dev_id)
  628. {
  629. struct solos_card *card = dev_id;
  630. int handled = 1;
  631. iowrite32(0, card->config_regs + IRQ_CLEAR);
  632. /* If we're up and running, just kick the tasklet to process TX/RX */
  633. if (card->atmdev[0])
  634. tasklet_schedule(&card->tlet);
  635. else
  636. wake_up(&card->fw_wq);
  637. return IRQ_RETVAL(handled);
  638. }
  639. static void solos_bh(unsigned long card_arg)
  640. {
  641. struct solos_card *card = (void *)card_arg;
  642. uint32_t card_flags;
  643. uint32_t rx_done = 0;
  644. int port;
  645. /*
  646. * Since fpga_tx() is going to need to read the flags under its lock,
  647. * it can return them to us so that we don't have to hit PCI MMIO
  648. * again for the same information
  649. */
  650. card_flags = fpga_tx(card);
  651. for (port = 0; port < card->nr_ports; port++) {
  652. if (card_flags & (0x10 << port)) {
  653. struct pkt_hdr _hdr, *header;
  654. struct sk_buff *skb;
  655. struct atm_vcc *vcc;
  656. int size;
  657. if (card->using_dma) {
  658. skb = card->rx_skb[port];
  659. card->rx_skb[port] = NULL;
  660. dma_unmap_single(&card->dev->dev, SKB_CB(skb)->dma_addr,
  661. RX_DMA_SIZE, DMA_FROM_DEVICE);
  662. header = (void *)skb->data;
  663. size = le16_to_cpu(header->size);
  664. skb_put(skb, size + sizeof(*header));
  665. skb_pull(skb, sizeof(*header));
  666. } else {
  667. header = &_hdr;
  668. rx_done |= 0x10 << port;
  669. memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
  670. size = le16_to_cpu(header->size);
  671. if (size > (card->buffer_size - sizeof(*header))){
  672. dev_warn(&card->dev->dev, "Invalid buffer size\n");
  673. continue;
  674. }
  675. /* Use netdev_alloc_skb() because it adds NET_SKB_PAD of
  676. * headroom, and ensures we can route packets back out an
  677. * Ethernet interface (for example) without having to
  678. * reallocate. Adding NET_IP_ALIGN also ensures that both
  679. * PPPoATM and PPPoEoBR2684 packets end up aligned. */
  680. skb = netdev_alloc_skb_ip_align(NULL, size + 1);
  681. if (!skb) {
  682. if (net_ratelimit())
  683. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  684. continue;
  685. }
  686. memcpy_fromio(skb_put(skb, size),
  687. RX_BUF(card, port) + sizeof(*header),
  688. size);
  689. }
  690. if (atmdebug) {
  691. dev_info(&card->dev->dev, "Received: port %d\n", port);
  692. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  693. size, le16_to_cpu(header->vpi),
  694. le16_to_cpu(header->vci));
  695. print_buffer(skb);
  696. }
  697. switch (le16_to_cpu(header->type)) {
  698. case PKT_DATA:
  699. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
  700. le16_to_cpu(header->vci));
  701. if (!vcc) {
  702. if (net_ratelimit())
  703. dev_warn(&card->dev->dev, "Received packet for unknown VPI.VCI %d.%d on port %d\n",
  704. le16_to_cpu(header->vpi), le16_to_cpu(header->vci),
  705. port);
  706. dev_kfree_skb_any(skb);
  707. break;
  708. }
  709. atm_charge(vcc, skb->truesize);
  710. vcc->push(vcc, skb);
  711. atomic_inc(&vcc->stats->rx);
  712. break;
  713. case PKT_STATUS:
  714. if (process_status(card, port, skb) &&
  715. net_ratelimit()) {
  716. dev_warn(&card->dev->dev, "Bad status packet of %d bytes on port %d:\n", skb->len, port);
  717. print_buffer(skb);
  718. }
  719. dev_kfree_skb_any(skb);
  720. break;
  721. case PKT_COMMAND:
  722. default: /* FIXME: Not really, surely? */
  723. if (process_command(card, port, skb))
  724. break;
  725. spin_lock(&card->cli_queue_lock);
  726. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  727. if (net_ratelimit())
  728. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  729. port);
  730. dev_kfree_skb_any(skb);
  731. } else
  732. skb_queue_tail(&card->cli_queue[port], skb);
  733. spin_unlock(&card->cli_queue_lock);
  734. break;
  735. }
  736. }
  737. /* Allocate RX skbs for any ports which need them */
  738. if (card->using_dma && card->atmdev[port] &&
  739. !card->rx_skb[port]) {
  740. /* Unlike the MMIO case (qv) we can't add NET_IP_ALIGN
  741. * here; the FPGA can only DMA to addresses which are
  742. * aligned to 4 bytes. */
  743. struct sk_buff *skb = dev_alloc_skb(RX_DMA_SIZE);
  744. if (skb) {
  745. SKB_CB(skb)->dma_addr =
  746. dma_map_single(&card->dev->dev, skb->data,
  747. RX_DMA_SIZE, DMA_FROM_DEVICE);
  748. iowrite32(SKB_CB(skb)->dma_addr,
  749. card->config_regs + RX_DMA_ADDR(port));
  750. card->rx_skb[port] = skb;
  751. } else {
  752. if (net_ratelimit())
  753. dev_warn(&card->dev->dev, "Failed to allocate RX skb");
  754. /* We'll have to try again later */
  755. tasklet_schedule(&card->tlet);
  756. }
  757. }
  758. }
  759. if (rx_done)
  760. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  761. return;
  762. }
  763. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  764. {
  765. struct hlist_head *head;
  766. struct atm_vcc *vcc = NULL;
  767. struct sock *s;
  768. read_lock(&vcc_sklist_lock);
  769. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  770. sk_for_each(s, head) {
  771. vcc = atm_sk(s);
  772. if (vcc->dev == dev && vcc->vci == vci &&
  773. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE &&
  774. test_bit(ATM_VF_READY, &vcc->flags))
  775. goto out;
  776. }
  777. vcc = NULL;
  778. out:
  779. read_unlock(&vcc_sklist_lock);
  780. return vcc;
  781. }
  782. static int popen(struct atm_vcc *vcc)
  783. {
  784. struct solos_card *card = vcc->dev->dev_data;
  785. struct sk_buff *skb;
  786. struct pkt_hdr *header;
  787. if (vcc->qos.aal != ATM_AAL5) {
  788. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  789. vcc->qos.aal);
  790. return -EINVAL;
  791. }
  792. skb = alloc_skb(sizeof(*header), GFP_KERNEL);
  793. if (!skb) {
  794. if (net_ratelimit())
  795. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  796. return -ENOMEM;
  797. }
  798. header = (void *)skb_put(skb, sizeof(*header));
  799. header->size = cpu_to_le16(0);
  800. header->vpi = cpu_to_le16(vcc->vpi);
  801. header->vci = cpu_to_le16(vcc->vci);
  802. header->type = cpu_to_le16(PKT_POPEN);
  803. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  804. set_bit(ATM_VF_ADDR, &vcc->flags);
  805. set_bit(ATM_VF_READY, &vcc->flags);
  806. return 0;
  807. }
  808. static void pclose(struct atm_vcc *vcc)
  809. {
  810. struct solos_card *card = vcc->dev->dev_data;
  811. unsigned char port = SOLOS_CHAN(vcc->dev);
  812. struct sk_buff *skb, *tmpskb;
  813. struct pkt_hdr *header;
  814. /* Remove any yet-to-be-transmitted packets from the pending queue */
  815. spin_lock(&card->tx_queue_lock);
  816. skb_queue_walk_safe(&card->tx_queue[port], skb, tmpskb) {
  817. if (SKB_CB(skb)->vcc == vcc) {
  818. skb_unlink(skb, &card->tx_queue[port]);
  819. solos_pop(vcc, skb);
  820. }
  821. }
  822. spin_unlock(&card->tx_queue_lock);
  823. skb = alloc_skb(sizeof(*header), GFP_KERNEL);
  824. if (!skb) {
  825. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  826. return;
  827. }
  828. header = (void *)skb_put(skb, sizeof(*header));
  829. header->size = cpu_to_le16(0);
  830. header->vpi = cpu_to_le16(vcc->vpi);
  831. header->vci = cpu_to_le16(vcc->vci);
  832. header->type = cpu_to_le16(PKT_PCLOSE);
  833. skb_get(skb);
  834. fpga_queue(card, port, skb, NULL);
  835. if (!wait_event_timeout(card->param_wq, !skb_shared(skb), 5 * HZ))
  836. dev_warn(&card->dev->dev,
  837. "Timeout waiting for VCC close on port %d\n", port);
  838. dev_kfree_skb(skb);
  839. /* Hold up vcc_destroy_socket() (our caller) until solos_bh() in the
  840. tasklet has finished processing any incoming packets (and, more to
  841. the point, using the vcc pointer). */
  842. tasklet_unlock_wait(&card->tlet);
  843. clear_bit(ATM_VF_ADDR, &vcc->flags);
  844. return;
  845. }
  846. static int print_buffer(struct sk_buff *buf)
  847. {
  848. int len,i;
  849. char msg[500];
  850. char item[10];
  851. len = buf->len;
  852. for (i = 0; i < len; i++){
  853. if(i % 8 == 0)
  854. sprintf(msg, "%02X: ", i);
  855. sprintf(item,"%02X ",*(buf->data + i));
  856. strcat(msg, item);
  857. if(i % 8 == 7) {
  858. sprintf(item, "\n");
  859. strcat(msg, item);
  860. printk(KERN_DEBUG "%s", msg);
  861. }
  862. }
  863. if (i % 8 != 0) {
  864. sprintf(item, "\n");
  865. strcat(msg, item);
  866. printk(KERN_DEBUG "%s", msg);
  867. }
  868. printk(KERN_DEBUG "\n");
  869. return 0;
  870. }
  871. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  872. struct atm_vcc *vcc)
  873. {
  874. int old_len;
  875. unsigned long flags;
  876. SKB_CB(skb)->vcc = vcc;
  877. spin_lock_irqsave(&card->tx_queue_lock, flags);
  878. old_len = skb_queue_len(&card->tx_queue[port]);
  879. skb_queue_tail(&card->tx_queue[port], skb);
  880. if (!old_len)
  881. card->tx_mask |= (1 << port);
  882. spin_unlock_irqrestore(&card->tx_queue_lock, flags);
  883. /* Theoretically we could just schedule the tasklet here, but
  884. that introduces latency we don't want -- it's noticeable */
  885. if (!old_len)
  886. fpga_tx(card);
  887. }
  888. static uint32_t fpga_tx(struct solos_card *card)
  889. {
  890. uint32_t tx_pending, card_flags;
  891. uint32_t tx_started = 0;
  892. struct sk_buff *skb;
  893. struct atm_vcc *vcc;
  894. unsigned char port;
  895. unsigned long flags;
  896. spin_lock_irqsave(&card->tx_lock, flags);
  897. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  898. /*
  899. * The queue lock is required for _writing_ to tx_mask, but we're
  900. * OK to read it here without locking. The only potential update
  901. * that we could race with is in fpga_queue() where it sets a bit
  902. * for a new port... but it's going to call this function again if
  903. * it's doing that, anyway.
  904. */
  905. tx_pending = card->tx_mask & ~card_flags;
  906. for (port = 0; tx_pending; tx_pending >>= 1, port++) {
  907. if (tx_pending & 1) {
  908. struct sk_buff *oldskb = card->tx_skb[port];
  909. if (oldskb) {
  910. dma_unmap_single(&card->dev->dev, SKB_CB(oldskb)->dma_addr,
  911. oldskb->len, DMA_TO_DEVICE);
  912. card->tx_skb[port] = NULL;
  913. }
  914. spin_lock(&card->tx_queue_lock);
  915. skb = skb_dequeue(&card->tx_queue[port]);
  916. if (!skb)
  917. card->tx_mask &= ~(1 << port);
  918. spin_unlock(&card->tx_queue_lock);
  919. if (skb && !card->using_dma) {
  920. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  921. tx_started |= 1 << port;
  922. oldskb = skb; /* We're done with this skb already */
  923. } else if (skb && card->using_dma) {
  924. unsigned char *data = skb->data;
  925. if ((unsigned long)data & card->dma_alignment) {
  926. data = card->dma_bounce + (BUF_SIZE * port);
  927. memcpy(data, skb->data, skb->len);
  928. }
  929. SKB_CB(skb)->dma_addr = dma_map_single(&card->dev->dev, data,
  930. skb->len, DMA_TO_DEVICE);
  931. card->tx_skb[port] = skb;
  932. iowrite32(SKB_CB(skb)->dma_addr,
  933. card->config_regs + TX_DMA_ADDR(port));
  934. }
  935. if (!oldskb)
  936. continue;
  937. /* Clean up and free oldskb now it's gone */
  938. if (atmdebug) {
  939. struct pkt_hdr *header = (void *)oldskb->data;
  940. int size = le16_to_cpu(header->size);
  941. skb_pull(oldskb, sizeof(*header));
  942. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  943. port);
  944. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  945. size, le16_to_cpu(header->vpi),
  946. le16_to_cpu(header->vci));
  947. print_buffer(oldskb);
  948. }
  949. vcc = SKB_CB(oldskb)->vcc;
  950. if (vcc) {
  951. atomic_inc(&vcc->stats->tx);
  952. solos_pop(vcc, oldskb);
  953. } else {
  954. dev_kfree_skb_irq(oldskb);
  955. wake_up(&card->param_wq);
  956. }
  957. }
  958. }
  959. /* For non-DMA TX, write the 'TX start' bit for all four ports simultaneously */
  960. if (tx_started)
  961. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  962. spin_unlock_irqrestore(&card->tx_lock, flags);
  963. return card_flags;
  964. }
  965. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  966. {
  967. struct solos_card *card = vcc->dev->dev_data;
  968. struct pkt_hdr *header;
  969. int pktlen;
  970. pktlen = skb->len;
  971. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  972. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  973. solos_pop(vcc, skb);
  974. return 0;
  975. }
  976. if (!skb_clone_writable(skb, sizeof(*header))) {
  977. int expand_by = 0;
  978. int ret;
  979. if (skb_headroom(skb) < sizeof(*header))
  980. expand_by = sizeof(*header) - skb_headroom(skb);
  981. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  982. if (ret) {
  983. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  984. solos_pop(vcc, skb);
  985. return ret;
  986. }
  987. }
  988. header = (void *)skb_push(skb, sizeof(*header));
  989. /* This does _not_ include the size of the header */
  990. header->size = cpu_to_le16(pktlen);
  991. header->vpi = cpu_to_le16(vcc->vpi);
  992. header->vci = cpu_to_le16(vcc->vci);
  993. header->type = cpu_to_le16(PKT_DATA);
  994. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  995. return 0;
  996. }
  997. static struct atmdev_ops fpga_ops = {
  998. .open = popen,
  999. .close = pclose,
  1000. .ioctl = NULL,
  1001. .getsockopt = NULL,
  1002. .setsockopt = NULL,
  1003. .send = psend,
  1004. .send_oam = NULL,
  1005. .phy_put = NULL,
  1006. .phy_get = NULL,
  1007. .change_qos = NULL,
  1008. .proc_read = NULL,
  1009. .owner = THIS_MODULE
  1010. };
  1011. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  1012. {
  1013. int err;
  1014. uint16_t fpga_ver;
  1015. uint8_t major_ver, minor_ver;
  1016. uint32_t data32;
  1017. struct solos_card *card;
  1018. card = kzalloc(sizeof(*card), GFP_KERNEL);
  1019. if (!card)
  1020. return -ENOMEM;
  1021. card->dev = dev;
  1022. init_waitqueue_head(&card->fw_wq);
  1023. init_waitqueue_head(&card->param_wq);
  1024. err = pci_enable_device(dev);
  1025. if (err) {
  1026. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  1027. goto out;
  1028. }
  1029. err = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
  1030. if (err) {
  1031. dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
  1032. goto out;
  1033. }
  1034. err = pci_request_regions(dev, "solos");
  1035. if (err) {
  1036. dev_warn(&dev->dev, "Failed to request regions\n");
  1037. goto out;
  1038. }
  1039. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  1040. if (!card->config_regs) {
  1041. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  1042. err = -ENOMEM;
  1043. goto out_release_regions;
  1044. }
  1045. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  1046. if (!card->buffers) {
  1047. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  1048. err = -ENOMEM;
  1049. goto out_unmap_config;
  1050. }
  1051. if (reset) {
  1052. iowrite32(1, card->config_regs + FPGA_MODE);
  1053. data32 = ioread32(card->config_regs + FPGA_MODE);
  1054. iowrite32(0, card->config_regs + FPGA_MODE);
  1055. data32 = ioread32(card->config_regs + FPGA_MODE);
  1056. }
  1057. data32 = ioread32(card->config_regs + FPGA_VER);
  1058. fpga_ver = (data32 & 0x0000FFFF);
  1059. major_ver = ((data32 & 0xFF000000) >> 24);
  1060. minor_ver = ((data32 & 0x00FF0000) >> 16);
  1061. card->fpga_version = FPGA_VERSION(major_ver,minor_ver);
  1062. if (card->fpga_version > LEGACY_BUFFERS)
  1063. card->buffer_size = BUF_SIZE;
  1064. else
  1065. card->buffer_size = OLD_BUF_SIZE;
  1066. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  1067. major_ver, minor_ver, fpga_ver);
  1068. if (fpga_ver < 37 && (fpga_upgrade || firmware_upgrade ||
  1069. db_fpga_upgrade || db_firmware_upgrade)) {
  1070. dev_warn(&dev->dev,
  1071. "FPGA too old; cannot upgrade flash. Use JTAG.\n");
  1072. fpga_upgrade = firmware_upgrade = 0;
  1073. db_fpga_upgrade = db_firmware_upgrade = 0;
  1074. }
  1075. /* Stopped using Atmel flash after 0.03-38 */
  1076. if (fpga_ver < 39)
  1077. card->atmel_flash = 1;
  1078. else
  1079. card->atmel_flash = 0;
  1080. data32 = ioread32(card->config_regs + PORTS);
  1081. card->nr_ports = (data32 & 0x000000FF);
  1082. if (card->fpga_version >= DMA_SUPPORTED) {
  1083. pci_set_master(dev);
  1084. card->using_dma = 1;
  1085. if (1) { /* All known FPGA versions so far */
  1086. card->dma_alignment = 3;
  1087. card->dma_bounce = kmalloc(card->nr_ports * BUF_SIZE, GFP_KERNEL);
  1088. if (!card->dma_bounce) {
  1089. dev_warn(&card->dev->dev, "Failed to allocate DMA bounce buffers\n");
  1090. err = -ENOMEM;
  1091. /* Fallback to MMIO doesn't work */
  1092. goto out_unmap_both;
  1093. }
  1094. }
  1095. } else {
  1096. card->using_dma = 0;
  1097. /* Set RX empty flag for all ports */
  1098. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  1099. }
  1100. pci_set_drvdata(dev, card);
  1101. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  1102. spin_lock_init(&card->tx_lock);
  1103. spin_lock_init(&card->tx_queue_lock);
  1104. spin_lock_init(&card->cli_queue_lock);
  1105. spin_lock_init(&card->param_queue_lock);
  1106. INIT_LIST_HEAD(&card->param_queue);
  1107. err = request_irq(dev->irq, solos_irq, IRQF_SHARED,
  1108. "solos-pci", card);
  1109. if (err) {
  1110. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  1111. goto out_unmap_both;
  1112. }
  1113. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  1114. if (fpga_upgrade)
  1115. flash_upgrade(card, 0);
  1116. if (firmware_upgrade)
  1117. flash_upgrade(card, 1);
  1118. if (db_fpga_upgrade)
  1119. flash_upgrade(card, 2);
  1120. if (db_firmware_upgrade)
  1121. flash_upgrade(card, 3);
  1122. err = atm_init(card, &dev->dev);
  1123. if (err)
  1124. goto out_free_irq;
  1125. if (card->fpga_version >= DMA_SUPPORTED &&
  1126. sysfs_create_group(&card->dev->dev.kobj, &gpio_attr_group))
  1127. dev_err(&card->dev->dev, "Could not register parameter group for GPIOs\n");
  1128. return 0;
  1129. out_free_irq:
  1130. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1131. free_irq(dev->irq, card);
  1132. tasklet_kill(&card->tlet);
  1133. out_unmap_both:
  1134. kfree(card->dma_bounce);
  1135. pci_iounmap(dev, card->buffers);
  1136. out_unmap_config:
  1137. pci_iounmap(dev, card->config_regs);
  1138. out_release_regions:
  1139. pci_release_regions(dev);
  1140. out:
  1141. kfree(card);
  1142. return err;
  1143. }
  1144. static int atm_init(struct solos_card *card, struct device *parent)
  1145. {
  1146. int i;
  1147. for (i = 0; i < card->nr_ports; i++) {
  1148. struct sk_buff *skb;
  1149. struct pkt_hdr *header;
  1150. skb_queue_head_init(&card->tx_queue[i]);
  1151. skb_queue_head_init(&card->cli_queue[i]);
  1152. card->atmdev[i] = atm_dev_register("solos-pci", parent, &fpga_ops, -1, NULL);
  1153. if (!card->atmdev[i]) {
  1154. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  1155. atm_remove(card);
  1156. return -ENODEV;
  1157. }
  1158. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  1159. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  1160. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  1161. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  1162. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  1163. card->atmdev[i]->ci_range.vpi_bits = 8;
  1164. card->atmdev[i]->ci_range.vci_bits = 16;
  1165. card->atmdev[i]->dev_data = card;
  1166. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  1167. atm_dev_signal_change(card->atmdev[i], ATM_PHY_SIG_FOUND);
  1168. skb = alloc_skb(sizeof(*header), GFP_KERNEL);
  1169. if (!skb) {
  1170. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  1171. continue;
  1172. }
  1173. header = (void *)skb_put(skb, sizeof(*header));
  1174. header->size = cpu_to_le16(0);
  1175. header->vpi = cpu_to_le16(0);
  1176. header->vci = cpu_to_le16(0);
  1177. header->type = cpu_to_le16(PKT_STATUS);
  1178. fpga_queue(card, i, skb, NULL);
  1179. }
  1180. return 0;
  1181. }
  1182. static void atm_remove(struct solos_card *card)
  1183. {
  1184. int i;
  1185. for (i = 0; i < card->nr_ports; i++) {
  1186. if (card->atmdev[i]) {
  1187. struct sk_buff *skb;
  1188. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  1189. sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
  1190. atm_dev_deregister(card->atmdev[i]);
  1191. skb = card->rx_skb[i];
  1192. if (skb) {
  1193. dma_unmap_single(&card->dev->dev, SKB_CB(skb)->dma_addr,
  1194. RX_DMA_SIZE, DMA_FROM_DEVICE);
  1195. dev_kfree_skb(skb);
  1196. }
  1197. skb = card->tx_skb[i];
  1198. if (skb) {
  1199. dma_unmap_single(&card->dev->dev, SKB_CB(skb)->dma_addr,
  1200. skb->len, DMA_TO_DEVICE);
  1201. dev_kfree_skb(skb);
  1202. }
  1203. while ((skb = skb_dequeue(&card->tx_queue[i])))
  1204. dev_kfree_skb(skb);
  1205. }
  1206. }
  1207. }
  1208. static void fpga_remove(struct pci_dev *dev)
  1209. {
  1210. struct solos_card *card = pci_get_drvdata(dev);
  1211. /* Disable IRQs */
  1212. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1213. /* Reset FPGA */
  1214. iowrite32(1, card->config_regs + FPGA_MODE);
  1215. (void)ioread32(card->config_regs + FPGA_MODE);
  1216. if (card->fpga_version >= DMA_SUPPORTED)
  1217. sysfs_remove_group(&card->dev->dev.kobj, &gpio_attr_group);
  1218. atm_remove(card);
  1219. free_irq(dev->irq, card);
  1220. tasklet_kill(&card->tlet);
  1221. kfree(card->dma_bounce);
  1222. /* Release device from reset */
  1223. iowrite32(0, card->config_regs + FPGA_MODE);
  1224. (void)ioread32(card->config_regs + FPGA_MODE);
  1225. pci_iounmap(dev, card->buffers);
  1226. pci_iounmap(dev, card->config_regs);
  1227. pci_release_regions(dev);
  1228. pci_disable_device(dev);
  1229. kfree(card);
  1230. }
  1231. static struct pci_device_id fpga_pci_tbl[] = {
  1232. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1233. { 0, }
  1234. };
  1235. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  1236. static struct pci_driver fpga_driver = {
  1237. .name = "solos",
  1238. .id_table = fpga_pci_tbl,
  1239. .probe = fpga_probe,
  1240. .remove = fpga_remove,
  1241. };
  1242. static int __init solos_pci_init(void)
  1243. {
  1244. BUILD_BUG_ON(sizeof(struct solos_skb_cb) > sizeof(((struct sk_buff *)0)->cb));
  1245. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  1246. return pci_register_driver(&fpga_driver);
  1247. }
  1248. static void __exit solos_pci_exit(void)
  1249. {
  1250. pci_unregister_driver(&fpga_driver);
  1251. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  1252. }
  1253. module_init(solos_pci_init);
  1254. module_exit(solos_pci_exit);