sunxi-nand.txt 1.5 KB

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  1. Allwinner NAND Flash Controller (NFC)
  2. Required properties:
  3. - compatible : "allwinner,sun4i-a10-nand".
  4. - reg : shall contain registers location and length for data and reg.
  5. - interrupts : shall define the nand controller interrupt.
  6. - #address-cells: shall be set to 1. Encode the nand CS.
  7. - #size-cells : shall be set to 0.
  8. - clocks : shall reference nand controller clocks.
  9. - clock-names : nand controller internal clock names. Shall contain :
  10. * "ahb" : AHB gating clock
  11. * "mod" : nand controller clock
  12. Optional properties:
  13. - dmas : shall reference DMA channel associated to the NAND controller.
  14. - dma-names : shall be "rxtx".
  15. Optional children nodes:
  16. Children nodes represent the available nand chips.
  17. Optional properties:
  18. - reset : phandle + reset specifier pair
  19. - reset-names : must contain "ahb"
  20. - allwinner,rb : shall contain the native Ready/Busy ids.
  21. or
  22. - rb-gpios : shall contain the gpios used as R/B pins.
  23. - nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft",
  24. "soft_bch" or "none")
  25. see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
  26. Examples:
  27. nfc: nand@01c03000 {
  28. compatible = "allwinner,sun4i-a10-nand";
  29. reg = <0x01c03000 0x1000>;
  30. interrupts = <0 37 1>;
  31. clocks = <&ahb_gates 13>, <&nand_clk>;
  32. clock-names = "ahb", "mod";
  33. #address-cells = <1>;
  34. #size-cells = <0>;
  35. pinctrl-names = "default";
  36. pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
  37. status = "okay";
  38. nand@0 {
  39. reg = <0>;
  40. allwinner,rb = <0>;
  41. nand-ecc-mode = "soft_bch";
  42. };
  43. };