Home Verkennen Help
Inloggen
phreedom2600net
/
linux-libre
Volgen 2
Ster 0
Vork 0
Bestanden Kwesties 0 Pull-aanvragen 0 Wiki
Aftakking: audiocape
Aftakkingen Labels
linux-libre
/
drivers
/
usb
/
musb
/
tusb6010.h

tusb6010.h 9.0 KB
Permalink Geschiedenis Ruwe

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219 
  1. /*
    2. 

  2.  * Definitions for TUSB6010 USB 2.0 OTG Dual Role controller
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2006 Nokia Corporation
    5. 

  5.  * Tony Lindgren <tony@atomide.com>
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or modify
    8. 

  8.  * it under the terms of the GNU General Public License version 2 as
    9. 

  9.  * published by the Free Software Foundation.
    10. 

  10.  */
    11. 

  11. 

  12. #ifndef __TUSB6010_H__
    13. 

  13. #define __TUSB6010_H__
    14. 

  14. 

  15. /* VLYNQ control register. 32-bit at offset 0x000 */
    16. 

  16. #define TUSB_VLYNQ_CTRL			0x004
    17. 

  17. 

  18. /* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
    19. 

  19. #define TUSB_BASE_OFFSET		0x400
    20. 

  20. 

  21. /* FIFO registers 32-bit at offset 0x600 */
    22. 

  22. #define TUSB_FIFO_BASE			0x600
    23. 

  23. 

  24. /* Device System & Control registers. 32-bit at offset 0x800 */
    25. 

  25. #define TUSB_SYS_REG_BASE		0x800
    26. 

  26. 

  27. #define TUSB_DEV_CONF			(TUSB_SYS_REG_BASE + 0x000)
    28. 

  28. #define		TUSB_DEV_CONF_USB_HOST_MODE		(1 << 16)
    29. 

  29. #define		TUSB_DEV_CONF_PROD_TEST_MODE		(1 << 15)
    30. 

  30. #define		TUSB_DEV_CONF_SOFT_ID			(1 << 1)
    31. 

  31. #define		TUSB_DEV_CONF_ID_SEL			(1 << 0)
    32. 

  32. 

  33. #define TUSB_PHY_OTG_CTRL_ENABLE	(TUSB_SYS_REG_BASE + 0x004)
    34. 

  34. #define TUSB_PHY_OTG_CTRL		(TUSB_SYS_REG_BASE + 0x008)
    35. 

  35. #define		TUSB_PHY_OTG_CTRL_WRPROTECT		(0xa5 << 24)
    36. 

  36. #define		TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP		(1 << 23)
    37. 

  37. #define		TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN	(1 << 19)
    38. 

  38. #define		TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN	(1 << 18)
    39. 

  39. #define		TUSB_PHY_OTG_CTRL_TESTM2		(1 << 17)
    40. 

  40. #define		TUSB_PHY_OTG_CTRL_TESTM1		(1 << 16)
    41. 

  41. #define		TUSB_PHY_OTG_CTRL_TESTM0		(1 << 15)
    42. 

  42. #define		TUSB_PHY_OTG_CTRL_TX_DATA2		(1 << 14)
    43. 

  43. #define		TUSB_PHY_OTG_CTRL_TX_GZ2		(1 << 13)
    44. 

  44. #define		TUSB_PHY_OTG_CTRL_TX_ENABLE2		(1 << 12)
    45. 

  45. #define		TUSB_PHY_OTG_CTRL_DM_PULLDOWN		(1 << 11)
    46. 

  46. #define		TUSB_PHY_OTG_CTRL_DP_PULLDOWN		(1 << 10)
    47. 

  47. #define		TUSB_PHY_OTG_CTRL_OSC_EN		(1 << 9)
    48. 

  48. #define		TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v)	(((v) & 3) << 7)
    49. 

  49. #define		TUSB_PHY_OTG_CTRL_PD			(1 << 6)
    50. 

  50. #define		TUSB_PHY_OTG_CTRL_PLL_ON		(1 << 5)
    51. 

  51. #define		TUSB_PHY_OTG_CTRL_EXT_RPU		(1 << 4)
    52. 

  52. #define		TUSB_PHY_OTG_CTRL_PWR_GOOD		(1 << 3)
    53. 

  53. #define		TUSB_PHY_OTG_CTRL_RESET			(1 << 2)
    54. 

  54. #define		TUSB_PHY_OTG_CTRL_SUSPENDM		(1 << 1)
    55. 

  55. #define		TUSB_PHY_OTG_CTRL_CLK_MODE		(1 << 0)
    56. 

  56. 

  57. /*OTG status register */
    58. 

  58. #define TUSB_DEV_OTG_STAT		(TUSB_SYS_REG_BASE + 0x00c)
    59. 

  59. #define		TUSB_DEV_OTG_STAT_PWR_CLK_GOOD		(1 << 8)
    60. 

  60. #define		TUSB_DEV_OTG_STAT_SESS_END		(1 << 7)
    61. 

  61. #define		TUSB_DEV_OTG_STAT_SESS_VALID		(1 << 6)
    62. 

  62. #define		TUSB_DEV_OTG_STAT_VBUS_VALID		(1 << 5)
    63. 

  63. #define		TUSB_DEV_OTG_STAT_VBUS_SENSE		(1 << 4)
    64. 

  64. #define		TUSB_DEV_OTG_STAT_ID_STATUS		(1 << 3)
    65. 

  65. #define		TUSB_DEV_OTG_STAT_HOST_DISCON		(1 << 2)
    66. 

  66. #define		TUSB_DEV_OTG_STAT_LINE_STATE		(3 << 0)
    67. 

  67. #define		TUSB_DEV_OTG_STAT_DP_ENABLE		(1 << 1)
    68. 

  68. #define		TUSB_DEV_OTG_STAT_DM_ENABLE		(1 << 0)
    69. 

  69. 

  70. #define TUSB_DEV_OTG_TIMER		(TUSB_SYS_REG_BASE + 0x010)
    71. 

  71. #	define TUSB_DEV_OTG_TIMER_ENABLE		(1 << 31)
    72. 

  72. #	define TUSB_DEV_OTG_TIMER_VAL(v)		((v) & 0x07ffffff)
    73. 

  73. #define TUSB_PRCM_REV			(TUSB_SYS_REG_BASE + 0x014)
    74. 

  74. 

  75. /* PRCM configuration register */
    76. 

  76. #define TUSB_PRCM_CONF			(TUSB_SYS_REG_BASE + 0x018)
    77. 

  77. #define		TUSB_PRCM_CONF_SFW_CPEN		(1 << 24)
    78. 

  78. #define		TUSB_PRCM_CONF_SYS_CLKSEL(v)	(((v) & 3) << 16)
    79. 

  79. 

  80. /* PRCM management register */
    81. 

  81. #define TUSB_PRCM_MNGMT			(TUSB_SYS_REG_BASE + 0x01c)
    82. 

  82. #define		TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v)	(((v) & 0xf) << 25)
    83. 

  83. #define		TUSB_PRCM_MNGMT_SRP_FIX_EN		(1 << 24)
    84. 

  84. #define		TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v)	(((v) & 0xf) << 20)
    85. 

  85. #define		TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN	(1 << 19)
    86. 

  86. #define		TUSB_PRCM_MNGMT_DFT_CLK_DIS		(1 << 18)
    87. 

  87. #define		TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS		(1 << 17)
    88. 

  88. #define		TUSB_PRCM_MNGMT_OTG_SESS_END_EN		(1 << 10)
    89. 

  89. #define		TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN		(1 << 9)
    90. 

  90. #define		TUSB_PRCM_MNGMT_OTG_ID_PULLUP		(1 << 8)
    91. 

  91. #define		TUSB_PRCM_MNGMT_15_SW_EN		(1 << 4)
    92. 

  92. #define		TUSB_PRCM_MNGMT_33_SW_EN		(1 << 3)
    93. 

  93. #define		TUSB_PRCM_MNGMT_5V_CPEN			(1 << 2)
    94. 

  94. #define		TUSB_PRCM_MNGMT_PM_IDLE			(1 << 1)
    95. 

  95. #define		TUSB_PRCM_MNGMT_DEV_IDLE		(1 << 0)
    96. 

  96. 

  97. /* Wake-up source clear and mask registers */
    98. 

  98. #define TUSB_PRCM_WAKEUP_SOURCE		(TUSB_SYS_REG_BASE + 0x020)
    99. 

  99. #define TUSB_PRCM_WAKEUP_CLEAR		(TUSB_SYS_REG_BASE + 0x028)
    100. 

  100. #define TUSB_PRCM_WAKEUP_MASK		(TUSB_SYS_REG_BASE + 0x02c)
    101. 

  101. #define		TUSB_PRCM_WAKEUP_RESERVED_BITS	(0xffffe << 13)
    102. 

  102. #define		TUSB_PRCM_WGPIO_7	(1 << 12)
    103. 

  103. #define		TUSB_PRCM_WGPIO_6	(1 << 11)
    104. 

  104. #define		TUSB_PRCM_WGPIO_5	(1 << 10)
    105. 

  105. #define		TUSB_PRCM_WGPIO_4	(1 << 9)
    106. 

  106. #define		TUSB_PRCM_WGPIO_3	(1 << 8)
    107. 

  107. #define		TUSB_PRCM_WGPIO_2	(1 << 7)
    108. 

  108. #define		TUSB_PRCM_WGPIO_1	(1 << 6)
    109. 

  109. #define		TUSB_PRCM_WGPIO_0	(1 << 5)
    110. 

  110. #define		TUSB_PRCM_WHOSTDISCON	(1 << 4)	/* Host disconnect */
    111. 

  111. #define		TUSB_PRCM_WBUS		(1 << 3)	/* USB bus resume */
    112. 

  112. #define		TUSB_PRCM_WNORCS	(1 << 2)	/* NOR chip select */
    113. 

  113. #define		TUSB_PRCM_WVBUS		(1 << 1)	/* OTG PHY VBUS */
    114. 

  114. #define		TUSB_PRCM_WID		(1 << 0)	/* OTG PHY ID detect */
    115. 

  115. 

  116. #define TUSB_PULLUP_1_CTRL		(TUSB_SYS_REG_BASE + 0x030)
    117. 

  117. #define TUSB_PULLUP_2_CTRL		(TUSB_SYS_REG_BASE + 0x034)
    118. 

  118. #define TUSB_INT_CTRL_REV		(TUSB_SYS_REG_BASE + 0x038)
    119. 

  119. #define TUSB_INT_CTRL_CONF		(TUSB_SYS_REG_BASE + 0x03c)
    120. 

  120. #define TUSB_USBIP_INT_SRC		(TUSB_SYS_REG_BASE + 0x040)
    121. 

  121. #define TUSB_USBIP_INT_SET		(TUSB_SYS_REG_BASE + 0x044)
    122. 

  122. #define TUSB_USBIP_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x048)
    123. 

  123. #define TUSB_USBIP_INT_MASK		(TUSB_SYS_REG_BASE + 0x04c)
    124. 

  124. #define TUSB_DMA_INT_SRC		(TUSB_SYS_REG_BASE + 0x050)
    125. 

  125. #define TUSB_DMA_INT_SET		(TUSB_SYS_REG_BASE + 0x054)
    126. 

  126. #define TUSB_DMA_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x058)
    127. 

  127. #define TUSB_DMA_INT_MASK		(TUSB_SYS_REG_BASE + 0x05c)
    128. 

  128. #define TUSB_GPIO_INT_SRC		(TUSB_SYS_REG_BASE + 0x060)
    129. 

  129. #define TUSB_GPIO_INT_SET		(TUSB_SYS_REG_BASE + 0x064)
    130. 

  130. #define TUSB_GPIO_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x068)
    131. 

  131. #define TUSB_GPIO_INT_MASK		(TUSB_SYS_REG_BASE + 0x06c)
    132. 

  132. 

  133. /* NOR flash interrupt source registers */
    134. 

  134. #define TUSB_INT_SRC			(TUSB_SYS_REG_BASE + 0x070)
    135. 

  135. #define TUSB_INT_SRC_SET		(TUSB_SYS_REG_BASE + 0x074)
    136. 

  136. #define TUSB_INT_SRC_CLEAR		(TUSB_SYS_REG_BASE + 0x078)
    137. 

  137. #define TUSB_INT_MASK			(TUSB_SYS_REG_BASE + 0x07c)
    138. 

  138. #define		TUSB_INT_SRC_TXRX_DMA_DONE		(1 << 24)
    139. 

  139. #define		TUSB_INT_SRC_USB_IP_CORE		(1 << 17)
    140. 

  140. #define		TUSB_INT_SRC_OTG_TIMEOUT		(1 << 16)
    141. 

  141. #define		TUSB_INT_SRC_VBUS_SENSE_CHNG		(1 << 15)
    142. 

  142. #define		TUSB_INT_SRC_ID_STATUS_CHNG		(1 << 14)
    143. 

  143. #define		TUSB_INT_SRC_DEV_WAKEUP			(1 << 13)
    144. 

  144. #define		TUSB_INT_SRC_DEV_READY			(1 << 12)
    145. 

  145. #define		TUSB_INT_SRC_USB_IP_TX			(1 << 9)
    146. 

  146. #define		TUSB_INT_SRC_USB_IP_RX			(1 << 8)
    147. 

  147. #define		TUSB_INT_SRC_USB_IP_VBUS_ERR		(1 << 7)
    148. 

  148. #define		TUSB_INT_SRC_USB_IP_VBUS_REQ		(1 << 6)
    149. 

  149. #define		TUSB_INT_SRC_USB_IP_DISCON		(1 << 5)
    150. 

  150. #define		TUSB_INT_SRC_USB_IP_CONN		(1 << 4)
    151. 

  151. #define		TUSB_INT_SRC_USB_IP_SOF			(1 << 3)
    152. 

  152. #define		TUSB_INT_SRC_USB_IP_RST_BABBLE		(1 << 2)
    153. 

  153. #define		TUSB_INT_SRC_USB_IP_RESUME		(1 << 1)
    154. 

  154. #define		TUSB_INT_SRC_USB_IP_SUSPEND		(1 << 0)
    155. 

  155. 

  156. /* NOR flash interrupt registers reserved bits. Must be written as 0 */
    157. 

  157. #define		TUSB_INT_MASK_RESERVED_17		(0x3fff << 17)
    158. 

  158. #define		TUSB_INT_MASK_RESERVED_13		(1 << 13)
    159. 

  159. #define		TUSB_INT_MASK_RESERVED_8		(0xf << 8)
    160. 

  160. #define		TUSB_INT_SRC_RESERVED_26		(0x1f << 26)
    161. 

  161. #define		TUSB_INT_SRC_RESERVED_18		(0x3f << 18)
    162. 

  162. #define		TUSB_INT_SRC_RESERVED_10		(0x03 << 10)
    163. 

  163. 

  164. /* Reserved bits for NOR flash interrupt mask and clear register */
    165. 

  165. #define		TUSB_INT_MASK_RESERVED_BITS	(TUSB_INT_MASK_RESERVED_17 | \
    166. 

  166. 						TUSB_INT_MASK_RESERVED_13 | \
    167. 

  167. 						TUSB_INT_MASK_RESERVED_8)
    168. 

  168. 

  169. /* Reserved bits for NOR flash interrupt status register */
    170. 

  170. #define		TUSB_INT_SRC_RESERVED_BITS	(TUSB_INT_SRC_RESERVED_26 | \
    171. 

  171. 						TUSB_INT_SRC_RESERVED_18 | \
    172. 

  172. 						TUSB_INT_SRC_RESERVED_10)
    173. 

  173. 

  174. #define TUSB_GPIO_REV			(TUSB_SYS_REG_BASE + 0x080)
    175. 

  175. #define TUSB_GPIO_CONF			(TUSB_SYS_REG_BASE + 0x084)
    176. 

  176. #define TUSB_DMA_CTRL_REV		(TUSB_SYS_REG_BASE + 0x100)
    177. 

  177. #define TUSB_DMA_REQ_CONF		(TUSB_SYS_REG_BASE + 0x104)
    178. 

  178. #define TUSB_EP0_CONF			(TUSB_SYS_REG_BASE + 0x108)
    179. 

  179. #define TUSB_DMA_EP_MAP			(TUSB_SYS_REG_BASE + 0x148)
    180. 

  180. 

  181. /* Offsets from each ep base register */
    182. 

  182. #define TUSB_EP_TX_OFFSET		0x10c	/* EP_IN in docs */
    183. 

  183. #define TUSB_EP_RX_OFFSET		0x14c	/* EP_OUT in docs */
    184. 

  184. #define TUSB_EP_MAX_PACKET_SIZE_OFFSET	0x188
    185. 

  185. 

  186. #define TUSB_WAIT_COUNT			(TUSB_SYS_REG_BASE + 0x1c8)
    187. 

  187. #define TUSB_SCRATCH_PAD		(TUSB_SYS_REG_BASE + 0x1c4)
    188. 

  188. #define TUSB_PROD_TEST_RESET		(TUSB_SYS_REG_BASE + 0x1d8)
    189. 

  189. 

  190. /* Device System & Control register bitfields */
    191. 

  191. #define TUSB_INT_CTRL_CONF_INT_RELCYC(v)	(((v) & 0x7) << 18)
    192. 

  192. #define TUSB_INT_CTRL_CONF_INT_POLARITY		(1 << 17)
    193. 

  193. #define TUSB_INT_CTRL_CONF_INT_MODE		(1 << 16)
    194. 

  194. #define TUSB_GPIO_CONF_DMAREQ(v)		(((v) & 0x3f) << 24)
    195. 

  195. #define TUSB_DMA_REQ_CONF_BURST_SIZE(v)		(((v) & 3) << 26)
    196. 

  196. #define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v)		(((v) & 0x3f) << 20)
    197. 

  197. #define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v)	(((v) & 0xf) << 16)
    198. 

  198. #define TUSB_EP0_CONFIG_SW_EN			(1 << 8)
    199. 

  199. #define TUSB_EP0_CONFIG_DIR_TX			(1 << 7)
    200. 

  200. #define TUSB_EP0_CONFIG_XFR_SIZE(v)		((v) & 0x7f)
    201. 

  201. #define TUSB_EP_CONFIG_SW_EN			(1 << 31)
    202. 

  202. #define TUSB_EP_CONFIG_XFR_SIZE(v)		((v) & 0x7fffffff)
    203. 

  203. #define TUSB_PROD_TEST_RESET_VAL		0xa596
    204. 

  204. #define TUSB_EP_FIFO(ep)			(TUSB_FIFO_BASE + (ep) * 0x20)
    205. 

  205. 

  206. #define TUSB_DIDR1_LO				(TUSB_SYS_REG_BASE + 0x1f8)
    207. 

  207. #define TUSB_DIDR1_HI				(TUSB_SYS_REG_BASE + 0x1fc)
    208. 

  208. #define		TUSB_DIDR1_HI_CHIP_REV(v)		(((v) >> 17) & 0xf)
    209. 

  209. #define			TUSB_DIDR1_HI_REV_20		0
    210. 

  210. #define			TUSB_DIDR1_HI_REV_30		1
    211. 

  211. #define			TUSB_DIDR1_HI_REV_31		2
    212. 

  212. 

  213. #define TUSB_REV_10	0x10
    214. 

  214. #define TUSB_REV_20	0x20
    215. 

  215. #define TUSB_REV_30	0x30
    216. 

  216. #define TUSB_REV_31	0x31
    217. 

  217. 

  218. #endif /* __TUSB6010_H__ */
    219. 

  219.