8250_of.c 8.7 KB

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  1. /*
  2. * Serial Port driver for Open Firmware platform devices
  3. *
  4. * Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. */
  12. #include <linux/console.h>
  13. #include <linux/module.h>
  14. #include <linux/slab.h>
  15. #include <linux/delay.h>
  16. #include <linux/serial_core.h>
  17. #include <linux/serial_reg.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/of_platform.h>
  21. #include <linux/clk.h>
  22. #include "8250.h"
  23. struct of_serial_info {
  24. struct clk *clk;
  25. int type;
  26. int line;
  27. };
  28. #ifdef CONFIG_ARCH_TEGRA
  29. static void tegra_serial_handle_break(struct uart_port *p)
  30. {
  31. unsigned int status, tmout = 10000;
  32. do {
  33. status = p->serial_in(p, UART_LSR);
  34. if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
  35. status = p->serial_in(p, UART_RX);
  36. else
  37. break;
  38. if (--tmout == 0)
  39. break;
  40. udelay(1);
  41. } while (1);
  42. }
  43. #else
  44. static inline void tegra_serial_handle_break(struct uart_port *port)
  45. {
  46. }
  47. #endif
  48. /*
  49. * Fill a struct uart_port for a given device node
  50. */
  51. static int of_platform_serial_setup(struct platform_device *ofdev,
  52. int type, struct uart_port *port,
  53. struct of_serial_info *info)
  54. {
  55. struct resource resource;
  56. struct device_node *np = ofdev->dev.of_node;
  57. u32 clk, spd, prop;
  58. int ret;
  59. memset(port, 0, sizeof *port);
  60. if (of_property_read_u32(np, "clock-frequency", &clk)) {
  61. /* Get clk rate through clk driver if present */
  62. info->clk = devm_clk_get(&ofdev->dev, NULL);
  63. if (IS_ERR(info->clk)) {
  64. dev_warn(&ofdev->dev,
  65. "clk or clock-frequency not defined\n");
  66. return PTR_ERR(info->clk);
  67. }
  68. ret = clk_prepare_enable(info->clk);
  69. if (ret < 0)
  70. return ret;
  71. clk = clk_get_rate(info->clk);
  72. }
  73. /* If current-speed was set, then try not to change it. */
  74. if (of_property_read_u32(np, "current-speed", &spd) == 0)
  75. port->custom_divisor = clk / (16 * spd);
  76. ret = of_address_to_resource(np, 0, &resource);
  77. if (ret) {
  78. dev_warn(&ofdev->dev, "invalid address\n");
  79. goto out;
  80. }
  81. spin_lock_init(&port->lock);
  82. port->mapbase = resource.start;
  83. port->mapsize = resource_size(&resource);
  84. /* Check for shifted address mapping */
  85. if (of_property_read_u32(np, "reg-offset", &prop) == 0)
  86. port->mapbase += prop;
  87. /* Check for registers offset within the devices address range */
  88. if (of_property_read_u32(np, "reg-shift", &prop) == 0)
  89. port->regshift = prop;
  90. /* Check for fifo size */
  91. if (of_property_read_u32(np, "fifo-size", &prop) == 0)
  92. port->fifosize = prop;
  93. /* Check for a fixed line number */
  94. ret = of_alias_get_id(np, "serial");
  95. if (ret >= 0)
  96. port->line = ret;
  97. port->irq = irq_of_parse_and_map(np, 0);
  98. port->iotype = UPIO_MEM;
  99. if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
  100. switch (prop) {
  101. case 1:
  102. port->iotype = UPIO_MEM;
  103. break;
  104. case 2:
  105. port->iotype = UPIO_MEM16;
  106. break;
  107. case 4:
  108. port->iotype = of_device_is_big_endian(np) ?
  109. UPIO_MEM32BE : UPIO_MEM32;
  110. break;
  111. default:
  112. dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
  113. prop);
  114. ret = -EINVAL;
  115. goto out;
  116. }
  117. }
  118. port->type = type;
  119. port->uartclk = clk;
  120. port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
  121. | UPF_FIXED_PORT | UPF_FIXED_TYPE;
  122. if (of_find_property(np, "no-loopback-test", NULL))
  123. port->flags |= UPF_SKIP_TEST;
  124. port->dev = &ofdev->dev;
  125. switch (type) {
  126. case PORT_TEGRA:
  127. port->handle_break = tegra_serial_handle_break;
  128. break;
  129. case PORT_RT2880:
  130. port->iotype = UPIO_AU;
  131. break;
  132. }
  133. if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) &&
  134. (of_device_is_compatible(np, "fsl,ns16550") ||
  135. of_device_is_compatible(np, "fsl,16550-FIFO64")))
  136. port->handle_irq = fsl8250_handle_irq;
  137. return 0;
  138. out:
  139. if (info->clk)
  140. clk_disable_unprepare(info->clk);
  141. return ret;
  142. }
  143. /*
  144. * Try to register a serial port
  145. */
  146. static const struct of_device_id of_platform_serial_table[];
  147. static int of_platform_serial_probe(struct platform_device *ofdev)
  148. {
  149. const struct of_device_id *match;
  150. struct of_serial_info *info;
  151. struct uart_port port;
  152. int port_type;
  153. int ret;
  154. match = of_match_device(of_platform_serial_table, &ofdev->dev);
  155. if (!match)
  156. return -EINVAL;
  157. if (of_find_property(ofdev->dev.of_node, "used-by-rtas", NULL))
  158. return -EBUSY;
  159. info = kzalloc(sizeof(*info), GFP_KERNEL);
  160. if (info == NULL)
  161. return -ENOMEM;
  162. port_type = (unsigned long)match->data;
  163. ret = of_platform_serial_setup(ofdev, port_type, &port, info);
  164. if (ret)
  165. goto out;
  166. switch (port_type) {
  167. case PORT_8250 ... PORT_MAX_8250:
  168. {
  169. u32 tx_threshold;
  170. struct uart_8250_port port8250;
  171. memset(&port8250, 0, sizeof(port8250));
  172. port8250.port = port;
  173. if (port.fifosize)
  174. port8250.capabilities = UART_CAP_FIFO;
  175. /* Check for TX FIFO threshold & set tx_loadsz */
  176. if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
  177. &tx_threshold) == 0) &&
  178. (tx_threshold < port.fifosize))
  179. port8250.tx_loadsz = port.fifosize - tx_threshold;
  180. if (of_property_read_bool(ofdev->dev.of_node,
  181. "auto-flow-control"))
  182. port8250.capabilities |= UART_CAP_AFE;
  183. ret = serial8250_register_8250_port(&port8250);
  184. break;
  185. }
  186. default:
  187. /* need to add code for these */
  188. case PORT_UNKNOWN:
  189. dev_info(&ofdev->dev, "Unknown serial port found, ignored\n");
  190. ret = -ENODEV;
  191. break;
  192. }
  193. if (ret < 0)
  194. goto out;
  195. info->type = port_type;
  196. info->line = ret;
  197. platform_set_drvdata(ofdev, info);
  198. return 0;
  199. out:
  200. kfree(info);
  201. irq_dispose_mapping(port.irq);
  202. return ret;
  203. }
  204. /*
  205. * Release a line
  206. */
  207. static int of_platform_serial_remove(struct platform_device *ofdev)
  208. {
  209. struct of_serial_info *info = platform_get_drvdata(ofdev);
  210. switch (info->type) {
  211. case PORT_8250 ... PORT_MAX_8250:
  212. serial8250_unregister_port(info->line);
  213. break;
  214. default:
  215. /* need to add code for these */
  216. break;
  217. }
  218. if (info->clk)
  219. clk_disable_unprepare(info->clk);
  220. kfree(info);
  221. return 0;
  222. }
  223. #ifdef CONFIG_PM_SLEEP
  224. static void of_serial_suspend_8250(struct of_serial_info *info)
  225. {
  226. struct uart_8250_port *port8250 = serial8250_get_port(info->line);
  227. struct uart_port *port = &port8250->port;
  228. serial8250_suspend_port(info->line);
  229. if (info->clk && (!uart_console(port) || console_suspend_enabled))
  230. clk_disable_unprepare(info->clk);
  231. }
  232. static void of_serial_resume_8250(struct of_serial_info *info)
  233. {
  234. struct uart_8250_port *port8250 = serial8250_get_port(info->line);
  235. struct uart_port *port = &port8250->port;
  236. if (info->clk && (!uart_console(port) || console_suspend_enabled))
  237. clk_prepare_enable(info->clk);
  238. serial8250_resume_port(info->line);
  239. }
  240. static int of_serial_suspend(struct device *dev)
  241. {
  242. struct of_serial_info *info = dev_get_drvdata(dev);
  243. switch (info->type) {
  244. case PORT_8250 ... PORT_MAX_8250:
  245. of_serial_suspend_8250(info);
  246. break;
  247. default:
  248. break;
  249. }
  250. return 0;
  251. }
  252. static int of_serial_resume(struct device *dev)
  253. {
  254. struct of_serial_info *info = dev_get_drvdata(dev);
  255. switch (info->type) {
  256. case PORT_8250 ... PORT_MAX_8250:
  257. of_serial_resume_8250(info);
  258. break;
  259. default:
  260. break;
  261. }
  262. return 0;
  263. }
  264. #endif
  265. static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);
  266. /*
  267. * A few common types, add more as needed.
  268. */
  269. static const struct of_device_id of_platform_serial_table[] = {
  270. { .compatible = "ns8250", .data = (void *)PORT_8250, },
  271. { .compatible = "ns16450", .data = (void *)PORT_16450, },
  272. { .compatible = "ns16550a", .data = (void *)PORT_16550A, },
  273. { .compatible = "ns16550", .data = (void *)PORT_16550, },
  274. { .compatible = "ns16750", .data = (void *)PORT_16750, },
  275. { .compatible = "ns16850", .data = (void *)PORT_16850, },
  276. { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
  277. { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
  278. { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
  279. { .compatible = "altr,16550-FIFO32",
  280. .data = (void *)PORT_ALTR_16550_F32, },
  281. { .compatible = "altr,16550-FIFO64",
  282. .data = (void *)PORT_ALTR_16550_F64, },
  283. { .compatible = "altr,16550-FIFO128",
  284. .data = (void *)PORT_ALTR_16550_F128, },
  285. { .compatible = "mrvl,mmp-uart",
  286. .data = (void *)PORT_XSCALE, },
  287. { .compatible = "mrvl,pxa-uart",
  288. .data = (void *)PORT_XSCALE, },
  289. { /* end of list */ },
  290. };
  291. MODULE_DEVICE_TABLE(of, of_platform_serial_table);
  292. static struct platform_driver of_platform_serial_driver = {
  293. .driver = {
  294. .name = "of_serial",
  295. .of_match_table = of_platform_serial_table,
  296. .pm = &of_serial_pm_ops,
  297. },
  298. .probe = of_platform_serial_probe,
  299. .remove = of_platform_serial_remove,
  300. };
  301. module_platform_driver(of_platform_serial_driver);
  302. MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
  303. MODULE_LICENSE("GPL");
  304. MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");