rw.c 20 KB

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  1. /*
  2. * Copyright (c) 2016 HGST, a Western Digital Company.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. */
  13. #include <linux/moduleparam.h>
  14. #include <linux/slab.h>
  15. #include <rdma/mr_pool.h>
  16. #include <rdma/rw.h>
  17. enum {
  18. RDMA_RW_SINGLE_WR,
  19. RDMA_RW_MULTI_WR,
  20. RDMA_RW_MR,
  21. RDMA_RW_SIG_MR,
  22. };
  23. static bool rdma_rw_force_mr;
  24. module_param_named(force_mr, rdma_rw_force_mr, bool, 0);
  25. MODULE_PARM_DESC(force_mr, "Force usage of MRs for RDMA READ/WRITE operations");
  26. /*
  27. * Check if the device might use memory registration. This is currently only
  28. * true for iWarp devices. In the future we can hopefully fine tune this based
  29. * on HCA driver input.
  30. */
  31. static inline bool rdma_rw_can_use_mr(struct ib_device *dev, u8 port_num)
  32. {
  33. if (rdma_protocol_iwarp(dev, port_num))
  34. return true;
  35. if (unlikely(rdma_rw_force_mr))
  36. return true;
  37. return false;
  38. }
  39. /*
  40. * Check if the device will use memory registration for this RW operation.
  41. * We currently always use memory registrations for iWarp RDMA READs, and
  42. * have a debug option to force usage of MRs.
  43. *
  44. * XXX: In the future we can hopefully fine tune this based on HCA driver
  45. * input.
  46. */
  47. static inline bool rdma_rw_io_needs_mr(struct ib_device *dev, u8 port_num,
  48. enum dma_data_direction dir, int dma_nents)
  49. {
  50. if (rdma_protocol_iwarp(dev, port_num) && dir == DMA_FROM_DEVICE)
  51. return true;
  52. if (unlikely(rdma_rw_force_mr))
  53. return true;
  54. return false;
  55. }
  56. static inline u32 rdma_rw_fr_page_list_len(struct ib_device *dev)
  57. {
  58. /* arbitrary limit to avoid allocating gigantic resources */
  59. return min_t(u32, dev->attrs.max_fast_reg_page_list_len, 256);
  60. }
  61. /* Caller must have zero-initialized *reg. */
  62. static int rdma_rw_init_one_mr(struct ib_qp *qp, u8 port_num,
  63. struct rdma_rw_reg_ctx *reg, struct scatterlist *sg,
  64. u32 sg_cnt, u32 offset)
  65. {
  66. u32 pages_per_mr = rdma_rw_fr_page_list_len(qp->pd->device);
  67. u32 nents = min(sg_cnt, pages_per_mr);
  68. int count = 0, ret;
  69. reg->mr = ib_mr_pool_get(qp, &qp->rdma_mrs);
  70. if (!reg->mr)
  71. return -EAGAIN;
  72. if (reg->mr->need_inval) {
  73. reg->inv_wr.opcode = IB_WR_LOCAL_INV;
  74. reg->inv_wr.ex.invalidate_rkey = reg->mr->lkey;
  75. reg->inv_wr.next = &reg->reg_wr.wr;
  76. count++;
  77. } else {
  78. reg->inv_wr.next = NULL;
  79. }
  80. ret = ib_map_mr_sg(reg->mr, sg, nents, &offset, PAGE_SIZE);
  81. if (ret < nents) {
  82. ib_mr_pool_put(qp, &qp->rdma_mrs, reg->mr);
  83. return -EINVAL;
  84. }
  85. reg->reg_wr.wr.opcode = IB_WR_REG_MR;
  86. reg->reg_wr.mr = reg->mr;
  87. reg->reg_wr.access = IB_ACCESS_LOCAL_WRITE;
  88. if (rdma_protocol_iwarp(qp->device, port_num))
  89. reg->reg_wr.access |= IB_ACCESS_REMOTE_WRITE;
  90. count++;
  91. reg->sge.addr = reg->mr->iova;
  92. reg->sge.length = reg->mr->length;
  93. return count;
  94. }
  95. static int rdma_rw_init_mr_wrs(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  96. u8 port_num, struct scatterlist *sg, u32 sg_cnt, u32 offset,
  97. u64 remote_addr, u32 rkey, enum dma_data_direction dir)
  98. {
  99. struct rdma_rw_reg_ctx *prev = NULL;
  100. u32 pages_per_mr = rdma_rw_fr_page_list_len(qp->pd->device);
  101. int i, j, ret = 0, count = 0;
  102. ctx->nr_ops = (sg_cnt + pages_per_mr - 1) / pages_per_mr;
  103. ctx->reg = kcalloc(ctx->nr_ops, sizeof(*ctx->reg), GFP_KERNEL);
  104. if (!ctx->reg) {
  105. ret = -ENOMEM;
  106. goto out;
  107. }
  108. for (i = 0; i < ctx->nr_ops; i++) {
  109. struct rdma_rw_reg_ctx *reg = &ctx->reg[i];
  110. u32 nents = min(sg_cnt, pages_per_mr);
  111. ret = rdma_rw_init_one_mr(qp, port_num, reg, sg, sg_cnt,
  112. offset);
  113. if (ret < 0)
  114. goto out_free;
  115. count += ret;
  116. if (prev) {
  117. if (reg->mr->need_inval)
  118. prev->wr.wr.next = &reg->inv_wr;
  119. else
  120. prev->wr.wr.next = &reg->reg_wr.wr;
  121. }
  122. reg->reg_wr.wr.next = &reg->wr.wr;
  123. reg->wr.wr.sg_list = &reg->sge;
  124. reg->wr.wr.num_sge = 1;
  125. reg->wr.remote_addr = remote_addr;
  126. reg->wr.rkey = rkey;
  127. if (dir == DMA_TO_DEVICE) {
  128. reg->wr.wr.opcode = IB_WR_RDMA_WRITE;
  129. } else if (!rdma_cap_read_inv(qp->device, port_num)) {
  130. reg->wr.wr.opcode = IB_WR_RDMA_READ;
  131. } else {
  132. reg->wr.wr.opcode = IB_WR_RDMA_READ_WITH_INV;
  133. reg->wr.wr.ex.invalidate_rkey = reg->mr->lkey;
  134. }
  135. count++;
  136. remote_addr += reg->sge.length;
  137. sg_cnt -= nents;
  138. for (j = 0; j < nents; j++)
  139. sg = sg_next(sg);
  140. prev = reg;
  141. offset = 0;
  142. }
  143. if (prev)
  144. prev->wr.wr.next = NULL;
  145. ctx->type = RDMA_RW_MR;
  146. return count;
  147. out_free:
  148. while (--i >= 0)
  149. ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->reg[i].mr);
  150. kfree(ctx->reg);
  151. out:
  152. return ret;
  153. }
  154. static int rdma_rw_init_map_wrs(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  155. struct scatterlist *sg, u32 sg_cnt, u32 offset,
  156. u64 remote_addr, u32 rkey, enum dma_data_direction dir)
  157. {
  158. struct ib_device *dev = qp->pd->device;
  159. u32 max_sge = dir == DMA_TO_DEVICE ? qp->max_write_sge :
  160. qp->max_read_sge;
  161. struct ib_sge *sge;
  162. u32 total_len = 0, i, j;
  163. ctx->nr_ops = DIV_ROUND_UP(sg_cnt, max_sge);
  164. ctx->map.sges = sge = kcalloc(sg_cnt, sizeof(*sge), GFP_KERNEL);
  165. if (!ctx->map.sges)
  166. goto out;
  167. ctx->map.wrs = kcalloc(ctx->nr_ops, sizeof(*ctx->map.wrs), GFP_KERNEL);
  168. if (!ctx->map.wrs)
  169. goto out_free_sges;
  170. for (i = 0; i < ctx->nr_ops; i++) {
  171. struct ib_rdma_wr *rdma_wr = &ctx->map.wrs[i];
  172. u32 nr_sge = min(sg_cnt, max_sge);
  173. if (dir == DMA_TO_DEVICE)
  174. rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
  175. else
  176. rdma_wr->wr.opcode = IB_WR_RDMA_READ;
  177. rdma_wr->remote_addr = remote_addr + total_len;
  178. rdma_wr->rkey = rkey;
  179. rdma_wr->wr.num_sge = nr_sge;
  180. rdma_wr->wr.sg_list = sge;
  181. for (j = 0; j < nr_sge; j++, sg = sg_next(sg)) {
  182. sge->addr = ib_sg_dma_address(dev, sg) + offset;
  183. sge->length = ib_sg_dma_len(dev, sg) - offset;
  184. sge->lkey = qp->pd->local_dma_lkey;
  185. total_len += sge->length;
  186. sge++;
  187. sg_cnt--;
  188. offset = 0;
  189. }
  190. rdma_wr->wr.next = i + 1 < ctx->nr_ops ?
  191. &ctx->map.wrs[i + 1].wr : NULL;
  192. }
  193. ctx->type = RDMA_RW_MULTI_WR;
  194. return ctx->nr_ops;
  195. out_free_sges:
  196. kfree(ctx->map.sges);
  197. out:
  198. return -ENOMEM;
  199. }
  200. static int rdma_rw_init_single_wr(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  201. struct scatterlist *sg, u32 offset, u64 remote_addr, u32 rkey,
  202. enum dma_data_direction dir)
  203. {
  204. struct ib_device *dev = qp->pd->device;
  205. struct ib_rdma_wr *rdma_wr = &ctx->single.wr;
  206. ctx->nr_ops = 1;
  207. ctx->single.sge.lkey = qp->pd->local_dma_lkey;
  208. ctx->single.sge.addr = ib_sg_dma_address(dev, sg) + offset;
  209. ctx->single.sge.length = ib_sg_dma_len(dev, sg) - offset;
  210. memset(rdma_wr, 0, sizeof(*rdma_wr));
  211. if (dir == DMA_TO_DEVICE)
  212. rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
  213. else
  214. rdma_wr->wr.opcode = IB_WR_RDMA_READ;
  215. rdma_wr->wr.sg_list = &ctx->single.sge;
  216. rdma_wr->wr.num_sge = 1;
  217. rdma_wr->remote_addr = remote_addr;
  218. rdma_wr->rkey = rkey;
  219. ctx->type = RDMA_RW_SINGLE_WR;
  220. return 1;
  221. }
  222. /**
  223. * rdma_rw_ctx_init - initialize a RDMA READ/WRITE context
  224. * @ctx: context to initialize
  225. * @qp: queue pair to operate on
  226. * @port_num: port num to which the connection is bound
  227. * @sg: scatterlist to READ/WRITE from/to
  228. * @sg_cnt: number of entries in @sg
  229. * @sg_offset: current byte offset into @sg
  230. * @remote_addr:remote address to read/write (relative to @rkey)
  231. * @rkey: remote key to operate on
  232. * @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
  233. *
  234. * Returns the number of WQEs that will be needed on the workqueue if
  235. * successful, or a negative error code.
  236. */
  237. int rdma_rw_ctx_init(struct rdma_rw_ctx *ctx, struct ib_qp *qp, u8 port_num,
  238. struct scatterlist *sg, u32 sg_cnt, u32 sg_offset,
  239. u64 remote_addr, u32 rkey, enum dma_data_direction dir)
  240. {
  241. struct ib_device *dev = qp->pd->device;
  242. int ret;
  243. ret = ib_dma_map_sg(dev, sg, sg_cnt, dir);
  244. if (!ret)
  245. return -ENOMEM;
  246. sg_cnt = ret;
  247. /*
  248. * Skip to the S/G entry that sg_offset falls into:
  249. */
  250. for (;;) {
  251. u32 len = ib_sg_dma_len(dev, sg);
  252. if (sg_offset < len)
  253. break;
  254. sg = sg_next(sg);
  255. sg_offset -= len;
  256. sg_cnt--;
  257. }
  258. ret = -EIO;
  259. if (WARN_ON_ONCE(sg_cnt == 0))
  260. goto out_unmap_sg;
  261. if (rdma_rw_io_needs_mr(qp->device, port_num, dir, sg_cnt)) {
  262. ret = rdma_rw_init_mr_wrs(ctx, qp, port_num, sg, sg_cnt,
  263. sg_offset, remote_addr, rkey, dir);
  264. } else if (sg_cnt > 1) {
  265. ret = rdma_rw_init_map_wrs(ctx, qp, sg, sg_cnt, sg_offset,
  266. remote_addr, rkey, dir);
  267. } else {
  268. ret = rdma_rw_init_single_wr(ctx, qp, sg, sg_offset,
  269. remote_addr, rkey, dir);
  270. }
  271. if (ret < 0)
  272. goto out_unmap_sg;
  273. return ret;
  274. out_unmap_sg:
  275. ib_dma_unmap_sg(dev, sg, sg_cnt, dir);
  276. return ret;
  277. }
  278. EXPORT_SYMBOL(rdma_rw_ctx_init);
  279. /**
  280. * rdma_rw_ctx_signature init - initialize a RW context with signature offload
  281. * @ctx: context to initialize
  282. * @qp: queue pair to operate on
  283. * @port_num: port num to which the connection is bound
  284. * @sg: scatterlist to READ/WRITE from/to
  285. * @sg_cnt: number of entries in @sg
  286. * @prot_sg: scatterlist to READ/WRITE protection information from/to
  287. * @prot_sg_cnt: number of entries in @prot_sg
  288. * @sig_attrs: signature offloading algorithms
  289. * @remote_addr:remote address to read/write (relative to @rkey)
  290. * @rkey: remote key to operate on
  291. * @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
  292. *
  293. * Returns the number of WQEs that will be needed on the workqueue if
  294. * successful, or a negative error code.
  295. */
  296. int rdma_rw_ctx_signature_init(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  297. u8 port_num, struct scatterlist *sg, u32 sg_cnt,
  298. struct scatterlist *prot_sg, u32 prot_sg_cnt,
  299. struct ib_sig_attrs *sig_attrs,
  300. u64 remote_addr, u32 rkey, enum dma_data_direction dir)
  301. {
  302. struct ib_device *dev = qp->pd->device;
  303. u32 pages_per_mr = rdma_rw_fr_page_list_len(qp->pd->device);
  304. struct ib_rdma_wr *rdma_wr;
  305. struct ib_send_wr *prev_wr = NULL;
  306. int count = 0, ret;
  307. if (sg_cnt > pages_per_mr || prot_sg_cnt > pages_per_mr) {
  308. pr_err("SG count too large\n");
  309. return -EINVAL;
  310. }
  311. ret = ib_dma_map_sg(dev, sg, sg_cnt, dir);
  312. if (!ret)
  313. return -ENOMEM;
  314. sg_cnt = ret;
  315. ret = ib_dma_map_sg(dev, prot_sg, prot_sg_cnt, dir);
  316. if (!ret) {
  317. ret = -ENOMEM;
  318. goto out_unmap_sg;
  319. }
  320. prot_sg_cnt = ret;
  321. ctx->type = RDMA_RW_SIG_MR;
  322. ctx->nr_ops = 1;
  323. ctx->sig = kcalloc(1, sizeof(*ctx->sig), GFP_KERNEL);
  324. if (!ctx->sig) {
  325. ret = -ENOMEM;
  326. goto out_unmap_prot_sg;
  327. }
  328. ret = rdma_rw_init_one_mr(qp, port_num, &ctx->sig->data, sg, sg_cnt, 0);
  329. if (ret < 0)
  330. goto out_free_ctx;
  331. count += ret;
  332. prev_wr = &ctx->sig->data.reg_wr.wr;
  333. if (prot_sg_cnt) {
  334. ret = rdma_rw_init_one_mr(qp, port_num, &ctx->sig->prot,
  335. prot_sg, prot_sg_cnt, 0);
  336. if (ret < 0)
  337. goto out_destroy_data_mr;
  338. count += ret;
  339. if (ctx->sig->prot.inv_wr.next)
  340. prev_wr->next = &ctx->sig->prot.inv_wr;
  341. else
  342. prev_wr->next = &ctx->sig->prot.reg_wr.wr;
  343. prev_wr = &ctx->sig->prot.reg_wr.wr;
  344. } else {
  345. ctx->sig->prot.mr = NULL;
  346. }
  347. ctx->sig->sig_mr = ib_mr_pool_get(qp, &qp->sig_mrs);
  348. if (!ctx->sig->sig_mr) {
  349. ret = -EAGAIN;
  350. goto out_destroy_prot_mr;
  351. }
  352. if (ctx->sig->sig_mr->need_inval) {
  353. memset(&ctx->sig->sig_inv_wr, 0, sizeof(ctx->sig->sig_inv_wr));
  354. ctx->sig->sig_inv_wr.opcode = IB_WR_LOCAL_INV;
  355. ctx->sig->sig_inv_wr.ex.invalidate_rkey = ctx->sig->sig_mr->rkey;
  356. prev_wr->next = &ctx->sig->sig_inv_wr;
  357. prev_wr = &ctx->sig->sig_inv_wr;
  358. }
  359. ctx->sig->sig_wr.wr.opcode = IB_WR_REG_SIG_MR;
  360. ctx->sig->sig_wr.wr.wr_cqe = NULL;
  361. ctx->sig->sig_wr.wr.sg_list = &ctx->sig->data.sge;
  362. ctx->sig->sig_wr.wr.num_sge = 1;
  363. ctx->sig->sig_wr.access_flags = IB_ACCESS_LOCAL_WRITE;
  364. ctx->sig->sig_wr.sig_attrs = sig_attrs;
  365. ctx->sig->sig_wr.sig_mr = ctx->sig->sig_mr;
  366. if (prot_sg_cnt)
  367. ctx->sig->sig_wr.prot = &ctx->sig->prot.sge;
  368. prev_wr->next = &ctx->sig->sig_wr.wr;
  369. prev_wr = &ctx->sig->sig_wr.wr;
  370. count++;
  371. ctx->sig->sig_sge.addr = 0;
  372. ctx->sig->sig_sge.length = ctx->sig->data.sge.length;
  373. if (sig_attrs->wire.sig_type != IB_SIG_TYPE_NONE)
  374. ctx->sig->sig_sge.length += ctx->sig->prot.sge.length;
  375. rdma_wr = &ctx->sig->data.wr;
  376. rdma_wr->wr.sg_list = &ctx->sig->sig_sge;
  377. rdma_wr->wr.num_sge = 1;
  378. rdma_wr->remote_addr = remote_addr;
  379. rdma_wr->rkey = rkey;
  380. if (dir == DMA_TO_DEVICE)
  381. rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
  382. else
  383. rdma_wr->wr.opcode = IB_WR_RDMA_READ;
  384. prev_wr->next = &rdma_wr->wr;
  385. prev_wr = &rdma_wr->wr;
  386. count++;
  387. return count;
  388. out_destroy_prot_mr:
  389. if (prot_sg_cnt)
  390. ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->sig->prot.mr);
  391. out_destroy_data_mr:
  392. ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->sig->data.mr);
  393. out_free_ctx:
  394. kfree(ctx->sig);
  395. out_unmap_prot_sg:
  396. ib_dma_unmap_sg(dev, prot_sg, prot_sg_cnt, dir);
  397. out_unmap_sg:
  398. ib_dma_unmap_sg(dev, sg, sg_cnt, dir);
  399. return ret;
  400. }
  401. EXPORT_SYMBOL(rdma_rw_ctx_signature_init);
  402. /*
  403. * Now that we are going to post the WRs we can update the lkey and need_inval
  404. * state on the MRs. If we were doing this at init time, we would get double
  405. * or missing invalidations if a context was initialized but not actually
  406. * posted.
  407. */
  408. static void rdma_rw_update_lkey(struct rdma_rw_reg_ctx *reg, bool need_inval)
  409. {
  410. reg->mr->need_inval = need_inval;
  411. ib_update_fast_reg_key(reg->mr, ib_inc_rkey(reg->mr->lkey));
  412. reg->reg_wr.key = reg->mr->lkey;
  413. reg->sge.lkey = reg->mr->lkey;
  414. }
  415. /**
  416. * rdma_rw_ctx_wrs - return chain of WRs for a RDMA READ or WRITE operation
  417. * @ctx: context to operate on
  418. * @qp: queue pair to operate on
  419. * @port_num: port num to which the connection is bound
  420. * @cqe: completion queue entry for the last WR
  421. * @chain_wr: WR to append to the posted chain
  422. *
  423. * Return the WR chain for the set of RDMA READ/WRITE operations described by
  424. * @ctx, as well as any memory registration operations needed. If @chain_wr
  425. * is non-NULL the WR it points to will be appended to the chain of WRs posted.
  426. * If @chain_wr is not set @cqe must be set so that the caller gets a
  427. * completion notification.
  428. */
  429. struct ib_send_wr *rdma_rw_ctx_wrs(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  430. u8 port_num, struct ib_cqe *cqe, struct ib_send_wr *chain_wr)
  431. {
  432. struct ib_send_wr *first_wr, *last_wr;
  433. int i;
  434. switch (ctx->type) {
  435. case RDMA_RW_SIG_MR:
  436. rdma_rw_update_lkey(&ctx->sig->data, true);
  437. if (ctx->sig->prot.mr)
  438. rdma_rw_update_lkey(&ctx->sig->prot, true);
  439. ctx->sig->sig_mr->need_inval = true;
  440. ib_update_fast_reg_key(ctx->sig->sig_mr,
  441. ib_inc_rkey(ctx->sig->sig_mr->lkey));
  442. ctx->sig->sig_sge.lkey = ctx->sig->sig_mr->lkey;
  443. if (ctx->sig->data.inv_wr.next)
  444. first_wr = &ctx->sig->data.inv_wr;
  445. else
  446. first_wr = &ctx->sig->data.reg_wr.wr;
  447. last_wr = &ctx->sig->data.wr.wr;
  448. break;
  449. case RDMA_RW_MR:
  450. for (i = 0; i < ctx->nr_ops; i++) {
  451. rdma_rw_update_lkey(&ctx->reg[i],
  452. ctx->reg[i].wr.wr.opcode !=
  453. IB_WR_RDMA_READ_WITH_INV);
  454. }
  455. if (ctx->reg[0].inv_wr.next)
  456. first_wr = &ctx->reg[0].inv_wr;
  457. else
  458. first_wr = &ctx->reg[0].reg_wr.wr;
  459. last_wr = &ctx->reg[ctx->nr_ops - 1].wr.wr;
  460. break;
  461. case RDMA_RW_MULTI_WR:
  462. first_wr = &ctx->map.wrs[0].wr;
  463. last_wr = &ctx->map.wrs[ctx->nr_ops - 1].wr;
  464. break;
  465. case RDMA_RW_SINGLE_WR:
  466. first_wr = &ctx->single.wr.wr;
  467. last_wr = &ctx->single.wr.wr;
  468. break;
  469. default:
  470. BUG();
  471. }
  472. if (chain_wr) {
  473. last_wr->next = chain_wr;
  474. } else {
  475. last_wr->wr_cqe = cqe;
  476. last_wr->send_flags |= IB_SEND_SIGNALED;
  477. }
  478. return first_wr;
  479. }
  480. EXPORT_SYMBOL(rdma_rw_ctx_wrs);
  481. /**
  482. * rdma_rw_ctx_post - post a RDMA READ or RDMA WRITE operation
  483. * @ctx: context to operate on
  484. * @qp: queue pair to operate on
  485. * @port_num: port num to which the connection is bound
  486. * @cqe: completion queue entry for the last WR
  487. * @chain_wr: WR to append to the posted chain
  488. *
  489. * Post the set of RDMA READ/WRITE operations described by @ctx, as well as
  490. * any memory registration operations needed. If @chain_wr is non-NULL the
  491. * WR it points to will be appended to the chain of WRs posted. If @chain_wr
  492. * is not set @cqe must be set so that the caller gets a completion
  493. * notification.
  494. */
  495. int rdma_rw_ctx_post(struct rdma_rw_ctx *ctx, struct ib_qp *qp, u8 port_num,
  496. struct ib_cqe *cqe, struct ib_send_wr *chain_wr)
  497. {
  498. struct ib_send_wr *first_wr, *bad_wr;
  499. first_wr = rdma_rw_ctx_wrs(ctx, qp, port_num, cqe, chain_wr);
  500. return ib_post_send(qp, first_wr, &bad_wr);
  501. }
  502. EXPORT_SYMBOL(rdma_rw_ctx_post);
  503. /**
  504. * rdma_rw_ctx_destroy - release all resources allocated by rdma_rw_ctx_init
  505. * @ctx: context to release
  506. * @qp: queue pair to operate on
  507. * @port_num: port num to which the connection is bound
  508. * @sg: scatterlist that was used for the READ/WRITE
  509. * @sg_cnt: number of entries in @sg
  510. * @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
  511. */
  512. void rdma_rw_ctx_destroy(struct rdma_rw_ctx *ctx, struct ib_qp *qp, u8 port_num,
  513. struct scatterlist *sg, u32 sg_cnt, enum dma_data_direction dir)
  514. {
  515. int i;
  516. switch (ctx->type) {
  517. case RDMA_RW_MR:
  518. for (i = 0; i < ctx->nr_ops; i++)
  519. ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->reg[i].mr);
  520. kfree(ctx->reg);
  521. break;
  522. case RDMA_RW_MULTI_WR:
  523. kfree(ctx->map.wrs);
  524. kfree(ctx->map.sges);
  525. break;
  526. case RDMA_RW_SINGLE_WR:
  527. break;
  528. default:
  529. BUG();
  530. break;
  531. }
  532. ib_dma_unmap_sg(qp->pd->device, sg, sg_cnt, dir);
  533. }
  534. EXPORT_SYMBOL(rdma_rw_ctx_destroy);
  535. /**
  536. * rdma_rw_ctx_destroy_signature - release all resources allocated by
  537. * rdma_rw_ctx_init_signature
  538. * @ctx: context to release
  539. * @qp: queue pair to operate on
  540. * @port_num: port num to which the connection is bound
  541. * @sg: scatterlist that was used for the READ/WRITE
  542. * @sg_cnt: number of entries in @sg
  543. * @prot_sg: scatterlist that was used for the READ/WRITE of the PI
  544. * @prot_sg_cnt: number of entries in @prot_sg
  545. * @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
  546. */
  547. void rdma_rw_ctx_destroy_signature(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  548. u8 port_num, struct scatterlist *sg, u32 sg_cnt,
  549. struct scatterlist *prot_sg, u32 prot_sg_cnt,
  550. enum dma_data_direction dir)
  551. {
  552. if (WARN_ON_ONCE(ctx->type != RDMA_RW_SIG_MR))
  553. return;
  554. ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->sig->data.mr);
  555. ib_dma_unmap_sg(qp->pd->device, sg, sg_cnt, dir);
  556. if (ctx->sig->prot.mr) {
  557. ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->sig->prot.mr);
  558. ib_dma_unmap_sg(qp->pd->device, prot_sg, prot_sg_cnt, dir);
  559. }
  560. ib_mr_pool_put(qp, &qp->sig_mrs, ctx->sig->sig_mr);
  561. kfree(ctx->sig);
  562. }
  563. EXPORT_SYMBOL(rdma_rw_ctx_destroy_signature);
  564. void rdma_rw_init_qp(struct ib_device *dev, struct ib_qp_init_attr *attr)
  565. {
  566. u32 factor;
  567. WARN_ON_ONCE(attr->port_num == 0);
  568. /*
  569. * Each context needs at least one RDMA READ or WRITE WR.
  570. *
  571. * For some hardware we might need more, eventually we should ask the
  572. * HCA driver for a multiplier here.
  573. */
  574. factor = 1;
  575. /*
  576. * If the devices needs MRs to perform RDMA READ or WRITE operations,
  577. * we'll need two additional MRs for the registrations and the
  578. * invalidation.
  579. */
  580. if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
  581. factor += 6; /* (inv + reg) * (data + prot + sig) */
  582. else if (rdma_rw_can_use_mr(dev, attr->port_num))
  583. factor += 2; /* inv + reg */
  584. attr->cap.max_send_wr += factor * attr->cap.max_rdma_ctxs;
  585. /*
  586. * But maybe we were just too high in the sky and the device doesn't
  587. * even support all we need, and we'll have to live with what we get..
  588. */
  589. attr->cap.max_send_wr =
  590. min_t(u32, attr->cap.max_send_wr, dev->attrs.max_qp_wr);
  591. }
  592. int rdma_rw_init_mrs(struct ib_qp *qp, struct ib_qp_init_attr *attr)
  593. {
  594. struct ib_device *dev = qp->pd->device;
  595. u32 nr_mrs = 0, nr_sig_mrs = 0;
  596. int ret = 0;
  597. if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) {
  598. nr_sig_mrs = attr->cap.max_rdma_ctxs;
  599. nr_mrs = attr->cap.max_rdma_ctxs * 2;
  600. } else if (rdma_rw_can_use_mr(dev, attr->port_num)) {
  601. nr_mrs = attr->cap.max_rdma_ctxs;
  602. }
  603. if (nr_mrs) {
  604. ret = ib_mr_pool_init(qp, &qp->rdma_mrs, nr_mrs,
  605. IB_MR_TYPE_MEM_REG,
  606. rdma_rw_fr_page_list_len(dev));
  607. if (ret) {
  608. pr_err("%s: failed to allocated %d MRs\n",
  609. __func__, nr_mrs);
  610. return ret;
  611. }
  612. }
  613. if (nr_sig_mrs) {
  614. ret = ib_mr_pool_init(qp, &qp->sig_mrs, nr_sig_mrs,
  615. IB_MR_TYPE_SIGNATURE, 2);
  616. if (ret) {
  617. pr_err("%s: failed to allocated %d SIG MRs\n",
  618. __func__, nr_mrs);
  619. goto out_free_rdma_mrs;
  620. }
  621. }
  622. return 0;
  623. out_free_rdma_mrs:
  624. ib_mr_pool_destroy(qp, &qp->rdma_mrs);
  625. return ret;
  626. }
  627. void rdma_rw_cleanup_mrs(struct ib_qp *qp)
  628. {
  629. ib_mr_pool_destroy(qp, &qp->sig_mrs);
  630. ib_mr_pool_destroy(qp, &qp->rdma_mrs);
  631. }