octeon_edac-pci.c 2.7 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2012 Cavium, Inc.
  7. * Copyright (C) 2009 Wind River Systems,
  8. * written by Ralf Baechle <ralf@linux-mips.org>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/slab.h>
  13. #include <linux/io.h>
  14. #include <linux/edac.h>
  15. #include <asm/octeon/cvmx.h>
  16. #include <asm/octeon/cvmx-npi-defs.h>
  17. #include <asm/octeon/cvmx-pci-defs.h>
  18. #include <asm/octeon/octeon.h>
  19. #include "edac_core.h"
  20. #include "edac_module.h"
  21. static void octeon_pci_poll(struct edac_pci_ctl_info *pci)
  22. {
  23. union cvmx_pci_cfg01 cfg01;
  24. cfg01.u32 = octeon_npi_read32(CVMX_NPI_PCI_CFG01);
  25. if (cfg01.s.dpe) { /* Detected parity error */
  26. edac_pci_handle_pe(pci, pci->ctl_name);
  27. cfg01.s.dpe = 1; /* Reset */
  28. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  29. }
  30. if (cfg01.s.sse) {
  31. edac_pci_handle_npe(pci, "Signaled System Error");
  32. cfg01.s.sse = 1; /* Reset */
  33. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  34. }
  35. if (cfg01.s.rma) {
  36. edac_pci_handle_npe(pci, "Received Master Abort");
  37. cfg01.s.rma = 1; /* Reset */
  38. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  39. }
  40. if (cfg01.s.rta) {
  41. edac_pci_handle_npe(pci, "Received Target Abort");
  42. cfg01.s.rta = 1; /* Reset */
  43. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  44. }
  45. if (cfg01.s.sta) {
  46. edac_pci_handle_npe(pci, "Signaled Target Abort");
  47. cfg01.s.sta = 1; /* Reset */
  48. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  49. }
  50. if (cfg01.s.mdpe) {
  51. edac_pci_handle_npe(pci, "Master Data Parity Error");
  52. cfg01.s.mdpe = 1; /* Reset */
  53. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  54. }
  55. }
  56. static int octeon_pci_probe(struct platform_device *pdev)
  57. {
  58. struct edac_pci_ctl_info *pci;
  59. int res = 0;
  60. pci = edac_pci_alloc_ctl_info(0, "octeon_pci_err");
  61. if (!pci)
  62. return -ENOMEM;
  63. pci->dev = &pdev->dev;
  64. platform_set_drvdata(pdev, pci);
  65. pci->dev_name = dev_name(&pdev->dev);
  66. pci->mod_name = "octeon-pci";
  67. pci->ctl_name = "octeon_pci_err";
  68. pci->edac_check = octeon_pci_poll;
  69. if (edac_pci_add_device(pci, 0) > 0) {
  70. pr_err("%s: edac_pci_add_device() failed\n", __func__);
  71. goto err;
  72. }
  73. return 0;
  74. err:
  75. edac_pci_free_ctl_info(pci);
  76. return res;
  77. }
  78. static int octeon_pci_remove(struct platform_device *pdev)
  79. {
  80. struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev);
  81. edac_pci_del_device(&pdev->dev);
  82. edac_pci_free_ctl_info(pci);
  83. return 0;
  84. }
  85. static struct platform_driver octeon_pci_driver = {
  86. .probe = octeon_pci_probe,
  87. .remove = octeon_pci_remove,
  88. .driver = {
  89. .name = "octeon_pci_edac",
  90. }
  91. };
  92. module_platform_driver(octeon_pci_driver);
  93. MODULE_LICENSE("GPL");
  94. MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");