ccu-sun8i-a23-a33.h 1.6 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364
  1. /*
  2. * Copyright 2016 Maxime Ripard
  3. *
  4. * Maxime Ripard <maxime.ripard@free-electrons.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #ifndef _CCU_SUN8I_A23_A33_H_
  17. #define _CCU_SUN8I_A23_A33_H_
  18. #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
  19. #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
  20. #define CLK_PLL_CPUX 0
  21. #define CLK_PLL_AUDIO_BASE 1
  22. #define CLK_PLL_AUDIO 2
  23. #define CLK_PLL_AUDIO_2X 3
  24. #define CLK_PLL_AUDIO_4X 4
  25. #define CLK_PLL_AUDIO_8X 5
  26. #define CLK_PLL_VIDEO 6
  27. #define CLK_PLL_VIDEO_2X 7
  28. #define CLK_PLL_VE 8
  29. #define CLK_PLL_DDR0 9
  30. #define CLK_PLL_PERIPH 10
  31. #define CLK_PLL_PERIPH_2X 11
  32. #define CLK_PLL_GPU 12
  33. #define CLK_PLL_MIPI 13
  34. #define CLK_PLL_HSIC 14
  35. #define CLK_PLL_DE 15
  36. #define CLK_PLL_DDR1 16
  37. #define CLK_PLL_DDR 17
  38. /* The CPUX clock is exported */
  39. #define CLK_AXI 19
  40. #define CLK_AHB1 20
  41. #define CLK_APB1 21
  42. #define CLK_APB2 22
  43. /* All the bus gates are exported */
  44. /* The first part of the mod clocks is exported */
  45. #define CLK_DRAM 79
  46. /* Some more module clocks are exported */
  47. #define CLK_MBUS 95
  48. /* And the last module clocks are exported */
  49. #define CLK_NUMBER (CLK_ATS + 1)
  50. #endif /* _CCU_SUN8I_A23_A33_H_ */