clk-pll.h 2.1 KB

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  1. /*
  2. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  3. * Copyright (c) 2013 Linaro Ltd.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * Common Clock Framework support for all PLL's in Samsung platforms
  10. */
  11. #ifndef __SAMSUNG_CLK_PLL_H
  12. #define __SAMSUNG_CLK_PLL_H
  13. enum samsung_pll_type {
  14. pll_2126,
  15. pll_3000,
  16. pll_35xx,
  17. pll_36xx,
  18. pll_2550,
  19. pll_2650,
  20. pll_4500,
  21. pll_4502,
  22. pll_4508,
  23. pll_4600,
  24. pll_4650,
  25. pll_4650c,
  26. pll_6552,
  27. pll_6552_s3c2416,
  28. pll_6553,
  29. pll_s3c2410_mpll,
  30. pll_s3c2410_upll,
  31. pll_s3c2440_mpll,
  32. pll_2550x,
  33. pll_2550xx,
  34. pll_2650x,
  35. pll_2650xx,
  36. pll_1450x,
  37. pll_1451x,
  38. pll_1452x,
  39. pll_1460x,
  40. };
  41. #define PLL_35XX_RATE(_rate, _m, _p, _s) \
  42. { \
  43. .rate = (_rate), \
  44. .mdiv = (_m), \
  45. .pdiv = (_p), \
  46. .sdiv = (_s), \
  47. }
  48. #define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \
  49. { \
  50. .rate = (_rate), \
  51. .mdiv = (_m), \
  52. .pdiv = (_p), \
  53. .sdiv = (_s), \
  54. .kdiv = (_k), \
  55. }
  56. #define PLL_45XX_RATE(_rate, _m, _p, _s, _afc) \
  57. { \
  58. .rate = (_rate), \
  59. .mdiv = (_m), \
  60. .pdiv = (_p), \
  61. .sdiv = (_s), \
  62. .afc = (_afc), \
  63. }
  64. #define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel) \
  65. { \
  66. .rate = (_rate), \
  67. .mdiv = (_m), \
  68. .pdiv = (_p), \
  69. .sdiv = (_s), \
  70. .kdiv = (_k), \
  71. .vsel = (_vsel), \
  72. }
  73. #define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
  74. { \
  75. .rate = (_rate), \
  76. .mdiv = (_m), \
  77. .pdiv = (_p), \
  78. .sdiv = (_s), \
  79. .kdiv = (_k), \
  80. .mfr = (_mfr), \
  81. .mrr = (_mrr), \
  82. .vsel = (_vsel), \
  83. }
  84. /* NOTE: Rate table should be kept sorted in descending order. */
  85. struct samsung_pll_rate_table {
  86. unsigned int rate;
  87. unsigned int pdiv;
  88. unsigned int mdiv;
  89. unsigned int sdiv;
  90. unsigned int kdiv;
  91. unsigned int afc;
  92. unsigned int mfr;
  93. unsigned int mrr;
  94. unsigned int vsel;
  95. };
  96. extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
  97. const char *pname, const void __iomem *reg_base,
  98. const unsigned long offset);
  99. #endif /* __SAMSUNG_CLK_PLL_H */