irq.c 2.9 KB

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  1. /*
  2. * arch/score/kernel/irq.c
  3. *
  4. * Score Processor version.
  5. *
  6. * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
  7. * Chen Liqin <liqin.chen@sunplusct.com>
  8. * Lennox Wu <lennox.wu@sunplusct.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, see the file COPYING, or write
  22. * to the Free Software Foundation, Inc.,
  23. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  24. */
  25. #include <linux/interrupt.h>
  26. #include <linux/kernel_stat.h>
  27. #include <linux/seq_file.h>
  28. #include <asm/io.h>
  29. /* the interrupt controller is hardcoded at this address */
  30. #define SCORE_PIC ((u32 __iomem __force *)0x95F50000)
  31. #define INT_PNDL 0
  32. #define INT_PNDH 1
  33. #define INT_PRIORITY_M 2
  34. #define INT_PRIORITY_SG0 4
  35. #define INT_PRIORITY_SG1 5
  36. #define INT_PRIORITY_SG2 6
  37. #define INT_PRIORITY_SG3 7
  38. #define INT_MASKL 8
  39. #define INT_MASKH 9
  40. /*
  41. * handles all normal device IRQs
  42. */
  43. asmlinkage void do_IRQ(int irq)
  44. {
  45. irq_enter();
  46. generic_handle_irq(irq);
  47. irq_exit();
  48. }
  49. static void score_mask(struct irq_data *d)
  50. {
  51. unsigned int irq_source = 63 - d->irq;
  52. if (irq_source < 32)
  53. __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) | \
  54. (1 << irq_source)), SCORE_PIC + INT_MASKL);
  55. else
  56. __raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) | \
  57. (1 << (irq_source - 32))), SCORE_PIC + INT_MASKH);
  58. }
  59. static void score_unmask(struct irq_data *d)
  60. {
  61. unsigned int irq_source = 63 - d->irq;
  62. if (irq_source < 32)
  63. __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) & \
  64. ~(1 << irq_source)), SCORE_PIC + INT_MASKL);
  65. else
  66. __raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) & \
  67. ~(1 << (irq_source - 32))), SCORE_PIC + INT_MASKH);
  68. }
  69. struct irq_chip score_irq_chip = {
  70. .name = "Score7-level",
  71. .irq_mask = score_mask,
  72. .irq_mask_ack = score_mask,
  73. .irq_unmask = score_unmask,
  74. };
  75. /*
  76. * initialise the interrupt system
  77. */
  78. void __init init_IRQ(void)
  79. {
  80. int index;
  81. unsigned long target_addr;
  82. for (index = 0; index < NR_IRQS; ++index)
  83. irq_set_chip_and_handler(index, &score_irq_chip,
  84. handle_level_irq);
  85. for (target_addr = IRQ_VECTOR_BASE_ADDR;
  86. target_addr <= IRQ_VECTOR_END_ADDR;
  87. target_addr += IRQ_VECTOR_SIZE)
  88. memcpy((void *)target_addr, \
  89. interrupt_exception_vector, IRQ_VECTOR_SIZE);
  90. __raw_writel(0xffffffff, SCORE_PIC + INT_MASKL);
  91. __raw_writel(0xffffffff, SCORE_PIC + INT_MASKH);
  92. __asm__ __volatile__(
  93. "mtcr %0, cr3\n\t"
  94. : : "r" (EXCEPTION_VECTOR_BASE_ADDR | \
  95. VECTOR_ADDRESS_OFFSET_MODE16));
  96. }