mpic_msgr.c 6.8 KB

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  1. /*
  2. * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
  3. *
  4. * Some ideas based on un-pushed work done by Vivek Mahajan, Jason Jin, and
  5. * Mingkai Hu from Freescale Semiconductor, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; version 2 of the
  10. * License.
  11. *
  12. */
  13. #include <linux/list.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/errno.h>
  16. #include <linux/err.h>
  17. #include <linux/export.h>
  18. #include <linux/slab.h>
  19. #include <asm/prom.h>
  20. #include <asm/hw_irq.h>
  21. #include <asm/ppc-pci.h>
  22. #include <asm/mpic_msgr.h>
  23. #define MPIC_MSGR_REGISTERS_PER_BLOCK 4
  24. #define MPIC_MSGR_STRIDE 0x10
  25. #define MPIC_MSGR_MER_OFFSET 0x100
  26. #define MSGR_INUSE 0
  27. #define MSGR_FREE 1
  28. static struct mpic_msgr **mpic_msgrs;
  29. static unsigned int mpic_msgr_count;
  30. static DEFINE_RAW_SPINLOCK(msgrs_lock);
  31. static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
  32. {
  33. out_be32(msgr->mer, value);
  34. }
  35. static inline u32 _mpic_msgr_mer_read(struct mpic_msgr *msgr)
  36. {
  37. return in_be32(msgr->mer);
  38. }
  39. static inline void _mpic_msgr_disable(struct mpic_msgr *msgr)
  40. {
  41. u32 mer = _mpic_msgr_mer_read(msgr);
  42. _mpic_msgr_mer_write(msgr, mer & ~(1 << msgr->num));
  43. }
  44. struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
  45. {
  46. unsigned long flags;
  47. struct mpic_msgr *msgr;
  48. /* Assume busy until proven otherwise. */
  49. msgr = ERR_PTR(-EBUSY);
  50. if (reg_num >= mpic_msgr_count)
  51. return ERR_PTR(-ENODEV);
  52. raw_spin_lock_irqsave(&msgrs_lock, flags);
  53. msgr = mpic_msgrs[reg_num];
  54. if (msgr->in_use == MSGR_FREE)
  55. msgr->in_use = MSGR_INUSE;
  56. raw_spin_unlock_irqrestore(&msgrs_lock, flags);
  57. return msgr;
  58. }
  59. EXPORT_SYMBOL_GPL(mpic_msgr_get);
  60. void mpic_msgr_put(struct mpic_msgr *msgr)
  61. {
  62. unsigned long flags;
  63. raw_spin_lock_irqsave(&msgr->lock, flags);
  64. msgr->in_use = MSGR_FREE;
  65. _mpic_msgr_disable(msgr);
  66. raw_spin_unlock_irqrestore(&msgr->lock, flags);
  67. }
  68. EXPORT_SYMBOL_GPL(mpic_msgr_put);
  69. void mpic_msgr_enable(struct mpic_msgr *msgr)
  70. {
  71. unsigned long flags;
  72. u32 mer;
  73. raw_spin_lock_irqsave(&msgr->lock, flags);
  74. mer = _mpic_msgr_mer_read(msgr);
  75. _mpic_msgr_mer_write(msgr, mer | (1 << msgr->num));
  76. raw_spin_unlock_irqrestore(&msgr->lock, flags);
  77. }
  78. EXPORT_SYMBOL_GPL(mpic_msgr_enable);
  79. void mpic_msgr_disable(struct mpic_msgr *msgr)
  80. {
  81. unsigned long flags;
  82. raw_spin_lock_irqsave(&msgr->lock, flags);
  83. _mpic_msgr_disable(msgr);
  84. raw_spin_unlock_irqrestore(&msgr->lock, flags);
  85. }
  86. EXPORT_SYMBOL_GPL(mpic_msgr_disable);
  87. /* The following three functions are used to compute the order and number of
  88. * the message register blocks. They are clearly very inefficent. However,
  89. * they are called *only* a few times during device initialization.
  90. */
  91. static unsigned int mpic_msgr_number_of_blocks(void)
  92. {
  93. unsigned int count;
  94. struct device_node *aliases;
  95. count = 0;
  96. aliases = of_find_node_by_name(NULL, "aliases");
  97. if (aliases) {
  98. char buf[32];
  99. for (;;) {
  100. snprintf(buf, sizeof(buf), "mpic-msgr-block%d", count);
  101. if (!of_find_property(aliases, buf, NULL))
  102. break;
  103. count += 1;
  104. }
  105. }
  106. return count;
  107. }
  108. static unsigned int mpic_msgr_number_of_registers(void)
  109. {
  110. return mpic_msgr_number_of_blocks() * MPIC_MSGR_REGISTERS_PER_BLOCK;
  111. }
  112. static int mpic_msgr_block_number(struct device_node *node)
  113. {
  114. struct device_node *aliases;
  115. unsigned int index, number_of_blocks;
  116. char buf[64];
  117. number_of_blocks = mpic_msgr_number_of_blocks();
  118. aliases = of_find_node_by_name(NULL, "aliases");
  119. if (!aliases)
  120. return -1;
  121. for (index = 0; index < number_of_blocks; ++index) {
  122. struct property *prop;
  123. snprintf(buf, sizeof(buf), "mpic-msgr-block%d", index);
  124. prop = of_find_property(aliases, buf, NULL);
  125. if (node == of_find_node_by_path(prop->value))
  126. break;
  127. }
  128. return index == number_of_blocks ? -1 : index;
  129. }
  130. /* The probe function for a single message register block.
  131. */
  132. static int mpic_msgr_probe(struct platform_device *dev)
  133. {
  134. void __iomem *msgr_block_addr;
  135. int block_number;
  136. struct resource rsrc;
  137. unsigned int i;
  138. unsigned int irq_index;
  139. struct device_node *np = dev->dev.of_node;
  140. unsigned int receive_mask;
  141. const unsigned int *prop;
  142. if (!np) {
  143. dev_err(&dev->dev, "Device OF-Node is NULL");
  144. return -EFAULT;
  145. }
  146. /* Allocate the message register array upon the first device
  147. * registered.
  148. */
  149. if (!mpic_msgrs) {
  150. mpic_msgr_count = mpic_msgr_number_of_registers();
  151. dev_info(&dev->dev, "Found %d message registers\n",
  152. mpic_msgr_count);
  153. mpic_msgrs = kcalloc(mpic_msgr_count, sizeof(*mpic_msgrs),
  154. GFP_KERNEL);
  155. if (!mpic_msgrs) {
  156. dev_err(&dev->dev,
  157. "No memory for message register blocks\n");
  158. return -ENOMEM;
  159. }
  160. }
  161. dev_info(&dev->dev, "Of-device full name %s\n", np->full_name);
  162. /* IO map the message register block. */
  163. of_address_to_resource(np, 0, &rsrc);
  164. msgr_block_addr = ioremap(rsrc.start, rsrc.end - rsrc.start);
  165. if (!msgr_block_addr) {
  166. dev_err(&dev->dev, "Failed to iomap MPIC message registers");
  167. return -EFAULT;
  168. }
  169. /* Ensure the block has a defined order. */
  170. block_number = mpic_msgr_block_number(np);
  171. if (block_number < 0) {
  172. dev_err(&dev->dev,
  173. "Failed to find message register block alias\n");
  174. return -ENODEV;
  175. }
  176. dev_info(&dev->dev, "Setting up message register block %d\n",
  177. block_number);
  178. /* Grab the receive mask which specifies what registers can receive
  179. * interrupts.
  180. */
  181. prop = of_get_property(np, "mpic-msgr-receive-mask", NULL);
  182. receive_mask = (prop) ? *prop : 0xF;
  183. /* Build up the appropriate message register data structures. */
  184. for (i = 0, irq_index = 0; i < MPIC_MSGR_REGISTERS_PER_BLOCK; ++i) {
  185. struct mpic_msgr *msgr;
  186. unsigned int reg_number;
  187. msgr = kzalloc(sizeof(struct mpic_msgr), GFP_KERNEL);
  188. if (!msgr) {
  189. dev_err(&dev->dev, "No memory for message register\n");
  190. return -ENOMEM;
  191. }
  192. reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
  193. msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
  194. msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET);
  195. msgr->in_use = MSGR_FREE;
  196. msgr->num = i;
  197. raw_spin_lock_init(&msgr->lock);
  198. if (receive_mask & (1 << i)) {
  199. msgr->irq = irq_of_parse_and_map(np, irq_index);
  200. if (!msgr->irq) {
  201. dev_err(&dev->dev,
  202. "Missing interrupt specifier");
  203. kfree(msgr);
  204. return -EFAULT;
  205. }
  206. irq_index += 1;
  207. } else {
  208. msgr->irq = 0;
  209. }
  210. mpic_msgrs[reg_number] = msgr;
  211. mpic_msgr_disable(msgr);
  212. dev_info(&dev->dev, "Register %d initialized: irq %d\n",
  213. reg_number, msgr->irq);
  214. }
  215. return 0;
  216. }
  217. static const struct of_device_id mpic_msgr_ids[] = {
  218. {
  219. .compatible = "fsl,mpic-v3.1-msgr",
  220. .data = NULL,
  221. },
  222. {}
  223. };
  224. static struct platform_driver mpic_msgr_driver = {
  225. .driver = {
  226. .name = "mpic-msgr",
  227. .of_match_table = mpic_msgr_ids,
  228. },
  229. .probe = mpic_msgr_probe,
  230. };
  231. static __init int mpic_msgr_init(void)
  232. {
  233. return platform_driver_register(&mpic_msgr_driver);
  234. }
  235. subsys_initcall(mpic_msgr_init);