traps.c 18 KB

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  1. /*
  2. * Based on arch/arm/kernel/traps.c
  3. *
  4. * Copyright (C) 1995-2009 Russell King
  5. * Copyright (C) 2012 ARM Ltd.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/bug.h>
  20. #include <linux/signal.h>
  21. #include <linux/personality.h>
  22. #include <linux/kallsyms.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/uaccess.h>
  25. #include <linux/hardirq.h>
  26. #include <linux/kdebug.h>
  27. #include <linux/module.h>
  28. #include <linux/kexec.h>
  29. #include <linux/delay.h>
  30. #include <linux/init.h>
  31. #include <linux/sched.h>
  32. #include <linux/syscalls.h>
  33. #include <asm/atomic.h>
  34. #include <asm/bug.h>
  35. #include <asm/debug-monitors.h>
  36. #include <asm/esr.h>
  37. #include <asm/insn.h>
  38. #include <asm/traps.h>
  39. #include <asm/stacktrace.h>
  40. #include <asm/exception.h>
  41. #include <asm/system_misc.h>
  42. #include <asm/sysreg.h>
  43. static const char *handler[]= {
  44. "Synchronous Abort",
  45. "IRQ",
  46. "FIQ",
  47. "Error"
  48. };
  49. int show_unhandled_signals = 0;
  50. /*
  51. * Dump out the contents of some kernel memory nicely...
  52. */
  53. static void dump_mem(const char *lvl, const char *str, unsigned long bottom,
  54. unsigned long top)
  55. {
  56. unsigned long first;
  57. mm_segment_t fs;
  58. int i;
  59. /*
  60. * We need to switch to kernel mode so that we can use __get_user
  61. * to safely read from kernel space.
  62. */
  63. fs = get_fs();
  64. set_fs(KERNEL_DS);
  65. printk("%s%s(0x%016lx to 0x%016lx)\n", lvl, str, bottom, top);
  66. for (first = bottom & ~31; first < top; first += 32) {
  67. unsigned long p;
  68. char str[sizeof(" 12345678") * 8 + 1];
  69. memset(str, ' ', sizeof(str));
  70. str[sizeof(str) - 1] = '\0';
  71. for (p = first, i = 0; i < (32 / 8)
  72. && p < top; i++, p += 8) {
  73. if (p >= bottom && p < top) {
  74. unsigned long val;
  75. if (__get_user(val, (unsigned long *)p) == 0)
  76. sprintf(str + i * 17, " %016lx", val);
  77. else
  78. sprintf(str + i * 17, " ????????????????");
  79. }
  80. }
  81. printk("%s%04lx:%s\n", lvl, first & 0xffff, str);
  82. }
  83. set_fs(fs);
  84. }
  85. static void dump_backtrace_entry(unsigned long where)
  86. {
  87. /*
  88. * Note that 'where' can have a physical address, but it's not handled.
  89. */
  90. print_ip_sym(where);
  91. }
  92. static void __dump_instr(const char *lvl, struct pt_regs *regs)
  93. {
  94. unsigned long addr = instruction_pointer(regs);
  95. char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
  96. int i;
  97. for (i = -4; i < 1; i++) {
  98. unsigned int val, bad;
  99. bad = get_user(val, &((u32 *)addr)[i]);
  100. if (!bad)
  101. p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
  102. else {
  103. p += sprintf(p, "bad PC value");
  104. break;
  105. }
  106. }
  107. printk("%sCode: %s\n", lvl, str);
  108. }
  109. static void dump_instr(const char *lvl, struct pt_regs *regs)
  110. {
  111. if (!user_mode(regs)) {
  112. mm_segment_t fs = get_fs();
  113. set_fs(KERNEL_DS);
  114. __dump_instr(lvl, regs);
  115. set_fs(fs);
  116. } else {
  117. __dump_instr(lvl, regs);
  118. }
  119. }
  120. static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
  121. {
  122. struct stackframe frame;
  123. unsigned long irq_stack_ptr;
  124. int skip;
  125. pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
  126. if (!tsk)
  127. tsk = current;
  128. /*
  129. * Switching between stacks is valid when tracing current and in
  130. * non-preemptible context.
  131. */
  132. if (tsk == current && !preemptible())
  133. irq_stack_ptr = IRQ_STACK_PTR(smp_processor_id());
  134. else
  135. irq_stack_ptr = 0;
  136. if (tsk == current) {
  137. frame.fp = (unsigned long)__builtin_frame_address(0);
  138. frame.sp = current_stack_pointer;
  139. frame.pc = (unsigned long)dump_backtrace;
  140. } else {
  141. /*
  142. * task blocked in __switch_to
  143. */
  144. frame.fp = thread_saved_fp(tsk);
  145. frame.sp = thread_saved_sp(tsk);
  146. frame.pc = thread_saved_pc(tsk);
  147. }
  148. #ifdef CONFIG_FUNCTION_GRAPH_TRACER
  149. frame.graph = tsk->curr_ret_stack;
  150. #endif
  151. skip = !!regs;
  152. printk("Call trace:\n");
  153. while (1) {
  154. unsigned long where = frame.pc;
  155. unsigned long stack;
  156. int ret;
  157. /* skip until specified stack frame */
  158. if (!skip) {
  159. dump_backtrace_entry(where);
  160. } else if (frame.fp == regs->regs[29]) {
  161. skip = 0;
  162. /*
  163. * Mostly, this is the case where this function is
  164. * called in panic/abort. As exception handler's
  165. * stack frame does not contain the corresponding pc
  166. * at which an exception has taken place, use regs->pc
  167. * instead.
  168. */
  169. dump_backtrace_entry(regs->pc);
  170. }
  171. ret = unwind_frame(tsk, &frame);
  172. if (ret < 0)
  173. break;
  174. stack = frame.sp;
  175. if (in_exception_text(where)) {
  176. /*
  177. * If we switched to the irq_stack before calling this
  178. * exception handler, then the pt_regs will be on the
  179. * task stack. The easiest way to tell is if the large
  180. * pt_regs would overlap with the end of the irq_stack.
  181. */
  182. if (stack < irq_stack_ptr &&
  183. (stack + sizeof(struct pt_regs)) > irq_stack_ptr)
  184. stack = IRQ_STACK_TO_TASK_STACK(irq_stack_ptr);
  185. dump_mem("", "Exception stack", stack,
  186. stack + sizeof(struct pt_regs));
  187. }
  188. }
  189. }
  190. void show_stack(struct task_struct *tsk, unsigned long *sp)
  191. {
  192. dump_backtrace(NULL, tsk);
  193. barrier();
  194. }
  195. #ifdef CONFIG_PREEMPT
  196. #define S_PREEMPT " PREEMPT"
  197. #else
  198. #define S_PREEMPT ""
  199. #endif
  200. #define S_SMP " SMP"
  201. static int __die(const char *str, int err, struct thread_info *thread,
  202. struct pt_regs *regs)
  203. {
  204. struct task_struct *tsk = thread->task;
  205. static int die_counter;
  206. int ret;
  207. pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
  208. str, err, ++die_counter);
  209. /* trap and error numbers are mostly meaningless on ARM */
  210. ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
  211. if (ret == NOTIFY_STOP)
  212. return ret;
  213. print_modules();
  214. __show_regs(regs);
  215. pr_emerg("Process %.*s (pid: %d, stack limit = 0x%p)\n",
  216. TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), thread + 1);
  217. if (!user_mode(regs)) {
  218. dump_mem(KERN_EMERG, "Stack: ", regs->sp,
  219. THREAD_SIZE + (unsigned long)task_stack_page(tsk));
  220. dump_backtrace(regs, tsk);
  221. dump_instr(KERN_EMERG, regs);
  222. }
  223. return ret;
  224. }
  225. static DEFINE_RAW_SPINLOCK(die_lock);
  226. /*
  227. * This function is protected against re-entrancy.
  228. */
  229. void die(const char *str, struct pt_regs *regs, int err)
  230. {
  231. struct thread_info *thread = current_thread_info();
  232. int ret;
  233. oops_enter();
  234. raw_spin_lock_irq(&die_lock);
  235. console_verbose();
  236. bust_spinlocks(1);
  237. ret = __die(str, err, thread, regs);
  238. if (regs && kexec_should_crash(thread->task))
  239. crash_kexec(regs);
  240. bust_spinlocks(0);
  241. add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
  242. raw_spin_unlock_irq(&die_lock);
  243. oops_exit();
  244. if (in_interrupt())
  245. panic("Fatal exception in interrupt");
  246. if (panic_on_oops)
  247. panic("Fatal exception");
  248. if (ret != NOTIFY_STOP)
  249. do_exit(SIGSEGV);
  250. }
  251. void arm64_notify_die(const char *str, struct pt_regs *regs,
  252. struct siginfo *info, int err)
  253. {
  254. if (user_mode(regs)) {
  255. current->thread.fault_address = 0;
  256. current->thread.fault_code = err;
  257. force_sig_info(info->si_signo, info, current);
  258. } else {
  259. die(str, regs, err);
  260. }
  261. }
  262. static LIST_HEAD(undef_hook);
  263. static DEFINE_RAW_SPINLOCK(undef_lock);
  264. void register_undef_hook(struct undef_hook *hook)
  265. {
  266. unsigned long flags;
  267. raw_spin_lock_irqsave(&undef_lock, flags);
  268. list_add(&hook->node, &undef_hook);
  269. raw_spin_unlock_irqrestore(&undef_lock, flags);
  270. }
  271. void unregister_undef_hook(struct undef_hook *hook)
  272. {
  273. unsigned long flags;
  274. raw_spin_lock_irqsave(&undef_lock, flags);
  275. list_del(&hook->node);
  276. raw_spin_unlock_irqrestore(&undef_lock, flags);
  277. }
  278. static int call_undef_hook(struct pt_regs *regs)
  279. {
  280. struct undef_hook *hook;
  281. unsigned long flags;
  282. u32 instr;
  283. int (*fn)(struct pt_regs *regs, u32 instr) = NULL;
  284. void __user *pc = (void __user *)instruction_pointer(regs);
  285. if (!user_mode(regs))
  286. return 1;
  287. if (compat_thumb_mode(regs)) {
  288. /* 16-bit Thumb instruction */
  289. if (get_user(instr, (u16 __user *)pc))
  290. goto exit;
  291. instr = le16_to_cpu(instr);
  292. if (aarch32_insn_is_wide(instr)) {
  293. u32 instr2;
  294. if (get_user(instr2, (u16 __user *)(pc + 2)))
  295. goto exit;
  296. instr2 = le16_to_cpu(instr2);
  297. instr = (instr << 16) | instr2;
  298. }
  299. } else {
  300. /* 32-bit ARM instruction */
  301. if (get_user(instr, (u32 __user *)pc))
  302. goto exit;
  303. instr = le32_to_cpu(instr);
  304. }
  305. raw_spin_lock_irqsave(&undef_lock, flags);
  306. list_for_each_entry(hook, &undef_hook, node)
  307. if ((instr & hook->instr_mask) == hook->instr_val &&
  308. (regs->pstate & hook->pstate_mask) == hook->pstate_val)
  309. fn = hook->fn;
  310. raw_spin_unlock_irqrestore(&undef_lock, flags);
  311. exit:
  312. return fn ? fn(regs, instr) : 1;
  313. }
  314. static void force_signal_inject(int signal, int code, struct pt_regs *regs,
  315. unsigned long address)
  316. {
  317. siginfo_t info;
  318. void __user *pc = (void __user *)instruction_pointer(regs);
  319. const char *desc;
  320. switch (signal) {
  321. case SIGILL:
  322. desc = "undefined instruction";
  323. break;
  324. case SIGSEGV:
  325. desc = "illegal memory access";
  326. break;
  327. default:
  328. desc = "bad mode";
  329. break;
  330. }
  331. if (unhandled_signal(current, signal) &&
  332. show_unhandled_signals_ratelimited()) {
  333. pr_info("%s[%d]: %s: pc=%p\n",
  334. current->comm, task_pid_nr(current), desc, pc);
  335. dump_instr(KERN_INFO, regs);
  336. }
  337. info.si_signo = signal;
  338. info.si_errno = 0;
  339. info.si_code = code;
  340. info.si_addr = pc;
  341. arm64_notify_die(desc, regs, &info, 0);
  342. }
  343. /*
  344. * Set up process info to signal segmentation fault - called on access error.
  345. */
  346. void arm64_notify_segfault(struct pt_regs *regs, unsigned long addr)
  347. {
  348. int code;
  349. down_read(&current->mm->mmap_sem);
  350. if (find_vma(current->mm, addr) == NULL)
  351. code = SEGV_MAPERR;
  352. else
  353. code = SEGV_ACCERR;
  354. up_read(&current->mm->mmap_sem);
  355. force_signal_inject(SIGSEGV, code, regs, addr);
  356. }
  357. asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
  358. {
  359. /* check for AArch32 breakpoint instructions */
  360. if (!aarch32_break_handler(regs))
  361. return;
  362. if (call_undef_hook(regs) == 0)
  363. return;
  364. force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
  365. }
  366. int cpu_enable_cache_maint_trap(void *__unused)
  367. {
  368. config_sctlr_el1(SCTLR_EL1_UCI, 0);
  369. return 0;
  370. }
  371. #define __user_cache_maint(insn, address, res) \
  372. if (address >= user_addr_max()) \
  373. res = -EFAULT; \
  374. else \
  375. asm volatile ( \
  376. "1: " insn ", %1\n" \
  377. " mov %w0, #0\n" \
  378. "2:\n" \
  379. " .pushsection .fixup,\"ax\"\n" \
  380. " .align 2\n" \
  381. "3: mov %w0, %w2\n" \
  382. " b 2b\n" \
  383. " .popsection\n" \
  384. _ASM_EXTABLE(1b, 3b) \
  385. : "=r" (res) \
  386. : "r" (address), "i" (-EFAULT) )
  387. static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
  388. {
  389. unsigned long address;
  390. int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
  391. int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
  392. int ret = 0;
  393. address = (rt == 31) ? 0 : untagged_addr(regs->regs[rt]);
  394. switch (crm) {
  395. case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */
  396. __user_cache_maint("dc civac", address, ret);
  397. break;
  398. case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */
  399. __user_cache_maint("dc civac", address, ret);
  400. break;
  401. case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */
  402. __user_cache_maint("dc civac", address, ret);
  403. break;
  404. case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */
  405. __user_cache_maint("ic ivau", address, ret);
  406. break;
  407. default:
  408. force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
  409. return;
  410. }
  411. if (ret)
  412. arm64_notify_segfault(regs, address);
  413. else
  414. regs->pc += 4;
  415. }
  416. static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
  417. {
  418. int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
  419. regs->regs[rt] = arm64_ftr_reg_ctrel0.sys_val;
  420. regs->pc += 4;
  421. }
  422. struct sys64_hook {
  423. unsigned int esr_mask;
  424. unsigned int esr_val;
  425. void (*handler)(unsigned int esr, struct pt_regs *regs);
  426. };
  427. static struct sys64_hook sys64_hooks[] = {
  428. {
  429. .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
  430. .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
  431. .handler = user_cache_maint_handler,
  432. },
  433. {
  434. /* Trap read access to CTR_EL0 */
  435. .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
  436. .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
  437. .handler = ctr_read_handler,
  438. },
  439. {},
  440. };
  441. asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
  442. {
  443. struct sys64_hook *hook;
  444. for (hook = sys64_hooks; hook->handler; hook++)
  445. if ((hook->esr_mask & esr) == hook->esr_val) {
  446. hook->handler(esr, regs);
  447. return;
  448. }
  449. force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
  450. }
  451. long compat_arm_syscall(struct pt_regs *regs);
  452. asmlinkage long do_ni_syscall(struct pt_regs *regs)
  453. {
  454. #ifdef CONFIG_COMPAT
  455. long ret;
  456. if (is_compat_task()) {
  457. ret = compat_arm_syscall(regs);
  458. if (ret != -ENOSYS)
  459. return ret;
  460. }
  461. #endif
  462. if (show_unhandled_signals_ratelimited()) {
  463. pr_info("%s[%d]: syscall %d\n", current->comm,
  464. task_pid_nr(current), (int)regs->syscallno);
  465. dump_instr("", regs);
  466. if (user_mode(regs))
  467. __show_regs(regs);
  468. }
  469. return sys_ni_syscall();
  470. }
  471. static const char *esr_class_str[] = {
  472. [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC",
  473. [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized",
  474. [ESR_ELx_EC_WFx] = "WFI/WFE",
  475. [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC",
  476. [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC",
  477. [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC",
  478. [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC",
  479. [ESR_ELx_EC_FP_ASIMD] = "ASIMD",
  480. [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS",
  481. [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC",
  482. [ESR_ELx_EC_ILL] = "PSTATE.IL",
  483. [ESR_ELx_EC_SVC32] = "SVC (AArch32)",
  484. [ESR_ELx_EC_HVC32] = "HVC (AArch32)",
  485. [ESR_ELx_EC_SMC32] = "SMC (AArch32)",
  486. [ESR_ELx_EC_SVC64] = "SVC (AArch64)",
  487. [ESR_ELx_EC_HVC64] = "HVC (AArch64)",
  488. [ESR_ELx_EC_SMC64] = "SMC (AArch64)",
  489. [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)",
  490. [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF",
  491. [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)",
  492. [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)",
  493. [ESR_ELx_EC_PC_ALIGN] = "PC Alignment",
  494. [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)",
  495. [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)",
  496. [ESR_ELx_EC_SP_ALIGN] = "SP Alignment",
  497. [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)",
  498. [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)",
  499. [ESR_ELx_EC_SERROR] = "SError",
  500. [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)",
  501. [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)",
  502. [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)",
  503. [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)",
  504. [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)",
  505. [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)",
  506. [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)",
  507. [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)",
  508. [ESR_ELx_EC_BRK64] = "BRK (AArch64)",
  509. };
  510. const char *esr_get_class_string(u32 esr)
  511. {
  512. return esr_class_str[ESR_ELx_EC(esr)];
  513. }
  514. /*
  515. * bad_mode handles the impossible case in the exception vector. This is always
  516. * fatal.
  517. */
  518. asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
  519. {
  520. console_verbose();
  521. pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
  522. handler[reason], smp_processor_id(), esr,
  523. esr_get_class_string(esr));
  524. die("Oops - bad mode", regs, 0);
  525. local_irq_disable();
  526. panic("bad mode");
  527. }
  528. /*
  529. * bad_el0_sync handles unexpected, but potentially recoverable synchronous
  530. * exceptions taken from EL0. Unlike bad_mode, this returns.
  531. */
  532. asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
  533. {
  534. siginfo_t info;
  535. void __user *pc = (void __user *)instruction_pointer(regs);
  536. console_verbose();
  537. pr_crit("Bad EL0 synchronous exception detected on CPU%d, code 0x%08x -- %s\n",
  538. smp_processor_id(), esr, esr_get_class_string(esr));
  539. __show_regs(regs);
  540. info.si_signo = SIGILL;
  541. info.si_errno = 0;
  542. info.si_code = ILL_ILLOPC;
  543. info.si_addr = pc;
  544. current->thread.fault_address = 0;
  545. current->thread.fault_code = 0;
  546. force_sig_info(info.si_signo, &info, current);
  547. }
  548. void __pte_error(const char *file, int line, unsigned long val)
  549. {
  550. pr_err("%s:%d: bad pte %016lx.\n", file, line, val);
  551. }
  552. void __pmd_error(const char *file, int line, unsigned long val)
  553. {
  554. pr_err("%s:%d: bad pmd %016lx.\n", file, line, val);
  555. }
  556. void __pud_error(const char *file, int line, unsigned long val)
  557. {
  558. pr_err("%s:%d: bad pud %016lx.\n", file, line, val);
  559. }
  560. void __pgd_error(const char *file, int line, unsigned long val)
  561. {
  562. pr_err("%s:%d: bad pgd %016lx.\n", file, line, val);
  563. }
  564. /* GENERIC_BUG traps */
  565. int is_valid_bugaddr(unsigned long addr)
  566. {
  567. /*
  568. * bug_handler() only called for BRK #BUG_BRK_IMM.
  569. * So the answer is trivial -- any spurious instances with no
  570. * bug table entry will be rejected by report_bug() and passed
  571. * back to the debug-monitors code and handled as a fatal
  572. * unexpected debug exception.
  573. */
  574. return 1;
  575. }
  576. static int bug_handler(struct pt_regs *regs, unsigned int esr)
  577. {
  578. if (user_mode(regs))
  579. return DBG_HOOK_ERROR;
  580. switch (report_bug(regs->pc, regs)) {
  581. case BUG_TRAP_TYPE_BUG:
  582. die("Oops - BUG", regs, 0);
  583. break;
  584. case BUG_TRAP_TYPE_WARN:
  585. /* Ideally, report_bug() should backtrace for us... but no. */
  586. dump_backtrace(regs, NULL);
  587. break;
  588. default:
  589. /* unknown/unrecognised bug trap type */
  590. return DBG_HOOK_ERROR;
  591. }
  592. /* If thread survives, skip over the BUG instruction and continue: */
  593. regs->pc += AARCH64_INSN_SIZE; /* skip BRK and resume */
  594. return DBG_HOOK_HANDLED;
  595. }
  596. static struct break_hook bug_break_hook = {
  597. .esr_val = 0xf2000000 | BUG_BRK_IMM,
  598. .esr_mask = 0xffffffff,
  599. .fn = bug_handler,
  600. };
  601. /*
  602. * Initial handler for AArch64 BRK exceptions
  603. * This handler only used until debug_traps_init().
  604. */
  605. int __init early_brk64(unsigned long addr, unsigned int esr,
  606. struct pt_regs *regs)
  607. {
  608. return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
  609. }
  610. /* This registration must happen early, before debug_traps_init(). */
  611. void __init trap_init(void)
  612. {
  613. register_break_hook(&bug_break_hook);
  614. }