adc.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524
  1. /* arch/arm/plat-samsung/adc.c
  2. *
  3. * Copyright (c) 2008 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
  6. *
  7. * Samsung ADC device core
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/sched.h>
  17. #include <linux/list.h>
  18. #include <linux/slab.h>
  19. #include <linux/err.h>
  20. #include <linux/clk.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/io.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <plat/regs-adc.h>
  25. #include <plat/adc.h>
  26. /* This driver is designed to control the usage of the ADC block between
  27. * the touchscreen and any other drivers that may need to use it, such as
  28. * the hwmon driver.
  29. *
  30. * Priority will be given to the touchscreen driver, but as this itself is
  31. * rate limited it should not starve other requests which are processed in
  32. * order that they are received.
  33. *
  34. * Each user registers to get a client block which uniquely identifies it
  35. * and stores information such as the necessary functions to callback when
  36. * action is required.
  37. */
  38. enum s3c_cpu_type {
  39. TYPE_ADCV1, /* S3C24XX */
  40. TYPE_ADCV11, /* S3C2443 */
  41. TYPE_ADCV12, /* S3C2416, S3C2450 */
  42. TYPE_ADCV2, /* S3C64XX */
  43. TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
  44. };
  45. struct s3c_adc_client {
  46. struct platform_device *pdev;
  47. struct list_head pend;
  48. wait_queue_head_t *wait;
  49. unsigned int nr_samples;
  50. int result;
  51. unsigned char is_ts;
  52. unsigned char channel;
  53. void (*select_cb)(struct s3c_adc_client *c, unsigned selected);
  54. void (*convert_cb)(struct s3c_adc_client *c,
  55. unsigned val1, unsigned val2,
  56. unsigned *samples_left);
  57. };
  58. struct adc_device {
  59. struct platform_device *pdev;
  60. struct platform_device *owner;
  61. struct clk *clk;
  62. struct s3c_adc_client *cur;
  63. struct s3c_adc_client *ts_pend;
  64. void __iomem *regs;
  65. spinlock_t lock;
  66. unsigned int prescale;
  67. int irq;
  68. struct regulator *vdd;
  69. };
  70. static struct adc_device *adc_dev;
  71. static LIST_HEAD(adc_pending); /* protected by adc_device.lock */
  72. #define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg)
  73. static inline void s3c_adc_convert(struct adc_device *adc)
  74. {
  75. unsigned con = readl(adc->regs + S3C2410_ADCCON);
  76. con |= S3C2410_ADCCON_ENABLE_START;
  77. writel(con, adc->regs + S3C2410_ADCCON);
  78. }
  79. static inline void s3c_adc_select(struct adc_device *adc,
  80. struct s3c_adc_client *client)
  81. {
  82. unsigned con = readl(adc->regs + S3C2410_ADCCON);
  83. enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
  84. client->select_cb(client, 1);
  85. if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV2)
  86. con &= ~S3C2410_ADCCON_MUXMASK;
  87. con &= ~S3C2410_ADCCON_STDBM;
  88. con &= ~S3C2410_ADCCON_STARTMASK;
  89. if (!client->is_ts) {
  90. if (cpu == TYPE_ADCV3)
  91. writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
  92. else if (cpu == TYPE_ADCV11 || cpu == TYPE_ADCV12)
  93. writel(client->channel & 0xf,
  94. adc->regs + S3C2443_ADCMUX);
  95. else
  96. con |= S3C2410_ADCCON_SELMUX(client->channel);
  97. }
  98. writel(con, adc->regs + S3C2410_ADCCON);
  99. }
  100. static void s3c_adc_dbgshow(struct adc_device *adc)
  101. {
  102. adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n",
  103. readl(adc->regs + S3C2410_ADCCON),
  104. readl(adc->regs + S3C2410_ADCTSC),
  105. readl(adc->regs + S3C2410_ADCDLY));
  106. }
  107. static void s3c_adc_try(struct adc_device *adc)
  108. {
  109. struct s3c_adc_client *next = adc->ts_pend;
  110. if (!next && !list_empty(&adc_pending)) {
  111. next = list_first_entry(&adc_pending,
  112. struct s3c_adc_client, pend);
  113. list_del(&next->pend);
  114. } else
  115. adc->ts_pend = NULL;
  116. if (next) {
  117. adc_dbg(adc, "new client is %p\n", next);
  118. adc->cur = next;
  119. s3c_adc_select(adc, next);
  120. s3c_adc_convert(adc);
  121. s3c_adc_dbgshow(adc);
  122. }
  123. }
  124. int s3c_adc_start(struct s3c_adc_client *client,
  125. unsigned int channel, unsigned int nr_samples)
  126. {
  127. struct adc_device *adc = adc_dev;
  128. unsigned long flags;
  129. if (!adc) {
  130. printk(KERN_ERR "%s: failed to find adc\n", __func__);
  131. return -EINVAL;
  132. }
  133. spin_lock_irqsave(&adc->lock, flags);
  134. if (client->is_ts && adc->ts_pend) {
  135. spin_unlock_irqrestore(&adc->lock, flags);
  136. return -EAGAIN;
  137. }
  138. client->channel = channel;
  139. client->nr_samples = nr_samples;
  140. if (client->is_ts)
  141. adc->ts_pend = client;
  142. else
  143. list_add_tail(&client->pend, &adc_pending);
  144. if (!adc->cur)
  145. s3c_adc_try(adc);
  146. spin_unlock_irqrestore(&adc->lock, flags);
  147. return 0;
  148. }
  149. EXPORT_SYMBOL_GPL(s3c_adc_start);
  150. static void s3c_convert_done(struct s3c_adc_client *client,
  151. unsigned v, unsigned u, unsigned *left)
  152. {
  153. client->result = v;
  154. wake_up(client->wait);
  155. }
  156. int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
  157. {
  158. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake);
  159. int ret;
  160. client->convert_cb = s3c_convert_done;
  161. client->wait = &wake;
  162. client->result = -1;
  163. ret = s3c_adc_start(client, ch, 1);
  164. if (ret < 0)
  165. goto err;
  166. ret = wait_event_timeout(wake, client->result >= 0, HZ / 2);
  167. if (client->result < 0) {
  168. ret = -ETIMEDOUT;
  169. goto err;
  170. }
  171. client->convert_cb = NULL;
  172. return client->result;
  173. err:
  174. return ret;
  175. }
  176. EXPORT_SYMBOL_GPL(s3c_adc_read);
  177. static void s3c_adc_default_select(struct s3c_adc_client *client,
  178. unsigned select)
  179. {
  180. }
  181. struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
  182. void (*select)(struct s3c_adc_client *client,
  183. unsigned int selected),
  184. void (*conv)(struct s3c_adc_client *client,
  185. unsigned d0, unsigned d1,
  186. unsigned *samples_left),
  187. unsigned int is_ts)
  188. {
  189. struct s3c_adc_client *client;
  190. WARN_ON(!pdev);
  191. if (!select)
  192. select = s3c_adc_default_select;
  193. if (!pdev)
  194. return ERR_PTR(-EINVAL);
  195. client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL);
  196. if (!client) {
  197. dev_err(&pdev->dev, "no memory for adc client\n");
  198. return ERR_PTR(-ENOMEM);
  199. }
  200. client->pdev = pdev;
  201. client->is_ts = is_ts;
  202. client->select_cb = select;
  203. client->convert_cb = conv;
  204. return client;
  205. }
  206. EXPORT_SYMBOL_GPL(s3c_adc_register);
  207. void s3c_adc_release(struct s3c_adc_client *client)
  208. {
  209. unsigned long flags;
  210. spin_lock_irqsave(&adc_dev->lock, flags);
  211. /* We should really check that nothing is in progress. */
  212. if (adc_dev->cur == client)
  213. adc_dev->cur = NULL;
  214. if (adc_dev->ts_pend == client)
  215. adc_dev->ts_pend = NULL;
  216. else {
  217. struct list_head *p, *n;
  218. struct s3c_adc_client *tmp;
  219. list_for_each_safe(p, n, &adc_pending) {
  220. tmp = list_entry(p, struct s3c_adc_client, pend);
  221. if (tmp == client)
  222. list_del(&tmp->pend);
  223. }
  224. }
  225. if (adc_dev->cur == NULL)
  226. s3c_adc_try(adc_dev);
  227. spin_unlock_irqrestore(&adc_dev->lock, flags);
  228. kfree(client);
  229. }
  230. EXPORT_SYMBOL_GPL(s3c_adc_release);
  231. static irqreturn_t s3c_adc_irq(int irq, void *pw)
  232. {
  233. struct adc_device *adc = pw;
  234. struct s3c_adc_client *client = adc->cur;
  235. enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
  236. unsigned data0, data1;
  237. if (!client) {
  238. dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__);
  239. goto exit;
  240. }
  241. data0 = readl(adc->regs + S3C2410_ADCDAT0);
  242. data1 = readl(adc->regs + S3C2410_ADCDAT1);
  243. adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
  244. client->nr_samples--;
  245. if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV11) {
  246. data0 &= 0x3ff;
  247. data1 &= 0x3ff;
  248. } else {
  249. /* S3C2416/S3C64XX/S5P ADC resolution is 12-bit */
  250. data0 &= 0xfff;
  251. data1 &= 0xfff;
  252. }
  253. if (client->convert_cb)
  254. (client->convert_cb)(client, data0, data1, &client->nr_samples);
  255. if (client->nr_samples > 0) {
  256. /* fire another conversion for this */
  257. client->select_cb(client, 1);
  258. s3c_adc_convert(adc);
  259. } else {
  260. spin_lock(&adc->lock);
  261. (client->select_cb)(client, 0);
  262. adc->cur = NULL;
  263. s3c_adc_try(adc);
  264. spin_unlock(&adc->lock);
  265. }
  266. exit:
  267. if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) {
  268. /* Clear ADC interrupt */
  269. writel(0, adc->regs + S3C64XX_ADCCLRINT);
  270. }
  271. return IRQ_HANDLED;
  272. }
  273. static int s3c_adc_probe(struct platform_device *pdev)
  274. {
  275. struct device *dev = &pdev->dev;
  276. struct adc_device *adc;
  277. struct resource *regs;
  278. enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
  279. int ret;
  280. unsigned tmp;
  281. adc = devm_kzalloc(dev, sizeof(struct adc_device), GFP_KERNEL);
  282. if (adc == NULL) {
  283. dev_err(dev, "failed to allocate adc_device\n");
  284. return -ENOMEM;
  285. }
  286. spin_lock_init(&adc->lock);
  287. adc->pdev = pdev;
  288. adc->prescale = S3C2410_ADCCON_PRSCVL(49);
  289. adc->vdd = devm_regulator_get(dev, "vdd");
  290. if (IS_ERR(adc->vdd)) {
  291. dev_err(dev, "operating without regulator \"vdd\" .\n");
  292. return PTR_ERR(adc->vdd);
  293. }
  294. adc->irq = platform_get_irq(pdev, 1);
  295. if (adc->irq <= 0) {
  296. dev_err(dev, "failed to get adc irq\n");
  297. return -ENOENT;
  298. }
  299. ret = devm_request_irq(dev, adc->irq, s3c_adc_irq, 0, dev_name(dev),
  300. adc);
  301. if (ret < 0) {
  302. dev_err(dev, "failed to attach adc irq\n");
  303. return ret;
  304. }
  305. adc->clk = devm_clk_get(dev, "adc");
  306. if (IS_ERR(adc->clk)) {
  307. dev_err(dev, "failed to get adc clock\n");
  308. return PTR_ERR(adc->clk);
  309. }
  310. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  311. adc->regs = devm_ioremap_resource(dev, regs);
  312. if (IS_ERR(adc->regs))
  313. return PTR_ERR(adc->regs);
  314. ret = regulator_enable(adc->vdd);
  315. if (ret)
  316. return ret;
  317. clk_prepare_enable(adc->clk);
  318. tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
  319. /* Enable 12-bit ADC resolution */
  320. if (cpu == TYPE_ADCV12)
  321. tmp |= S3C2416_ADCCON_RESSEL;
  322. if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
  323. tmp |= S3C64XX_ADCCON_RESSEL;
  324. writel(tmp, adc->regs + S3C2410_ADCCON);
  325. dev_info(dev, "attached adc driver\n");
  326. platform_set_drvdata(pdev, adc);
  327. adc_dev = adc;
  328. return 0;
  329. }
  330. static int s3c_adc_remove(struct platform_device *pdev)
  331. {
  332. struct adc_device *adc = platform_get_drvdata(pdev);
  333. clk_disable_unprepare(adc->clk);
  334. regulator_disable(adc->vdd);
  335. return 0;
  336. }
  337. #ifdef CONFIG_PM
  338. static int s3c_adc_suspend(struct device *dev)
  339. {
  340. struct platform_device *pdev = to_platform_device(dev);
  341. struct adc_device *adc = platform_get_drvdata(pdev);
  342. unsigned long flags;
  343. u32 con;
  344. spin_lock_irqsave(&adc->lock, flags);
  345. con = readl(adc->regs + S3C2410_ADCCON);
  346. con |= S3C2410_ADCCON_STDBM;
  347. writel(con, adc->regs + S3C2410_ADCCON);
  348. disable_irq(adc->irq);
  349. spin_unlock_irqrestore(&adc->lock, flags);
  350. clk_disable(adc->clk);
  351. regulator_disable(adc->vdd);
  352. return 0;
  353. }
  354. static int s3c_adc_resume(struct device *dev)
  355. {
  356. struct platform_device *pdev = to_platform_device(dev);
  357. struct adc_device *adc = platform_get_drvdata(pdev);
  358. enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
  359. int ret;
  360. unsigned long tmp;
  361. ret = regulator_enable(adc->vdd);
  362. if (ret)
  363. return ret;
  364. clk_enable(adc->clk);
  365. enable_irq(adc->irq);
  366. tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
  367. /* Enable 12-bit ADC resolution */
  368. if (cpu == TYPE_ADCV12)
  369. tmp |= S3C2416_ADCCON_RESSEL;
  370. if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
  371. tmp |= S3C64XX_ADCCON_RESSEL;
  372. writel(tmp, adc->regs + S3C2410_ADCCON);
  373. return 0;
  374. }
  375. #else
  376. #define s3c_adc_suspend NULL
  377. #define s3c_adc_resume NULL
  378. #endif
  379. static const struct platform_device_id s3c_adc_driver_ids[] = {
  380. {
  381. .name = "s3c24xx-adc",
  382. .driver_data = TYPE_ADCV1,
  383. }, {
  384. .name = "s3c2443-adc",
  385. .driver_data = TYPE_ADCV11,
  386. }, {
  387. .name = "s3c2416-adc",
  388. .driver_data = TYPE_ADCV12,
  389. }, {
  390. .name = "s3c64xx-adc",
  391. .driver_data = TYPE_ADCV2,
  392. }, {
  393. .name = "samsung-adc-v3",
  394. .driver_data = TYPE_ADCV3,
  395. },
  396. { }
  397. };
  398. MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
  399. static const struct dev_pm_ops adc_pm_ops = {
  400. .suspend = s3c_adc_suspend,
  401. .resume = s3c_adc_resume,
  402. };
  403. static struct platform_driver s3c_adc_driver = {
  404. .id_table = s3c_adc_driver_ids,
  405. .driver = {
  406. .name = "s3c-adc",
  407. .pm = &adc_pm_ops,
  408. },
  409. .probe = s3c_adc_probe,
  410. .remove = s3c_adc_remove,
  411. };
  412. static int __init adc_init(void)
  413. {
  414. int ret;
  415. ret = platform_driver_register(&s3c_adc_driver);
  416. if (ret)
  417. printk(KERN_ERR "%s: failed to add adc driver\n", __func__);
  418. return ret;
  419. }
  420. module_init(adc_init);