avx2.c 8.6 KB

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  1. /* -*- linux-c -*- ------------------------------------------------------- *
  2. *
  3. * Copyright (C) 2012 Intel Corporation
  4. * Author: Yuanhan Liu <yuanhan.liu@linux.intel.com>
  5. *
  6. * Based on sse2.c: Copyright 2002 H. Peter Anvin - All Rights Reserved
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation, Inc., 53 Temple Place Ste 330,
  12. * Boston MA 02111-1307, USA; either version 2 of the License, or
  13. * (at your option) any later version; incorporated herein by reference.
  14. *
  15. * ----------------------------------------------------------------------- */
  16. /*
  17. * AVX2 implementation of RAID-6 syndrome functions
  18. *
  19. */
  20. #ifdef CONFIG_AS_AVX2
  21. #include <linux/raid/pq.h>
  22. #include "x86.h"
  23. static const struct raid6_avx2_constants {
  24. u64 x1d[4];
  25. } raid6_avx2_constants __aligned(32) = {
  26. { 0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,
  27. 0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,},
  28. };
  29. static int raid6_have_avx2(void)
  30. {
  31. return boot_cpu_has(X86_FEATURE_AVX2) && boot_cpu_has(X86_FEATURE_AVX);
  32. }
  33. /*
  34. * Plain AVX2 implementation
  35. */
  36. static void raid6_avx21_gen_syndrome(int disks, size_t bytes, void **ptrs)
  37. {
  38. u8 **dptr = (u8 **)ptrs;
  39. u8 *p, *q;
  40. int d, z, z0;
  41. z0 = disks - 3; /* Highest data disk */
  42. p = dptr[z0+1]; /* XOR parity */
  43. q = dptr[z0+2]; /* RS syndrome */
  44. kernel_fpu_begin();
  45. asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
  46. asm volatile("vpxor %ymm3,%ymm3,%ymm3"); /* Zero temp */
  47. for (d = 0; d < bytes; d += 32) {
  48. asm volatile("prefetchnta %0" : : "m" (dptr[z0][d]));
  49. asm volatile("vmovdqa %0,%%ymm2" : : "m" (dptr[z0][d]));/* P[0] */
  50. asm volatile("prefetchnta %0" : : "m" (dptr[z0-1][d]));
  51. asm volatile("vmovdqa %ymm2,%ymm4");/* Q[0] */
  52. asm volatile("vmovdqa %0,%%ymm6" : : "m" (dptr[z0-1][d]));
  53. for (z = z0-2; z >= 0; z--) {
  54. asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
  55. asm volatile("vpcmpgtb %ymm4,%ymm3,%ymm5");
  56. asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
  57. asm volatile("vpand %ymm0,%ymm5,%ymm5");
  58. asm volatile("vpxor %ymm5,%ymm4,%ymm4");
  59. asm volatile("vpxor %ymm6,%ymm2,%ymm2");
  60. asm volatile("vpxor %ymm6,%ymm4,%ymm4");
  61. asm volatile("vmovdqa %0,%%ymm6" : : "m" (dptr[z][d]));
  62. }
  63. asm volatile("vpcmpgtb %ymm4,%ymm3,%ymm5");
  64. asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
  65. asm volatile("vpand %ymm0,%ymm5,%ymm5");
  66. asm volatile("vpxor %ymm5,%ymm4,%ymm4");
  67. asm volatile("vpxor %ymm6,%ymm2,%ymm2");
  68. asm volatile("vpxor %ymm6,%ymm4,%ymm4");
  69. asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
  70. asm volatile("vpxor %ymm2,%ymm2,%ymm2");
  71. asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
  72. asm volatile("vpxor %ymm4,%ymm4,%ymm4");
  73. }
  74. asm volatile("sfence" : : : "memory");
  75. kernel_fpu_end();
  76. }
  77. const struct raid6_calls raid6_avx2x1 = {
  78. raid6_avx21_gen_syndrome,
  79. NULL, /* XOR not yet implemented */
  80. raid6_have_avx2,
  81. "avx2x1",
  82. 1 /* Has cache hints */
  83. };
  84. /*
  85. * Unrolled-by-2 AVX2 implementation
  86. */
  87. static void raid6_avx22_gen_syndrome(int disks, size_t bytes, void **ptrs)
  88. {
  89. u8 **dptr = (u8 **)ptrs;
  90. u8 *p, *q;
  91. int d, z, z0;
  92. z0 = disks - 3; /* Highest data disk */
  93. p = dptr[z0+1]; /* XOR parity */
  94. q = dptr[z0+2]; /* RS syndrome */
  95. kernel_fpu_begin();
  96. asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
  97. asm volatile("vpxor %ymm1,%ymm1,%ymm1"); /* Zero temp */
  98. /* We uniformly assume a single prefetch covers at least 32 bytes */
  99. for (d = 0; d < bytes; d += 64) {
  100. asm volatile("prefetchnta %0" : : "m" (dptr[z0][d]));
  101. asm volatile("prefetchnta %0" : : "m" (dptr[z0][d+32]));
  102. asm volatile("vmovdqa %0,%%ymm2" : : "m" (dptr[z0][d]));/* P[0] */
  103. asm volatile("vmovdqa %0,%%ymm3" : : "m" (dptr[z0][d+32]));/* P[1] */
  104. asm volatile("vmovdqa %ymm2,%ymm4"); /* Q[0] */
  105. asm volatile("vmovdqa %ymm3,%ymm6"); /* Q[1] */
  106. for (z = z0-1; z >= 0; z--) {
  107. asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
  108. asm volatile("prefetchnta %0" : : "m" (dptr[z][d+32]));
  109. asm volatile("vpcmpgtb %ymm4,%ymm1,%ymm5");
  110. asm volatile("vpcmpgtb %ymm6,%ymm1,%ymm7");
  111. asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
  112. asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
  113. asm volatile("vpand %ymm0,%ymm5,%ymm5");
  114. asm volatile("vpand %ymm0,%ymm7,%ymm7");
  115. asm volatile("vpxor %ymm5,%ymm4,%ymm4");
  116. asm volatile("vpxor %ymm7,%ymm6,%ymm6");
  117. asm volatile("vmovdqa %0,%%ymm5" : : "m" (dptr[z][d]));
  118. asm volatile("vmovdqa %0,%%ymm7" : : "m" (dptr[z][d+32]));
  119. asm volatile("vpxor %ymm5,%ymm2,%ymm2");
  120. asm volatile("vpxor %ymm7,%ymm3,%ymm3");
  121. asm volatile("vpxor %ymm5,%ymm4,%ymm4");
  122. asm volatile("vpxor %ymm7,%ymm6,%ymm6");
  123. }
  124. asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
  125. asm volatile("vmovntdq %%ymm3,%0" : "=m" (p[d+32]));
  126. asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
  127. asm volatile("vmovntdq %%ymm6,%0" : "=m" (q[d+32]));
  128. }
  129. asm volatile("sfence" : : : "memory");
  130. kernel_fpu_end();
  131. }
  132. const struct raid6_calls raid6_avx2x2 = {
  133. raid6_avx22_gen_syndrome,
  134. NULL, /* XOR not yet implemented */
  135. raid6_have_avx2,
  136. "avx2x2",
  137. 1 /* Has cache hints */
  138. };
  139. #ifdef CONFIG_X86_64
  140. /*
  141. * Unrolled-by-4 AVX2 implementation
  142. */
  143. static void raid6_avx24_gen_syndrome(int disks, size_t bytes, void **ptrs)
  144. {
  145. u8 **dptr = (u8 **)ptrs;
  146. u8 *p, *q;
  147. int d, z, z0;
  148. z0 = disks - 3; /* Highest data disk */
  149. p = dptr[z0+1]; /* XOR parity */
  150. q = dptr[z0+2]; /* RS syndrome */
  151. kernel_fpu_begin();
  152. asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
  153. asm volatile("vpxor %ymm1,%ymm1,%ymm1"); /* Zero temp */
  154. asm volatile("vpxor %ymm2,%ymm2,%ymm2"); /* P[0] */
  155. asm volatile("vpxor %ymm3,%ymm3,%ymm3"); /* P[1] */
  156. asm volatile("vpxor %ymm4,%ymm4,%ymm4"); /* Q[0] */
  157. asm volatile("vpxor %ymm6,%ymm6,%ymm6"); /* Q[1] */
  158. asm volatile("vpxor %ymm10,%ymm10,%ymm10"); /* P[2] */
  159. asm volatile("vpxor %ymm11,%ymm11,%ymm11"); /* P[3] */
  160. asm volatile("vpxor %ymm12,%ymm12,%ymm12"); /* Q[2] */
  161. asm volatile("vpxor %ymm14,%ymm14,%ymm14"); /* Q[3] */
  162. for (d = 0; d < bytes; d += 128) {
  163. for (z = z0; z >= 0; z--) {
  164. asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
  165. asm volatile("prefetchnta %0" : : "m" (dptr[z][d+32]));
  166. asm volatile("prefetchnta %0" : : "m" (dptr[z][d+64]));
  167. asm volatile("prefetchnta %0" : : "m" (dptr[z][d+96]));
  168. asm volatile("vpcmpgtb %ymm4,%ymm1,%ymm5");
  169. asm volatile("vpcmpgtb %ymm6,%ymm1,%ymm7");
  170. asm volatile("vpcmpgtb %ymm12,%ymm1,%ymm13");
  171. asm volatile("vpcmpgtb %ymm14,%ymm1,%ymm15");
  172. asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
  173. asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
  174. asm volatile("vpaddb %ymm12,%ymm12,%ymm12");
  175. asm volatile("vpaddb %ymm14,%ymm14,%ymm14");
  176. asm volatile("vpand %ymm0,%ymm5,%ymm5");
  177. asm volatile("vpand %ymm0,%ymm7,%ymm7");
  178. asm volatile("vpand %ymm0,%ymm13,%ymm13");
  179. asm volatile("vpand %ymm0,%ymm15,%ymm15");
  180. asm volatile("vpxor %ymm5,%ymm4,%ymm4");
  181. asm volatile("vpxor %ymm7,%ymm6,%ymm6");
  182. asm volatile("vpxor %ymm13,%ymm12,%ymm12");
  183. asm volatile("vpxor %ymm15,%ymm14,%ymm14");
  184. asm volatile("vmovdqa %0,%%ymm5" : : "m" (dptr[z][d]));
  185. asm volatile("vmovdqa %0,%%ymm7" : : "m" (dptr[z][d+32]));
  186. asm volatile("vmovdqa %0,%%ymm13" : : "m" (dptr[z][d+64]));
  187. asm volatile("vmovdqa %0,%%ymm15" : : "m" (dptr[z][d+96]));
  188. asm volatile("vpxor %ymm5,%ymm2,%ymm2");
  189. asm volatile("vpxor %ymm7,%ymm3,%ymm3");
  190. asm volatile("vpxor %ymm13,%ymm10,%ymm10");
  191. asm volatile("vpxor %ymm15,%ymm11,%ymm11");
  192. asm volatile("vpxor %ymm5,%ymm4,%ymm4");
  193. asm volatile("vpxor %ymm7,%ymm6,%ymm6");
  194. asm volatile("vpxor %ymm13,%ymm12,%ymm12");
  195. asm volatile("vpxor %ymm15,%ymm14,%ymm14");
  196. }
  197. asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
  198. asm volatile("vpxor %ymm2,%ymm2,%ymm2");
  199. asm volatile("vmovntdq %%ymm3,%0" : "=m" (p[d+32]));
  200. asm volatile("vpxor %ymm3,%ymm3,%ymm3");
  201. asm volatile("vmovntdq %%ymm10,%0" : "=m" (p[d+64]));
  202. asm volatile("vpxor %ymm10,%ymm10,%ymm10");
  203. asm volatile("vmovntdq %%ymm11,%0" : "=m" (p[d+96]));
  204. asm volatile("vpxor %ymm11,%ymm11,%ymm11");
  205. asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
  206. asm volatile("vpxor %ymm4,%ymm4,%ymm4");
  207. asm volatile("vmovntdq %%ymm6,%0" : "=m" (q[d+32]));
  208. asm volatile("vpxor %ymm6,%ymm6,%ymm6");
  209. asm volatile("vmovntdq %%ymm12,%0" : "=m" (q[d+64]));
  210. asm volatile("vpxor %ymm12,%ymm12,%ymm12");
  211. asm volatile("vmovntdq %%ymm14,%0" : "=m" (q[d+96]));
  212. asm volatile("vpxor %ymm14,%ymm14,%ymm14");
  213. }
  214. asm volatile("sfence" : : : "memory");
  215. kernel_fpu_end();
  216. }
  217. const struct raid6_calls raid6_avx2x4 = {
  218. raid6_avx24_gen_syndrome,
  219. NULL, /* XOR not yet implemented */
  220. raid6_have_avx2,
  221. "avx2x4",
  222. 1 /* Has cache hints */
  223. };
  224. #endif
  225. #endif /* CONFIG_AS_AVX2 */