init.c 4.9 KB

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  1. /*
  2. * Wireless Host Controller (WHC) initialization.
  3. *
  4. * Copyright (C) 2007 Cambridge Silicon Radio Ltd.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License version
  8. * 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/gfp.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/uwb/umc.h>
  22. #include "../../wusbcore/wusbhc.h"
  23. #include "whcd.h"
  24. /*
  25. * Reset the host controller.
  26. */
  27. static void whc_hw_reset(struct whc *whc)
  28. {
  29. le_writel(WUSBCMD_WHCRESET, whc->base + WUSBCMD);
  30. whci_wait_for(&whc->umc->dev, whc->base + WUSBCMD, WUSBCMD_WHCRESET, 0,
  31. 100, "reset");
  32. }
  33. static void whc_hw_init_di_buf(struct whc *whc)
  34. {
  35. int d;
  36. /* Disable all entries in the Device Information buffer. */
  37. for (d = 0; d < whc->n_devices; d++)
  38. whc->di_buf[d].addr_sec_info = WHC_DI_DISABLE;
  39. le_writeq(whc->di_buf_dma, whc->base + WUSBDEVICEINFOADDR);
  40. }
  41. static void whc_hw_init_dn_buf(struct whc *whc)
  42. {
  43. /* Clear the Device Notification buffer to ensure the V (valid)
  44. * bits are clear. */
  45. memset(whc->dn_buf, 0, 4096);
  46. le_writeq(whc->dn_buf_dma, whc->base + WUSBDNTSBUFADDR);
  47. }
  48. int whc_init(struct whc *whc)
  49. {
  50. u32 whcsparams;
  51. int ret, i;
  52. resource_size_t start, len;
  53. spin_lock_init(&whc->lock);
  54. mutex_init(&whc->mutex);
  55. init_waitqueue_head(&whc->cmd_wq);
  56. init_waitqueue_head(&whc->async_list_wq);
  57. init_waitqueue_head(&whc->periodic_list_wq);
  58. whc->workqueue = alloc_ordered_workqueue(dev_name(&whc->umc->dev), 0);
  59. if (whc->workqueue == NULL) {
  60. ret = -ENOMEM;
  61. goto error;
  62. }
  63. INIT_WORK(&whc->dn_work, whc_dn_work);
  64. INIT_WORK(&whc->async_work, scan_async_work);
  65. INIT_LIST_HEAD(&whc->async_list);
  66. INIT_LIST_HEAD(&whc->async_removed_list);
  67. INIT_WORK(&whc->periodic_work, scan_periodic_work);
  68. for (i = 0; i < 5; i++)
  69. INIT_LIST_HEAD(&whc->periodic_list[i]);
  70. INIT_LIST_HEAD(&whc->periodic_removed_list);
  71. /* Map HC registers. */
  72. start = whc->umc->resource.start;
  73. len = whc->umc->resource.end - start + 1;
  74. if (!request_mem_region(start, len, "whci-hc")) {
  75. dev_err(&whc->umc->dev, "can't request HC region\n");
  76. ret = -EBUSY;
  77. goto error;
  78. }
  79. whc->base_phys = start;
  80. whc->base = ioremap(start, len);
  81. if (!whc->base) {
  82. dev_err(&whc->umc->dev, "ioremap\n");
  83. ret = -ENOMEM;
  84. goto error;
  85. }
  86. whc_hw_reset(whc);
  87. /* Read maximum number of devices, keys and MMC IEs. */
  88. whcsparams = le_readl(whc->base + WHCSPARAMS);
  89. whc->n_devices = WHCSPARAMS_TO_N_DEVICES(whcsparams);
  90. whc->n_keys = WHCSPARAMS_TO_N_KEYS(whcsparams);
  91. whc->n_mmc_ies = WHCSPARAMS_TO_N_MMC_IES(whcsparams);
  92. dev_dbg(&whc->umc->dev, "N_DEVICES = %d, N_KEYS = %d, N_MMC_IES = %d\n",
  93. whc->n_devices, whc->n_keys, whc->n_mmc_ies);
  94. whc->qset_pool = dma_pool_create("qset", &whc->umc->dev,
  95. sizeof(struct whc_qset), 64, 0);
  96. if (whc->qset_pool == NULL) {
  97. ret = -ENOMEM;
  98. goto error;
  99. }
  100. ret = asl_init(whc);
  101. if (ret < 0)
  102. goto error;
  103. ret = pzl_init(whc);
  104. if (ret < 0)
  105. goto error;
  106. /* Allocate and initialize a buffer for generic commands, the
  107. Device Information buffer, and the Device Notification
  108. buffer. */
  109. whc->gen_cmd_buf = dma_alloc_coherent(&whc->umc->dev, WHC_GEN_CMD_DATA_LEN,
  110. &whc->gen_cmd_buf_dma, GFP_KERNEL);
  111. if (whc->gen_cmd_buf == NULL) {
  112. ret = -ENOMEM;
  113. goto error;
  114. }
  115. whc->dn_buf = dma_alloc_coherent(&whc->umc->dev,
  116. sizeof(struct dn_buf_entry) * WHC_N_DN_ENTRIES,
  117. &whc->dn_buf_dma, GFP_KERNEL);
  118. if (!whc->dn_buf) {
  119. ret = -ENOMEM;
  120. goto error;
  121. }
  122. whc_hw_init_dn_buf(whc);
  123. whc->di_buf = dma_alloc_coherent(&whc->umc->dev,
  124. sizeof(struct di_buf_entry) * whc->n_devices,
  125. &whc->di_buf_dma, GFP_KERNEL);
  126. if (!whc->di_buf) {
  127. ret = -ENOMEM;
  128. goto error;
  129. }
  130. whc_hw_init_di_buf(whc);
  131. return 0;
  132. error:
  133. whc_clean_up(whc);
  134. return ret;
  135. }
  136. void whc_clean_up(struct whc *whc)
  137. {
  138. resource_size_t len;
  139. if (whc->di_buf)
  140. dma_free_coherent(&whc->umc->dev, sizeof(struct di_buf_entry) * whc->n_devices,
  141. whc->di_buf, whc->di_buf_dma);
  142. if (whc->dn_buf)
  143. dma_free_coherent(&whc->umc->dev, sizeof(struct dn_buf_entry) * WHC_N_DN_ENTRIES,
  144. whc->dn_buf, whc->dn_buf_dma);
  145. if (whc->gen_cmd_buf)
  146. dma_free_coherent(&whc->umc->dev, WHC_GEN_CMD_DATA_LEN,
  147. whc->gen_cmd_buf, whc->gen_cmd_buf_dma);
  148. pzl_clean_up(whc);
  149. asl_clean_up(whc);
  150. dma_pool_destroy(whc->qset_pool);
  151. len = resource_size(&whc->umc->resource);
  152. if (whc->base)
  153. iounmap(whc->base);
  154. if (whc->base_phys)
  155. release_mem_region(whc->base_phys, len);
  156. if (whc->workqueue)
  157. destroy_workqueue(whc->workqueue);
  158. }