udc.c 48 KB

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  1. /*
  2. * udc.c - ChipIdea UDC driver
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/dmapool.h>
  15. #include <linux/err.h>
  16. #include <linux/irqreturn.h>
  17. #include <linux/kernel.h>
  18. #include <linux/slab.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/usb/ch9.h>
  21. #include <linux/usb/gadget.h>
  22. #include <linux/usb/otg-fsm.h>
  23. #include <linux/usb/chipidea.h>
  24. #include "ci.h"
  25. #include "udc.h"
  26. #include "bits.h"
  27. #include "otg.h"
  28. #include "otg_fsm.h"
  29. /* control endpoint description */
  30. static const struct usb_endpoint_descriptor
  31. ctrl_endpt_out_desc = {
  32. .bLength = USB_DT_ENDPOINT_SIZE,
  33. .bDescriptorType = USB_DT_ENDPOINT,
  34. .bEndpointAddress = USB_DIR_OUT,
  35. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  36. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  37. };
  38. static const struct usb_endpoint_descriptor
  39. ctrl_endpt_in_desc = {
  40. .bLength = USB_DT_ENDPOINT_SIZE,
  41. .bDescriptorType = USB_DT_ENDPOINT,
  42. .bEndpointAddress = USB_DIR_IN,
  43. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  44. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  45. };
  46. /**
  47. * hw_ep_bit: calculates the bit number
  48. * @num: endpoint number
  49. * @dir: endpoint direction
  50. *
  51. * This function returns bit number
  52. */
  53. static inline int hw_ep_bit(int num, int dir)
  54. {
  55. return num + ((dir == TX) ? 16 : 0);
  56. }
  57. static inline int ep_to_bit(struct ci_hdrc *ci, int n)
  58. {
  59. int fill = 16 - ci->hw_ep_max / 2;
  60. if (n >= ci->hw_ep_max / 2)
  61. n += fill;
  62. return n;
  63. }
  64. /**
  65. * hw_device_state: enables/disables interrupts (execute without interruption)
  66. * @dma: 0 => disable, !0 => enable and set dma engine
  67. *
  68. * This function returns an error code
  69. */
  70. static int hw_device_state(struct ci_hdrc *ci, u32 dma)
  71. {
  72. if (dma) {
  73. hw_write(ci, OP_ENDPTLISTADDR, ~0, dma);
  74. /* interrupt, error, port change, reset, sleep/suspend */
  75. hw_write(ci, OP_USBINTR, ~0,
  76. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  77. } else {
  78. hw_write(ci, OP_USBINTR, ~0, 0);
  79. }
  80. return 0;
  81. }
  82. /**
  83. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  84. * @num: endpoint number
  85. * @dir: endpoint direction
  86. *
  87. * This function returns an error code
  88. */
  89. static int hw_ep_flush(struct ci_hdrc *ci, int num, int dir)
  90. {
  91. int n = hw_ep_bit(num, dir);
  92. do {
  93. /* flush any pending transfer */
  94. hw_write(ci, OP_ENDPTFLUSH, ~0, BIT(n));
  95. while (hw_read(ci, OP_ENDPTFLUSH, BIT(n)))
  96. cpu_relax();
  97. } while (hw_read(ci, OP_ENDPTSTAT, BIT(n)));
  98. return 0;
  99. }
  100. /**
  101. * hw_ep_disable: disables endpoint (execute without interruption)
  102. * @num: endpoint number
  103. * @dir: endpoint direction
  104. *
  105. * This function returns an error code
  106. */
  107. static int hw_ep_disable(struct ci_hdrc *ci, int num, int dir)
  108. {
  109. hw_write(ci, OP_ENDPTCTRL + num,
  110. (dir == TX) ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  111. return 0;
  112. }
  113. /**
  114. * hw_ep_enable: enables endpoint (execute without interruption)
  115. * @num: endpoint number
  116. * @dir: endpoint direction
  117. * @type: endpoint type
  118. *
  119. * This function returns an error code
  120. */
  121. static int hw_ep_enable(struct ci_hdrc *ci, int num, int dir, int type)
  122. {
  123. u32 mask, data;
  124. if (dir == TX) {
  125. mask = ENDPTCTRL_TXT; /* type */
  126. data = type << __ffs(mask);
  127. mask |= ENDPTCTRL_TXS; /* unstall */
  128. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  129. data |= ENDPTCTRL_TXR;
  130. mask |= ENDPTCTRL_TXE; /* enable */
  131. data |= ENDPTCTRL_TXE;
  132. } else {
  133. mask = ENDPTCTRL_RXT; /* type */
  134. data = type << __ffs(mask);
  135. mask |= ENDPTCTRL_RXS; /* unstall */
  136. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  137. data |= ENDPTCTRL_RXR;
  138. mask |= ENDPTCTRL_RXE; /* enable */
  139. data |= ENDPTCTRL_RXE;
  140. }
  141. hw_write(ci, OP_ENDPTCTRL + num, mask, data);
  142. return 0;
  143. }
  144. /**
  145. * hw_ep_get_halt: return endpoint halt status
  146. * @num: endpoint number
  147. * @dir: endpoint direction
  148. *
  149. * This function returns 1 if endpoint halted
  150. */
  151. static int hw_ep_get_halt(struct ci_hdrc *ci, int num, int dir)
  152. {
  153. u32 mask = (dir == TX) ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  154. return hw_read(ci, OP_ENDPTCTRL + num, mask) ? 1 : 0;
  155. }
  156. /**
  157. * hw_ep_prime: primes endpoint (execute without interruption)
  158. * @num: endpoint number
  159. * @dir: endpoint direction
  160. * @is_ctrl: true if control endpoint
  161. *
  162. * This function returns an error code
  163. */
  164. static int hw_ep_prime(struct ci_hdrc *ci, int num, int dir, int is_ctrl)
  165. {
  166. int n = hw_ep_bit(num, dir);
  167. /* Synchronize before ep prime */
  168. wmb();
  169. if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
  170. return -EAGAIN;
  171. hw_write(ci, OP_ENDPTPRIME, ~0, BIT(n));
  172. while (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
  173. cpu_relax();
  174. if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
  175. return -EAGAIN;
  176. /* status shoult be tested according with manual but it doesn't work */
  177. return 0;
  178. }
  179. /**
  180. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  181. * without interruption)
  182. * @num: endpoint number
  183. * @dir: endpoint direction
  184. * @value: true => stall, false => unstall
  185. *
  186. * This function returns an error code
  187. */
  188. static int hw_ep_set_halt(struct ci_hdrc *ci, int num, int dir, int value)
  189. {
  190. if (value != 0 && value != 1)
  191. return -EINVAL;
  192. do {
  193. enum ci_hw_regs reg = OP_ENDPTCTRL + num;
  194. u32 mask_xs = (dir == TX) ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  195. u32 mask_xr = (dir == TX) ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  196. /* data toggle - reserved for EP0 but it's in ESS */
  197. hw_write(ci, reg, mask_xs|mask_xr,
  198. value ? mask_xs : mask_xr);
  199. } while (value != hw_ep_get_halt(ci, num, dir));
  200. return 0;
  201. }
  202. /**
  203. * hw_is_port_high_speed: test if port is high speed
  204. *
  205. * This function returns true if high speed port
  206. */
  207. static int hw_port_is_high_speed(struct ci_hdrc *ci)
  208. {
  209. return ci->hw_bank.lpm ? hw_read(ci, OP_DEVLC, DEVLC_PSPD) :
  210. hw_read(ci, OP_PORTSC, PORTSC_HSP);
  211. }
  212. /**
  213. * hw_test_and_clear_complete: test & clear complete status (execute without
  214. * interruption)
  215. * @n: endpoint number
  216. *
  217. * This function returns complete status
  218. */
  219. static int hw_test_and_clear_complete(struct ci_hdrc *ci, int n)
  220. {
  221. n = ep_to_bit(ci, n);
  222. return hw_test_and_clear(ci, OP_ENDPTCOMPLETE, BIT(n));
  223. }
  224. /**
  225. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  226. * without interruption)
  227. *
  228. * This function returns active interrutps
  229. */
  230. static u32 hw_test_and_clear_intr_active(struct ci_hdrc *ci)
  231. {
  232. u32 reg = hw_read_intr_status(ci) & hw_read_intr_enable(ci);
  233. hw_write(ci, OP_USBSTS, ~0, reg);
  234. return reg;
  235. }
  236. /**
  237. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  238. * interruption)
  239. *
  240. * This function returns guard value
  241. */
  242. static int hw_test_and_clear_setup_guard(struct ci_hdrc *ci)
  243. {
  244. return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, 0);
  245. }
  246. /**
  247. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  248. * interruption)
  249. *
  250. * This function returns guard value
  251. */
  252. static int hw_test_and_set_setup_guard(struct ci_hdrc *ci)
  253. {
  254. return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  255. }
  256. /**
  257. * hw_usb_set_address: configures USB address (execute without interruption)
  258. * @value: new USB address
  259. *
  260. * This function explicitly sets the address, without the "USBADRA" (advance)
  261. * feature, which is not supported by older versions of the controller.
  262. */
  263. static void hw_usb_set_address(struct ci_hdrc *ci, u8 value)
  264. {
  265. hw_write(ci, OP_DEVICEADDR, DEVICEADDR_USBADR,
  266. value << __ffs(DEVICEADDR_USBADR));
  267. }
  268. /**
  269. * hw_usb_reset: restart device after a bus reset (execute without
  270. * interruption)
  271. *
  272. * This function returns an error code
  273. */
  274. static int hw_usb_reset(struct ci_hdrc *ci)
  275. {
  276. hw_usb_set_address(ci, 0);
  277. /* ESS flushes only at end?!? */
  278. hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
  279. /* clear setup token semaphores */
  280. hw_write(ci, OP_ENDPTSETUPSTAT, 0, 0);
  281. /* clear complete status */
  282. hw_write(ci, OP_ENDPTCOMPLETE, 0, 0);
  283. /* wait until all bits cleared */
  284. while (hw_read(ci, OP_ENDPTPRIME, ~0))
  285. udelay(10); /* not RTOS friendly */
  286. /* reset all endpoints ? */
  287. /* reset internal status and wait for further instructions
  288. no need to verify the port reset status (ESS does it) */
  289. return 0;
  290. }
  291. /******************************************************************************
  292. * UTIL block
  293. *****************************************************************************/
  294. static int add_td_to_list(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq,
  295. unsigned length)
  296. {
  297. int i;
  298. u32 temp;
  299. struct td_node *lastnode, *node = kzalloc(sizeof(struct td_node),
  300. GFP_ATOMIC);
  301. if (node == NULL)
  302. return -ENOMEM;
  303. node->ptr = dma_pool_zalloc(hwep->td_pool, GFP_ATOMIC, &node->dma);
  304. if (node->ptr == NULL) {
  305. kfree(node);
  306. return -ENOMEM;
  307. }
  308. node->ptr->token = cpu_to_le32(length << __ffs(TD_TOTAL_BYTES));
  309. node->ptr->token &= cpu_to_le32(TD_TOTAL_BYTES);
  310. node->ptr->token |= cpu_to_le32(TD_STATUS_ACTIVE);
  311. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX) {
  312. u32 mul = hwreq->req.length / hwep->ep.maxpacket;
  313. if (hwreq->req.length == 0
  314. || hwreq->req.length % hwep->ep.maxpacket)
  315. mul++;
  316. node->ptr->token |= mul << __ffs(TD_MULTO);
  317. }
  318. temp = (u32) (hwreq->req.dma + hwreq->req.actual);
  319. if (length) {
  320. node->ptr->page[0] = cpu_to_le32(temp);
  321. for (i = 1; i < TD_PAGE_COUNT; i++) {
  322. u32 page = temp + i * CI_HDRC_PAGE_SIZE;
  323. page &= ~TD_RESERVED_MASK;
  324. node->ptr->page[i] = cpu_to_le32(page);
  325. }
  326. }
  327. hwreq->req.actual += length;
  328. if (!list_empty(&hwreq->tds)) {
  329. /* get the last entry */
  330. lastnode = list_entry(hwreq->tds.prev,
  331. struct td_node, td);
  332. lastnode->ptr->next = cpu_to_le32(node->dma);
  333. }
  334. INIT_LIST_HEAD(&node->td);
  335. list_add_tail(&node->td, &hwreq->tds);
  336. return 0;
  337. }
  338. /**
  339. * _usb_addr: calculates endpoint address from direction & number
  340. * @ep: endpoint
  341. */
  342. static inline u8 _usb_addr(struct ci_hw_ep *ep)
  343. {
  344. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  345. }
  346. /**
  347. * _hardware_enqueue: configures a request at hardware level
  348. * @hwep: endpoint
  349. * @hwreq: request
  350. *
  351. * This function returns an error code
  352. */
  353. static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
  354. {
  355. struct ci_hdrc *ci = hwep->ci;
  356. int ret = 0;
  357. unsigned rest = hwreq->req.length;
  358. int pages = TD_PAGE_COUNT;
  359. struct td_node *firstnode, *lastnode;
  360. /* don't queue twice */
  361. if (hwreq->req.status == -EALREADY)
  362. return -EALREADY;
  363. hwreq->req.status = -EALREADY;
  364. ret = usb_gadget_map_request(&ci->gadget, &hwreq->req, hwep->dir);
  365. if (ret)
  366. return ret;
  367. /*
  368. * The first buffer could be not page aligned.
  369. * In that case we have to span into one extra td.
  370. */
  371. if (hwreq->req.dma % PAGE_SIZE)
  372. pages--;
  373. if (rest == 0) {
  374. ret = add_td_to_list(hwep, hwreq, 0);
  375. if (ret < 0)
  376. goto done;
  377. }
  378. while (rest > 0) {
  379. unsigned count = min(hwreq->req.length - hwreq->req.actual,
  380. (unsigned)(pages * CI_HDRC_PAGE_SIZE));
  381. ret = add_td_to_list(hwep, hwreq, count);
  382. if (ret < 0)
  383. goto done;
  384. rest -= count;
  385. }
  386. if (hwreq->req.zero && hwreq->req.length && hwep->dir == TX
  387. && (hwreq->req.length % hwep->ep.maxpacket == 0)) {
  388. ret = add_td_to_list(hwep, hwreq, 0);
  389. if (ret < 0)
  390. goto done;
  391. }
  392. firstnode = list_first_entry(&hwreq->tds, struct td_node, td);
  393. lastnode = list_entry(hwreq->tds.prev,
  394. struct td_node, td);
  395. lastnode->ptr->next = cpu_to_le32(TD_TERMINATE);
  396. if (!hwreq->req.no_interrupt)
  397. lastnode->ptr->token |= cpu_to_le32(TD_IOC);
  398. wmb();
  399. hwreq->req.actual = 0;
  400. if (!list_empty(&hwep->qh.queue)) {
  401. struct ci_hw_req *hwreqprev;
  402. int n = hw_ep_bit(hwep->num, hwep->dir);
  403. int tmp_stat;
  404. struct td_node *prevlastnode;
  405. u32 next = firstnode->dma & TD_ADDR_MASK;
  406. hwreqprev = list_entry(hwep->qh.queue.prev,
  407. struct ci_hw_req, queue);
  408. prevlastnode = list_entry(hwreqprev->tds.prev,
  409. struct td_node, td);
  410. prevlastnode->ptr->next = cpu_to_le32(next);
  411. wmb();
  412. if (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
  413. goto done;
  414. do {
  415. hw_write(ci, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  416. tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n));
  417. } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW));
  418. hw_write(ci, OP_USBCMD, USBCMD_ATDTW, 0);
  419. if (tmp_stat)
  420. goto done;
  421. }
  422. /* QH configuration */
  423. hwep->qh.ptr->td.next = cpu_to_le32(firstnode->dma);
  424. hwep->qh.ptr->td.token &=
  425. cpu_to_le32(~(TD_STATUS_HALTED|TD_STATUS_ACTIVE));
  426. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == RX) {
  427. u32 mul = hwreq->req.length / hwep->ep.maxpacket;
  428. if (hwreq->req.length == 0
  429. || hwreq->req.length % hwep->ep.maxpacket)
  430. mul++;
  431. hwep->qh.ptr->cap |= mul << __ffs(QH_MULT);
  432. }
  433. ret = hw_ep_prime(ci, hwep->num, hwep->dir,
  434. hwep->type == USB_ENDPOINT_XFER_CONTROL);
  435. done:
  436. return ret;
  437. }
  438. /*
  439. * free_pending_td: remove a pending request for the endpoint
  440. * @hwep: endpoint
  441. */
  442. static void free_pending_td(struct ci_hw_ep *hwep)
  443. {
  444. struct td_node *pending = hwep->pending_td;
  445. dma_pool_free(hwep->td_pool, pending->ptr, pending->dma);
  446. hwep->pending_td = NULL;
  447. kfree(pending);
  448. }
  449. static int reprime_dtd(struct ci_hdrc *ci, struct ci_hw_ep *hwep,
  450. struct td_node *node)
  451. {
  452. hwep->qh.ptr->td.next = node->dma;
  453. hwep->qh.ptr->td.token &=
  454. cpu_to_le32(~(TD_STATUS_HALTED | TD_STATUS_ACTIVE));
  455. return hw_ep_prime(ci, hwep->num, hwep->dir,
  456. hwep->type == USB_ENDPOINT_XFER_CONTROL);
  457. }
  458. /**
  459. * _hardware_dequeue: handles a request at hardware level
  460. * @gadget: gadget
  461. * @hwep: endpoint
  462. *
  463. * This function returns an error code
  464. */
  465. static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
  466. {
  467. u32 tmptoken;
  468. struct td_node *node, *tmpnode;
  469. unsigned remaining_length;
  470. unsigned actual = hwreq->req.length;
  471. struct ci_hdrc *ci = hwep->ci;
  472. if (hwreq->req.status != -EALREADY)
  473. return -EINVAL;
  474. hwreq->req.status = 0;
  475. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  476. tmptoken = le32_to_cpu(node->ptr->token);
  477. if ((TD_STATUS_ACTIVE & tmptoken) != 0) {
  478. int n = hw_ep_bit(hwep->num, hwep->dir);
  479. if (ci->rev == CI_REVISION_24)
  480. if (!hw_read(ci, OP_ENDPTSTAT, BIT(n)))
  481. reprime_dtd(ci, hwep, node);
  482. hwreq->req.status = -EALREADY;
  483. return -EBUSY;
  484. }
  485. remaining_length = (tmptoken & TD_TOTAL_BYTES);
  486. remaining_length >>= __ffs(TD_TOTAL_BYTES);
  487. actual -= remaining_length;
  488. hwreq->req.status = tmptoken & TD_STATUS;
  489. if ((TD_STATUS_HALTED & hwreq->req.status)) {
  490. hwreq->req.status = -EPIPE;
  491. break;
  492. } else if ((TD_STATUS_DT_ERR & hwreq->req.status)) {
  493. hwreq->req.status = -EPROTO;
  494. break;
  495. } else if ((TD_STATUS_TR_ERR & hwreq->req.status)) {
  496. hwreq->req.status = -EILSEQ;
  497. break;
  498. }
  499. if (remaining_length) {
  500. if (hwep->dir == TX) {
  501. hwreq->req.status = -EPROTO;
  502. break;
  503. }
  504. }
  505. /*
  506. * As the hardware could still address the freed td
  507. * which will run the udc unusable, the cleanup of the
  508. * td has to be delayed by one.
  509. */
  510. if (hwep->pending_td)
  511. free_pending_td(hwep);
  512. hwep->pending_td = node;
  513. list_del_init(&node->td);
  514. }
  515. usb_gadget_unmap_request(&hwep->ci->gadget, &hwreq->req, hwep->dir);
  516. hwreq->req.actual += actual;
  517. if (hwreq->req.status)
  518. return hwreq->req.status;
  519. return hwreq->req.actual;
  520. }
  521. /**
  522. * _ep_nuke: dequeues all endpoint requests
  523. * @hwep: endpoint
  524. *
  525. * This function returns an error code
  526. * Caller must hold lock
  527. */
  528. static int _ep_nuke(struct ci_hw_ep *hwep)
  529. __releases(hwep->lock)
  530. __acquires(hwep->lock)
  531. {
  532. struct td_node *node, *tmpnode;
  533. if (hwep == NULL)
  534. return -EINVAL;
  535. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  536. while (!list_empty(&hwep->qh.queue)) {
  537. /* pop oldest request */
  538. struct ci_hw_req *hwreq = list_entry(hwep->qh.queue.next,
  539. struct ci_hw_req, queue);
  540. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  541. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  542. list_del_init(&node->td);
  543. node->ptr = NULL;
  544. kfree(node);
  545. }
  546. list_del_init(&hwreq->queue);
  547. hwreq->req.status = -ESHUTDOWN;
  548. if (hwreq->req.complete != NULL) {
  549. spin_unlock(hwep->lock);
  550. usb_gadget_giveback_request(&hwep->ep, &hwreq->req);
  551. spin_lock(hwep->lock);
  552. }
  553. }
  554. if (hwep->pending_td)
  555. free_pending_td(hwep);
  556. return 0;
  557. }
  558. static int _ep_set_halt(struct usb_ep *ep, int value, bool check_transfer)
  559. {
  560. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  561. int direction, retval = 0;
  562. unsigned long flags;
  563. if (ep == NULL || hwep->ep.desc == NULL)
  564. return -EINVAL;
  565. if (usb_endpoint_xfer_isoc(hwep->ep.desc))
  566. return -EOPNOTSUPP;
  567. spin_lock_irqsave(hwep->lock, flags);
  568. if (value && hwep->dir == TX && check_transfer &&
  569. !list_empty(&hwep->qh.queue) &&
  570. !usb_endpoint_xfer_control(hwep->ep.desc)) {
  571. spin_unlock_irqrestore(hwep->lock, flags);
  572. return -EAGAIN;
  573. }
  574. direction = hwep->dir;
  575. do {
  576. retval |= hw_ep_set_halt(hwep->ci, hwep->num, hwep->dir, value);
  577. if (!value)
  578. hwep->wedge = 0;
  579. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  580. hwep->dir = (hwep->dir == TX) ? RX : TX;
  581. } while (hwep->dir != direction);
  582. spin_unlock_irqrestore(hwep->lock, flags);
  583. return retval;
  584. }
  585. /**
  586. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  587. * @gadget: gadget
  588. *
  589. * This function returns an error code
  590. */
  591. static int _gadget_stop_activity(struct usb_gadget *gadget)
  592. {
  593. struct usb_ep *ep;
  594. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  595. unsigned long flags;
  596. spin_lock_irqsave(&ci->lock, flags);
  597. ci->gadget.speed = USB_SPEED_UNKNOWN;
  598. ci->remote_wakeup = 0;
  599. ci->suspended = 0;
  600. spin_unlock_irqrestore(&ci->lock, flags);
  601. /* flush all endpoints */
  602. gadget_for_each_ep(ep, gadget) {
  603. usb_ep_fifo_flush(ep);
  604. }
  605. usb_ep_fifo_flush(&ci->ep0out->ep);
  606. usb_ep_fifo_flush(&ci->ep0in->ep);
  607. /* make sure to disable all endpoints */
  608. gadget_for_each_ep(ep, gadget) {
  609. usb_ep_disable(ep);
  610. }
  611. if (ci->status != NULL) {
  612. usb_ep_free_request(&ci->ep0in->ep, ci->status);
  613. ci->status = NULL;
  614. }
  615. return 0;
  616. }
  617. /******************************************************************************
  618. * ISR block
  619. *****************************************************************************/
  620. /**
  621. * isr_reset_handler: USB reset interrupt handler
  622. * @ci: UDC device
  623. *
  624. * This function resets USB engine after a bus reset occurred
  625. */
  626. static void isr_reset_handler(struct ci_hdrc *ci)
  627. __releases(ci->lock)
  628. __acquires(ci->lock)
  629. {
  630. int retval;
  631. spin_unlock(&ci->lock);
  632. if (ci->gadget.speed != USB_SPEED_UNKNOWN)
  633. usb_gadget_udc_reset(&ci->gadget, ci->driver);
  634. retval = _gadget_stop_activity(&ci->gadget);
  635. if (retval)
  636. goto done;
  637. retval = hw_usb_reset(ci);
  638. if (retval)
  639. goto done;
  640. ci->status = usb_ep_alloc_request(&ci->ep0in->ep, GFP_ATOMIC);
  641. if (ci->status == NULL)
  642. retval = -ENOMEM;
  643. done:
  644. spin_lock(&ci->lock);
  645. if (retval)
  646. dev_err(ci->dev, "error: %i\n", retval);
  647. }
  648. /**
  649. * isr_get_status_complete: get_status request complete function
  650. * @ep: endpoint
  651. * @req: request handled
  652. *
  653. * Caller must release lock
  654. */
  655. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  656. {
  657. if (ep == NULL || req == NULL)
  658. return;
  659. kfree(req->buf);
  660. usb_ep_free_request(ep, req);
  661. }
  662. /**
  663. * _ep_queue: queues (submits) an I/O request to an endpoint
  664. * @ep: endpoint
  665. * @req: request
  666. * @gfp_flags: GFP flags (not used)
  667. *
  668. * Caller must hold lock
  669. * This function returns an error code
  670. */
  671. static int _ep_queue(struct usb_ep *ep, struct usb_request *req,
  672. gfp_t __maybe_unused gfp_flags)
  673. {
  674. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  675. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  676. struct ci_hdrc *ci = hwep->ci;
  677. int retval = 0;
  678. if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
  679. return -EINVAL;
  680. if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  681. if (req->length)
  682. hwep = (ci->ep0_dir == RX) ?
  683. ci->ep0out : ci->ep0in;
  684. if (!list_empty(&hwep->qh.queue)) {
  685. _ep_nuke(hwep);
  686. dev_warn(hwep->ci->dev, "endpoint ctrl %X nuked\n",
  687. _usb_addr(hwep));
  688. }
  689. }
  690. if (usb_endpoint_xfer_isoc(hwep->ep.desc) &&
  691. hwreq->req.length > (1 + hwep->ep.mult) * hwep->ep.maxpacket) {
  692. dev_err(hwep->ci->dev, "request length too big for isochronous\n");
  693. return -EMSGSIZE;
  694. }
  695. /* first nuke then test link, e.g. previous status has not sent */
  696. if (!list_empty(&hwreq->queue)) {
  697. dev_err(hwep->ci->dev, "request already in queue\n");
  698. return -EBUSY;
  699. }
  700. /* push request */
  701. hwreq->req.status = -EINPROGRESS;
  702. hwreq->req.actual = 0;
  703. retval = _hardware_enqueue(hwep, hwreq);
  704. if (retval == -EALREADY)
  705. retval = 0;
  706. if (!retval)
  707. list_add_tail(&hwreq->queue, &hwep->qh.queue);
  708. return retval;
  709. }
  710. /**
  711. * isr_get_status_response: get_status request response
  712. * @ci: ci struct
  713. * @setup: setup request packet
  714. *
  715. * This function returns an error code
  716. */
  717. static int isr_get_status_response(struct ci_hdrc *ci,
  718. struct usb_ctrlrequest *setup)
  719. __releases(hwep->lock)
  720. __acquires(hwep->lock)
  721. {
  722. struct ci_hw_ep *hwep = ci->ep0in;
  723. struct usb_request *req = NULL;
  724. gfp_t gfp_flags = GFP_ATOMIC;
  725. int dir, num, retval;
  726. if (hwep == NULL || setup == NULL)
  727. return -EINVAL;
  728. spin_unlock(hwep->lock);
  729. req = usb_ep_alloc_request(&hwep->ep, gfp_flags);
  730. spin_lock(hwep->lock);
  731. if (req == NULL)
  732. return -ENOMEM;
  733. req->complete = isr_get_status_complete;
  734. req->length = 2;
  735. req->buf = kzalloc(req->length, gfp_flags);
  736. if (req->buf == NULL) {
  737. retval = -ENOMEM;
  738. goto err_free_req;
  739. }
  740. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  741. *(u16 *)req->buf = (ci->remote_wakeup << 1) |
  742. ci->gadget.is_selfpowered;
  743. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  744. == USB_RECIP_ENDPOINT) {
  745. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  746. TX : RX;
  747. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  748. *(u16 *)req->buf = hw_ep_get_halt(ci, num, dir);
  749. }
  750. /* else do nothing; reserved for future use */
  751. retval = _ep_queue(&hwep->ep, req, gfp_flags);
  752. if (retval)
  753. goto err_free_buf;
  754. return 0;
  755. err_free_buf:
  756. kfree(req->buf);
  757. err_free_req:
  758. spin_unlock(hwep->lock);
  759. usb_ep_free_request(&hwep->ep, req);
  760. spin_lock(hwep->lock);
  761. return retval;
  762. }
  763. /**
  764. * isr_setup_status_complete: setup_status request complete function
  765. * @ep: endpoint
  766. * @req: request handled
  767. *
  768. * Caller must release lock. Put the port in test mode if test mode
  769. * feature is selected.
  770. */
  771. static void
  772. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  773. {
  774. struct ci_hdrc *ci = req->context;
  775. unsigned long flags;
  776. if (ci->setaddr) {
  777. hw_usb_set_address(ci, ci->address);
  778. ci->setaddr = false;
  779. if (ci->address)
  780. usb_gadget_set_state(&ci->gadget, USB_STATE_ADDRESS);
  781. }
  782. spin_lock_irqsave(&ci->lock, flags);
  783. if (ci->test_mode)
  784. hw_port_test_set(ci, ci->test_mode);
  785. spin_unlock_irqrestore(&ci->lock, flags);
  786. }
  787. /**
  788. * isr_setup_status_phase: queues the status phase of a setup transation
  789. * @ci: ci struct
  790. *
  791. * This function returns an error code
  792. */
  793. static int isr_setup_status_phase(struct ci_hdrc *ci)
  794. {
  795. int retval;
  796. struct ci_hw_ep *hwep;
  797. /*
  798. * Unexpected USB controller behavior, caused by bad signal integrity
  799. * or ground reference problems, can lead to isr_setup_status_phase
  800. * being called with ci->status equal to NULL.
  801. * If this situation occurs, you should review your USB hardware design.
  802. */
  803. if (WARN_ON_ONCE(!ci->status))
  804. return -EPIPE;
  805. hwep = (ci->ep0_dir == TX) ? ci->ep0out : ci->ep0in;
  806. ci->status->context = ci;
  807. ci->status->complete = isr_setup_status_complete;
  808. retval = _ep_queue(&hwep->ep, ci->status, GFP_ATOMIC);
  809. return retval;
  810. }
  811. /**
  812. * isr_tr_complete_low: transaction complete low level handler
  813. * @hwep: endpoint
  814. *
  815. * This function returns an error code
  816. * Caller must hold lock
  817. */
  818. static int isr_tr_complete_low(struct ci_hw_ep *hwep)
  819. __releases(hwep->lock)
  820. __acquires(hwep->lock)
  821. {
  822. struct ci_hw_req *hwreq, *hwreqtemp;
  823. struct ci_hw_ep *hweptemp = hwep;
  824. int retval = 0;
  825. list_for_each_entry_safe(hwreq, hwreqtemp, &hwep->qh.queue,
  826. queue) {
  827. retval = _hardware_dequeue(hwep, hwreq);
  828. if (retval < 0)
  829. break;
  830. list_del_init(&hwreq->queue);
  831. if (hwreq->req.complete != NULL) {
  832. spin_unlock(hwep->lock);
  833. if ((hwep->type == USB_ENDPOINT_XFER_CONTROL) &&
  834. hwreq->req.length)
  835. hweptemp = hwep->ci->ep0in;
  836. usb_gadget_giveback_request(&hweptemp->ep, &hwreq->req);
  837. spin_lock(hwep->lock);
  838. }
  839. }
  840. if (retval == -EBUSY)
  841. retval = 0;
  842. return retval;
  843. }
  844. static int otg_a_alt_hnp_support(struct ci_hdrc *ci)
  845. {
  846. dev_warn(&ci->gadget.dev,
  847. "connect the device to an alternate port if you want HNP\n");
  848. return isr_setup_status_phase(ci);
  849. }
  850. /**
  851. * isr_setup_packet_handler: setup packet handler
  852. * @ci: UDC descriptor
  853. *
  854. * This function handles setup packet
  855. */
  856. static void isr_setup_packet_handler(struct ci_hdrc *ci)
  857. __releases(ci->lock)
  858. __acquires(ci->lock)
  859. {
  860. struct ci_hw_ep *hwep = &ci->ci_hw_ep[0];
  861. struct usb_ctrlrequest req;
  862. int type, num, dir, err = -EINVAL;
  863. u8 tmode = 0;
  864. /*
  865. * Flush data and handshake transactions of previous
  866. * setup packet.
  867. */
  868. _ep_nuke(ci->ep0out);
  869. _ep_nuke(ci->ep0in);
  870. /* read_setup_packet */
  871. do {
  872. hw_test_and_set_setup_guard(ci);
  873. memcpy(&req, &hwep->qh.ptr->setup, sizeof(req));
  874. } while (!hw_test_and_clear_setup_guard(ci));
  875. type = req.bRequestType;
  876. ci->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  877. switch (req.bRequest) {
  878. case USB_REQ_CLEAR_FEATURE:
  879. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  880. le16_to_cpu(req.wValue) ==
  881. USB_ENDPOINT_HALT) {
  882. if (req.wLength != 0)
  883. break;
  884. num = le16_to_cpu(req.wIndex);
  885. dir = (num & USB_ENDPOINT_DIR_MASK) ? TX : RX;
  886. num &= USB_ENDPOINT_NUMBER_MASK;
  887. if (dir == TX)
  888. num += ci->hw_ep_max / 2;
  889. if (!ci->ci_hw_ep[num].wedge) {
  890. spin_unlock(&ci->lock);
  891. err = usb_ep_clear_halt(
  892. &ci->ci_hw_ep[num].ep);
  893. spin_lock(&ci->lock);
  894. if (err)
  895. break;
  896. }
  897. err = isr_setup_status_phase(ci);
  898. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  899. le16_to_cpu(req.wValue) ==
  900. USB_DEVICE_REMOTE_WAKEUP) {
  901. if (req.wLength != 0)
  902. break;
  903. ci->remote_wakeup = 0;
  904. err = isr_setup_status_phase(ci);
  905. } else {
  906. goto delegate;
  907. }
  908. break;
  909. case USB_REQ_GET_STATUS:
  910. if ((type != (USB_DIR_IN|USB_RECIP_DEVICE) ||
  911. le16_to_cpu(req.wIndex) == OTG_STS_SELECTOR) &&
  912. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  913. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  914. goto delegate;
  915. if (le16_to_cpu(req.wLength) != 2 ||
  916. le16_to_cpu(req.wValue) != 0)
  917. break;
  918. err = isr_get_status_response(ci, &req);
  919. break;
  920. case USB_REQ_SET_ADDRESS:
  921. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  922. goto delegate;
  923. if (le16_to_cpu(req.wLength) != 0 ||
  924. le16_to_cpu(req.wIndex) != 0)
  925. break;
  926. ci->address = (u8)le16_to_cpu(req.wValue);
  927. ci->setaddr = true;
  928. err = isr_setup_status_phase(ci);
  929. break;
  930. case USB_REQ_SET_FEATURE:
  931. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  932. le16_to_cpu(req.wValue) ==
  933. USB_ENDPOINT_HALT) {
  934. if (req.wLength != 0)
  935. break;
  936. num = le16_to_cpu(req.wIndex);
  937. dir = (num & USB_ENDPOINT_DIR_MASK) ? TX : RX;
  938. num &= USB_ENDPOINT_NUMBER_MASK;
  939. if (dir == TX)
  940. num += ci->hw_ep_max / 2;
  941. spin_unlock(&ci->lock);
  942. err = _ep_set_halt(&ci->ci_hw_ep[num].ep, 1, false);
  943. spin_lock(&ci->lock);
  944. if (!err)
  945. isr_setup_status_phase(ci);
  946. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  947. if (req.wLength != 0)
  948. break;
  949. switch (le16_to_cpu(req.wValue)) {
  950. case USB_DEVICE_REMOTE_WAKEUP:
  951. ci->remote_wakeup = 1;
  952. err = isr_setup_status_phase(ci);
  953. break;
  954. case USB_DEVICE_TEST_MODE:
  955. tmode = le16_to_cpu(req.wIndex) >> 8;
  956. switch (tmode) {
  957. case TEST_J:
  958. case TEST_K:
  959. case TEST_SE0_NAK:
  960. case TEST_PACKET:
  961. case TEST_FORCE_EN:
  962. ci->test_mode = tmode;
  963. err = isr_setup_status_phase(
  964. ci);
  965. break;
  966. default:
  967. break;
  968. }
  969. break;
  970. case USB_DEVICE_B_HNP_ENABLE:
  971. if (ci_otg_is_fsm_mode(ci)) {
  972. ci->gadget.b_hnp_enable = 1;
  973. err = isr_setup_status_phase(
  974. ci);
  975. }
  976. break;
  977. case USB_DEVICE_A_ALT_HNP_SUPPORT:
  978. if (ci_otg_is_fsm_mode(ci))
  979. err = otg_a_alt_hnp_support(ci);
  980. break;
  981. case USB_DEVICE_A_HNP_SUPPORT:
  982. if (ci_otg_is_fsm_mode(ci)) {
  983. ci->gadget.a_hnp_support = 1;
  984. err = isr_setup_status_phase(
  985. ci);
  986. }
  987. break;
  988. default:
  989. goto delegate;
  990. }
  991. } else {
  992. goto delegate;
  993. }
  994. break;
  995. default:
  996. delegate:
  997. if (req.wLength == 0) /* no data phase */
  998. ci->ep0_dir = TX;
  999. spin_unlock(&ci->lock);
  1000. err = ci->driver->setup(&ci->gadget, &req);
  1001. spin_lock(&ci->lock);
  1002. break;
  1003. }
  1004. if (err < 0) {
  1005. spin_unlock(&ci->lock);
  1006. if (_ep_set_halt(&hwep->ep, 1, false))
  1007. dev_err(ci->dev, "error: _ep_set_halt\n");
  1008. spin_lock(&ci->lock);
  1009. }
  1010. }
  1011. /**
  1012. * isr_tr_complete_handler: transaction complete interrupt handler
  1013. * @ci: UDC descriptor
  1014. *
  1015. * This function handles traffic events
  1016. */
  1017. static void isr_tr_complete_handler(struct ci_hdrc *ci)
  1018. __releases(ci->lock)
  1019. __acquires(ci->lock)
  1020. {
  1021. unsigned i;
  1022. int err;
  1023. for (i = 0; i < ci->hw_ep_max; i++) {
  1024. struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
  1025. if (hwep->ep.desc == NULL)
  1026. continue; /* not configured */
  1027. if (hw_test_and_clear_complete(ci, i)) {
  1028. err = isr_tr_complete_low(hwep);
  1029. if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  1030. if (err > 0) /* needs status phase */
  1031. err = isr_setup_status_phase(ci);
  1032. if (err < 0) {
  1033. spin_unlock(&ci->lock);
  1034. if (_ep_set_halt(&hwep->ep, 1, false))
  1035. dev_err(ci->dev,
  1036. "error: _ep_set_halt\n");
  1037. spin_lock(&ci->lock);
  1038. }
  1039. }
  1040. }
  1041. /* Only handle setup packet below */
  1042. if (i == 0 &&
  1043. hw_test_and_clear(ci, OP_ENDPTSETUPSTAT, BIT(0)))
  1044. isr_setup_packet_handler(ci);
  1045. }
  1046. }
  1047. /******************************************************************************
  1048. * ENDPT block
  1049. *****************************************************************************/
  1050. /**
  1051. * ep_enable: configure endpoint, making it usable
  1052. *
  1053. * Check usb_ep_enable() at "usb_gadget.h" for details
  1054. */
  1055. static int ep_enable(struct usb_ep *ep,
  1056. const struct usb_endpoint_descriptor *desc)
  1057. {
  1058. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1059. int retval = 0;
  1060. unsigned long flags;
  1061. u32 cap = 0;
  1062. if (ep == NULL || desc == NULL)
  1063. return -EINVAL;
  1064. spin_lock_irqsave(hwep->lock, flags);
  1065. /* only internal SW should enable ctrl endpts */
  1066. if (!list_empty(&hwep->qh.queue)) {
  1067. dev_warn(hwep->ci->dev, "enabling a non-empty endpoint!\n");
  1068. spin_unlock_irqrestore(hwep->lock, flags);
  1069. return -EBUSY;
  1070. }
  1071. hwep->ep.desc = desc;
  1072. hwep->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1073. hwep->num = usb_endpoint_num(desc);
  1074. hwep->type = usb_endpoint_type(desc);
  1075. hwep->ep.maxpacket = usb_endpoint_maxp(desc) & 0x07ff;
  1076. hwep->ep.mult = QH_ISO_MULT(usb_endpoint_maxp(desc));
  1077. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1078. cap |= QH_IOS;
  1079. cap |= QH_ZLT;
  1080. cap |= (hwep->ep.maxpacket << __ffs(QH_MAX_PKT)) & QH_MAX_PKT;
  1081. /*
  1082. * For ISO-TX, we set mult at QH as the largest value, and use
  1083. * MultO at TD as real mult value.
  1084. */
  1085. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX)
  1086. cap |= 3 << __ffs(QH_MULT);
  1087. hwep->qh.ptr->cap = cpu_to_le32(cap);
  1088. hwep->qh.ptr->td.next |= cpu_to_le32(TD_TERMINATE); /* needed? */
  1089. if (hwep->num != 0 && hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  1090. dev_err(hwep->ci->dev, "Set control xfer at non-ep0\n");
  1091. retval = -EINVAL;
  1092. }
  1093. /*
  1094. * Enable endpoints in the HW other than ep0 as ep0
  1095. * is always enabled
  1096. */
  1097. if (hwep->num)
  1098. retval |= hw_ep_enable(hwep->ci, hwep->num, hwep->dir,
  1099. hwep->type);
  1100. spin_unlock_irqrestore(hwep->lock, flags);
  1101. return retval;
  1102. }
  1103. /**
  1104. * ep_disable: endpoint is no longer usable
  1105. *
  1106. * Check usb_ep_disable() at "usb_gadget.h" for details
  1107. */
  1108. static int ep_disable(struct usb_ep *ep)
  1109. {
  1110. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1111. int direction, retval = 0;
  1112. unsigned long flags;
  1113. if (ep == NULL)
  1114. return -EINVAL;
  1115. else if (hwep->ep.desc == NULL)
  1116. return -EBUSY;
  1117. spin_lock_irqsave(hwep->lock, flags);
  1118. /* only internal SW should disable ctrl endpts */
  1119. direction = hwep->dir;
  1120. do {
  1121. retval |= _ep_nuke(hwep);
  1122. retval |= hw_ep_disable(hwep->ci, hwep->num, hwep->dir);
  1123. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1124. hwep->dir = (hwep->dir == TX) ? RX : TX;
  1125. } while (hwep->dir != direction);
  1126. hwep->ep.desc = NULL;
  1127. spin_unlock_irqrestore(hwep->lock, flags);
  1128. return retval;
  1129. }
  1130. /**
  1131. * ep_alloc_request: allocate a request object to use with this endpoint
  1132. *
  1133. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1134. */
  1135. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1136. {
  1137. struct ci_hw_req *hwreq = NULL;
  1138. if (ep == NULL)
  1139. return NULL;
  1140. hwreq = kzalloc(sizeof(struct ci_hw_req), gfp_flags);
  1141. if (hwreq != NULL) {
  1142. INIT_LIST_HEAD(&hwreq->queue);
  1143. INIT_LIST_HEAD(&hwreq->tds);
  1144. }
  1145. return (hwreq == NULL) ? NULL : &hwreq->req;
  1146. }
  1147. /**
  1148. * ep_free_request: frees a request object
  1149. *
  1150. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1151. */
  1152. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1153. {
  1154. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1155. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  1156. struct td_node *node, *tmpnode;
  1157. unsigned long flags;
  1158. if (ep == NULL || req == NULL) {
  1159. return;
  1160. } else if (!list_empty(&hwreq->queue)) {
  1161. dev_err(hwep->ci->dev, "freeing queued request\n");
  1162. return;
  1163. }
  1164. spin_lock_irqsave(hwep->lock, flags);
  1165. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  1166. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  1167. list_del_init(&node->td);
  1168. node->ptr = NULL;
  1169. kfree(node);
  1170. }
  1171. kfree(hwreq);
  1172. spin_unlock_irqrestore(hwep->lock, flags);
  1173. }
  1174. /**
  1175. * ep_queue: queues (submits) an I/O request to an endpoint
  1176. *
  1177. * Check usb_ep_queue()* at usb_gadget.h" for details
  1178. */
  1179. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1180. gfp_t __maybe_unused gfp_flags)
  1181. {
  1182. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1183. int retval = 0;
  1184. unsigned long flags;
  1185. if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
  1186. return -EINVAL;
  1187. spin_lock_irqsave(hwep->lock, flags);
  1188. retval = _ep_queue(ep, req, gfp_flags);
  1189. spin_unlock_irqrestore(hwep->lock, flags);
  1190. return retval;
  1191. }
  1192. /**
  1193. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1194. *
  1195. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1196. */
  1197. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1198. {
  1199. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1200. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  1201. unsigned long flags;
  1202. struct td_node *node, *tmpnode;
  1203. if (ep == NULL || req == NULL || hwreq->req.status != -EALREADY ||
  1204. hwep->ep.desc == NULL || list_empty(&hwreq->queue) ||
  1205. list_empty(&hwep->qh.queue))
  1206. return -EINVAL;
  1207. spin_lock_irqsave(hwep->lock, flags);
  1208. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  1209. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  1210. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  1211. list_del(&node->td);
  1212. kfree(node);
  1213. }
  1214. /* pop request */
  1215. list_del_init(&hwreq->queue);
  1216. usb_gadget_unmap_request(&hwep->ci->gadget, req, hwep->dir);
  1217. req->status = -ECONNRESET;
  1218. if (hwreq->req.complete != NULL) {
  1219. spin_unlock(hwep->lock);
  1220. usb_gadget_giveback_request(&hwep->ep, &hwreq->req);
  1221. spin_lock(hwep->lock);
  1222. }
  1223. spin_unlock_irqrestore(hwep->lock, flags);
  1224. return 0;
  1225. }
  1226. /**
  1227. * ep_set_halt: sets the endpoint halt feature
  1228. *
  1229. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  1230. */
  1231. static int ep_set_halt(struct usb_ep *ep, int value)
  1232. {
  1233. return _ep_set_halt(ep, value, true);
  1234. }
  1235. /**
  1236. * ep_set_wedge: sets the halt feature and ignores clear requests
  1237. *
  1238. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  1239. */
  1240. static int ep_set_wedge(struct usb_ep *ep)
  1241. {
  1242. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1243. unsigned long flags;
  1244. if (ep == NULL || hwep->ep.desc == NULL)
  1245. return -EINVAL;
  1246. spin_lock_irqsave(hwep->lock, flags);
  1247. hwep->wedge = 1;
  1248. spin_unlock_irqrestore(hwep->lock, flags);
  1249. return usb_ep_set_halt(ep);
  1250. }
  1251. /**
  1252. * ep_fifo_flush: flushes contents of a fifo
  1253. *
  1254. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  1255. */
  1256. static void ep_fifo_flush(struct usb_ep *ep)
  1257. {
  1258. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1259. unsigned long flags;
  1260. if (ep == NULL) {
  1261. dev_err(hwep->ci->dev, "%02X: -EINVAL\n", _usb_addr(hwep));
  1262. return;
  1263. }
  1264. spin_lock_irqsave(hwep->lock, flags);
  1265. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  1266. spin_unlock_irqrestore(hwep->lock, flags);
  1267. }
  1268. /**
  1269. * Endpoint-specific part of the API to the USB controller hardware
  1270. * Check "usb_gadget.h" for details
  1271. */
  1272. static const struct usb_ep_ops usb_ep_ops = {
  1273. .enable = ep_enable,
  1274. .disable = ep_disable,
  1275. .alloc_request = ep_alloc_request,
  1276. .free_request = ep_free_request,
  1277. .queue = ep_queue,
  1278. .dequeue = ep_dequeue,
  1279. .set_halt = ep_set_halt,
  1280. .set_wedge = ep_set_wedge,
  1281. .fifo_flush = ep_fifo_flush,
  1282. };
  1283. /******************************************************************************
  1284. * GADGET block
  1285. *****************************************************************************/
  1286. static int ci_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
  1287. {
  1288. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1289. unsigned long flags;
  1290. int gadget_ready = 0;
  1291. spin_lock_irqsave(&ci->lock, flags);
  1292. ci->vbus_active = is_active;
  1293. if (ci->driver)
  1294. gadget_ready = 1;
  1295. spin_unlock_irqrestore(&ci->lock, flags);
  1296. if (gadget_ready) {
  1297. if (is_active) {
  1298. pm_runtime_get_sync(&_gadget->dev);
  1299. hw_device_reset(ci);
  1300. hw_device_state(ci, ci->ep0out->qh.dma);
  1301. usb_gadget_set_state(_gadget, USB_STATE_POWERED);
  1302. usb_udc_vbus_handler(_gadget, true);
  1303. } else {
  1304. usb_udc_vbus_handler(_gadget, false);
  1305. if (ci->driver)
  1306. ci->driver->disconnect(&ci->gadget);
  1307. hw_device_state(ci, 0);
  1308. if (ci->platdata->notify_event)
  1309. ci->platdata->notify_event(ci,
  1310. CI_HDRC_CONTROLLER_STOPPED_EVENT);
  1311. _gadget_stop_activity(&ci->gadget);
  1312. pm_runtime_put_sync(&_gadget->dev);
  1313. usb_gadget_set_state(_gadget, USB_STATE_NOTATTACHED);
  1314. }
  1315. }
  1316. return 0;
  1317. }
  1318. static int ci_udc_wakeup(struct usb_gadget *_gadget)
  1319. {
  1320. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1321. unsigned long flags;
  1322. int ret = 0;
  1323. spin_lock_irqsave(&ci->lock, flags);
  1324. if (!ci->remote_wakeup) {
  1325. ret = -EOPNOTSUPP;
  1326. goto out;
  1327. }
  1328. if (!hw_read(ci, OP_PORTSC, PORTSC_SUSP)) {
  1329. ret = -EINVAL;
  1330. goto out;
  1331. }
  1332. hw_write(ci, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  1333. out:
  1334. spin_unlock_irqrestore(&ci->lock, flags);
  1335. return ret;
  1336. }
  1337. static int ci_udc_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1338. {
  1339. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1340. if (ci->usb_phy)
  1341. return usb_phy_set_power(ci->usb_phy, ma);
  1342. return -ENOTSUPP;
  1343. }
  1344. static int ci_udc_selfpowered(struct usb_gadget *_gadget, int is_on)
  1345. {
  1346. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1347. struct ci_hw_ep *hwep = ci->ep0in;
  1348. unsigned long flags;
  1349. spin_lock_irqsave(hwep->lock, flags);
  1350. _gadget->is_selfpowered = (is_on != 0);
  1351. spin_unlock_irqrestore(hwep->lock, flags);
  1352. return 0;
  1353. }
  1354. /* Change Data+ pullup status
  1355. * this func is used by usb_gadget_connect/disconnet
  1356. */
  1357. static int ci_udc_pullup(struct usb_gadget *_gadget, int is_on)
  1358. {
  1359. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1360. /*
  1361. * Data+ pullup controlled by OTG state machine in OTG fsm mode;
  1362. * and don't touch Data+ in host mode for dual role config.
  1363. */
  1364. if (ci_otg_is_fsm_mode(ci) || ci->role == CI_ROLE_HOST)
  1365. return 0;
  1366. pm_runtime_get_sync(&ci->gadget.dev);
  1367. if (is_on)
  1368. hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  1369. else
  1370. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  1371. pm_runtime_put_sync(&ci->gadget.dev);
  1372. return 0;
  1373. }
  1374. static int ci_udc_start(struct usb_gadget *gadget,
  1375. struct usb_gadget_driver *driver);
  1376. static int ci_udc_stop(struct usb_gadget *gadget);
  1377. /**
  1378. * Device operations part of the API to the USB controller hardware,
  1379. * which don't involve endpoints (or i/o)
  1380. * Check "usb_gadget.h" for details
  1381. */
  1382. static const struct usb_gadget_ops usb_gadget_ops = {
  1383. .vbus_session = ci_udc_vbus_session,
  1384. .wakeup = ci_udc_wakeup,
  1385. .set_selfpowered = ci_udc_selfpowered,
  1386. .pullup = ci_udc_pullup,
  1387. .vbus_draw = ci_udc_vbus_draw,
  1388. .udc_start = ci_udc_start,
  1389. .udc_stop = ci_udc_stop,
  1390. };
  1391. static int init_eps(struct ci_hdrc *ci)
  1392. {
  1393. int retval = 0, i, j;
  1394. for (i = 0; i < ci->hw_ep_max/2; i++)
  1395. for (j = RX; j <= TX; j++) {
  1396. int k = i + j * ci->hw_ep_max/2;
  1397. struct ci_hw_ep *hwep = &ci->ci_hw_ep[k];
  1398. scnprintf(hwep->name, sizeof(hwep->name), "ep%i%s", i,
  1399. (j == TX) ? "in" : "out");
  1400. hwep->ci = ci;
  1401. hwep->lock = &ci->lock;
  1402. hwep->td_pool = ci->td_pool;
  1403. hwep->ep.name = hwep->name;
  1404. hwep->ep.ops = &usb_ep_ops;
  1405. if (i == 0) {
  1406. hwep->ep.caps.type_control = true;
  1407. } else {
  1408. hwep->ep.caps.type_iso = true;
  1409. hwep->ep.caps.type_bulk = true;
  1410. hwep->ep.caps.type_int = true;
  1411. }
  1412. if (j == TX)
  1413. hwep->ep.caps.dir_in = true;
  1414. else
  1415. hwep->ep.caps.dir_out = true;
  1416. /*
  1417. * for ep0: maxP defined in desc, for other
  1418. * eps, maxP is set by epautoconfig() called
  1419. * by gadget layer
  1420. */
  1421. usb_ep_set_maxpacket_limit(&hwep->ep, (unsigned short)~0);
  1422. INIT_LIST_HEAD(&hwep->qh.queue);
  1423. hwep->qh.ptr = dma_pool_zalloc(ci->qh_pool, GFP_KERNEL,
  1424. &hwep->qh.dma);
  1425. if (hwep->qh.ptr == NULL)
  1426. retval = -ENOMEM;
  1427. /*
  1428. * set up shorthands for ep0 out and in endpoints,
  1429. * don't add to gadget's ep_list
  1430. */
  1431. if (i == 0) {
  1432. if (j == RX)
  1433. ci->ep0out = hwep;
  1434. else
  1435. ci->ep0in = hwep;
  1436. usb_ep_set_maxpacket_limit(&hwep->ep, CTRL_PAYLOAD_MAX);
  1437. continue;
  1438. }
  1439. list_add_tail(&hwep->ep.ep_list, &ci->gadget.ep_list);
  1440. }
  1441. return retval;
  1442. }
  1443. static void destroy_eps(struct ci_hdrc *ci)
  1444. {
  1445. int i;
  1446. for (i = 0; i < ci->hw_ep_max; i++) {
  1447. struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
  1448. if (hwep->pending_td)
  1449. free_pending_td(hwep);
  1450. dma_pool_free(ci->qh_pool, hwep->qh.ptr, hwep->qh.dma);
  1451. }
  1452. }
  1453. /**
  1454. * ci_udc_start: register a gadget driver
  1455. * @gadget: our gadget
  1456. * @driver: the driver being registered
  1457. *
  1458. * Interrupts are enabled here.
  1459. */
  1460. static int ci_udc_start(struct usb_gadget *gadget,
  1461. struct usb_gadget_driver *driver)
  1462. {
  1463. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  1464. unsigned long flags;
  1465. int retval = -ENOMEM;
  1466. if (driver->disconnect == NULL)
  1467. return -EINVAL;
  1468. ci->ep0out->ep.desc = &ctrl_endpt_out_desc;
  1469. retval = usb_ep_enable(&ci->ep0out->ep);
  1470. if (retval)
  1471. return retval;
  1472. ci->ep0in->ep.desc = &ctrl_endpt_in_desc;
  1473. retval = usb_ep_enable(&ci->ep0in->ep);
  1474. if (retval)
  1475. return retval;
  1476. ci->driver = driver;
  1477. /* Start otg fsm for B-device */
  1478. if (ci_otg_is_fsm_mode(ci) && ci->fsm.id) {
  1479. ci_hdrc_otg_fsm_start(ci);
  1480. return retval;
  1481. }
  1482. pm_runtime_get_sync(&ci->gadget.dev);
  1483. if (ci->vbus_active) {
  1484. spin_lock_irqsave(&ci->lock, flags);
  1485. hw_device_reset(ci);
  1486. } else {
  1487. usb_udc_vbus_handler(&ci->gadget, false);
  1488. pm_runtime_put_sync(&ci->gadget.dev);
  1489. return retval;
  1490. }
  1491. retval = hw_device_state(ci, ci->ep0out->qh.dma);
  1492. spin_unlock_irqrestore(&ci->lock, flags);
  1493. if (retval)
  1494. pm_runtime_put_sync(&ci->gadget.dev);
  1495. return retval;
  1496. }
  1497. static void ci_udc_stop_for_otg_fsm(struct ci_hdrc *ci)
  1498. {
  1499. if (!ci_otg_is_fsm_mode(ci))
  1500. return;
  1501. mutex_lock(&ci->fsm.lock);
  1502. if (ci->fsm.otg->state == OTG_STATE_A_PERIPHERAL) {
  1503. ci->fsm.a_bidl_adis_tmout = 1;
  1504. ci_hdrc_otg_fsm_start(ci);
  1505. } else if (ci->fsm.otg->state == OTG_STATE_B_PERIPHERAL) {
  1506. ci->fsm.protocol = PROTO_UNDEF;
  1507. ci->fsm.otg->state = OTG_STATE_UNDEFINED;
  1508. }
  1509. mutex_unlock(&ci->fsm.lock);
  1510. }
  1511. /**
  1512. * ci_udc_stop: unregister a gadget driver
  1513. */
  1514. static int ci_udc_stop(struct usb_gadget *gadget)
  1515. {
  1516. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  1517. unsigned long flags;
  1518. spin_lock_irqsave(&ci->lock, flags);
  1519. if (ci->vbus_active) {
  1520. hw_device_state(ci, 0);
  1521. if (ci->platdata->notify_event)
  1522. ci->platdata->notify_event(ci,
  1523. CI_HDRC_CONTROLLER_STOPPED_EVENT);
  1524. spin_unlock_irqrestore(&ci->lock, flags);
  1525. _gadget_stop_activity(&ci->gadget);
  1526. spin_lock_irqsave(&ci->lock, flags);
  1527. pm_runtime_put(&ci->gadget.dev);
  1528. }
  1529. ci->driver = NULL;
  1530. spin_unlock_irqrestore(&ci->lock, flags);
  1531. ci_udc_stop_for_otg_fsm(ci);
  1532. return 0;
  1533. }
  1534. /******************************************************************************
  1535. * BUS block
  1536. *****************************************************************************/
  1537. /**
  1538. * udc_irq: ci interrupt handler
  1539. *
  1540. * This function returns IRQ_HANDLED if the IRQ has been handled
  1541. * It locks access to registers
  1542. */
  1543. static irqreturn_t udc_irq(struct ci_hdrc *ci)
  1544. {
  1545. irqreturn_t retval;
  1546. u32 intr;
  1547. if (ci == NULL)
  1548. return IRQ_HANDLED;
  1549. spin_lock(&ci->lock);
  1550. if (ci->platdata->flags & CI_HDRC_REGS_SHARED) {
  1551. if (hw_read(ci, OP_USBMODE, USBMODE_CM) !=
  1552. USBMODE_CM_DC) {
  1553. spin_unlock(&ci->lock);
  1554. return IRQ_NONE;
  1555. }
  1556. }
  1557. intr = hw_test_and_clear_intr_active(ci);
  1558. if (intr) {
  1559. /* order defines priority - do NOT change it */
  1560. if (USBi_URI & intr)
  1561. isr_reset_handler(ci);
  1562. if (USBi_PCI & intr) {
  1563. ci->gadget.speed = hw_port_is_high_speed(ci) ?
  1564. USB_SPEED_HIGH : USB_SPEED_FULL;
  1565. if (ci->suspended && ci->driver->resume) {
  1566. spin_unlock(&ci->lock);
  1567. ci->driver->resume(&ci->gadget);
  1568. spin_lock(&ci->lock);
  1569. ci->suspended = 0;
  1570. }
  1571. }
  1572. if (USBi_UI & intr)
  1573. isr_tr_complete_handler(ci);
  1574. if (USBi_SLI & intr) {
  1575. if (ci->gadget.speed != USB_SPEED_UNKNOWN &&
  1576. ci->driver->suspend) {
  1577. ci->suspended = 1;
  1578. spin_unlock(&ci->lock);
  1579. ci->driver->suspend(&ci->gadget);
  1580. usb_gadget_set_state(&ci->gadget,
  1581. USB_STATE_SUSPENDED);
  1582. spin_lock(&ci->lock);
  1583. }
  1584. }
  1585. retval = IRQ_HANDLED;
  1586. } else {
  1587. retval = IRQ_NONE;
  1588. }
  1589. spin_unlock(&ci->lock);
  1590. return retval;
  1591. }
  1592. /**
  1593. * udc_start: initialize gadget role
  1594. * @ci: chipidea controller
  1595. */
  1596. static int udc_start(struct ci_hdrc *ci)
  1597. {
  1598. struct device *dev = ci->dev;
  1599. struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
  1600. int retval = 0;
  1601. ci->gadget.ops = &usb_gadget_ops;
  1602. ci->gadget.speed = USB_SPEED_UNKNOWN;
  1603. ci->gadget.max_speed = USB_SPEED_HIGH;
  1604. ci->gadget.name = ci->platdata->name;
  1605. ci->gadget.otg_caps = otg_caps;
  1606. if (ci->is_otg && (otg_caps->hnp_support || otg_caps->srp_support ||
  1607. otg_caps->adp_support))
  1608. ci->gadget.is_otg = 1;
  1609. INIT_LIST_HEAD(&ci->gadget.ep_list);
  1610. /* alloc resources */
  1611. ci->qh_pool = dma_pool_create("ci_hw_qh", dev,
  1612. sizeof(struct ci_hw_qh),
  1613. 64, CI_HDRC_PAGE_SIZE);
  1614. if (ci->qh_pool == NULL)
  1615. return -ENOMEM;
  1616. ci->td_pool = dma_pool_create("ci_hw_td", dev,
  1617. sizeof(struct ci_hw_td),
  1618. 64, CI_HDRC_PAGE_SIZE);
  1619. if (ci->td_pool == NULL) {
  1620. retval = -ENOMEM;
  1621. goto free_qh_pool;
  1622. }
  1623. retval = init_eps(ci);
  1624. if (retval)
  1625. goto free_pools;
  1626. ci->gadget.ep0 = &ci->ep0in->ep;
  1627. retval = usb_add_gadget_udc(dev, &ci->gadget);
  1628. if (retval)
  1629. goto destroy_eps;
  1630. pm_runtime_no_callbacks(&ci->gadget.dev);
  1631. pm_runtime_enable(&ci->gadget.dev);
  1632. return retval;
  1633. destroy_eps:
  1634. destroy_eps(ci);
  1635. free_pools:
  1636. dma_pool_destroy(ci->td_pool);
  1637. free_qh_pool:
  1638. dma_pool_destroy(ci->qh_pool);
  1639. return retval;
  1640. }
  1641. /**
  1642. * ci_hdrc_gadget_destroy: parent remove must call this to remove UDC
  1643. *
  1644. * No interrupts active, the IRQ has been released
  1645. */
  1646. void ci_hdrc_gadget_destroy(struct ci_hdrc *ci)
  1647. {
  1648. if (!ci->roles[CI_ROLE_GADGET])
  1649. return;
  1650. usb_del_gadget_udc(&ci->gadget);
  1651. destroy_eps(ci);
  1652. dma_pool_destroy(ci->td_pool);
  1653. dma_pool_destroy(ci->qh_pool);
  1654. }
  1655. static int udc_id_switch_for_device(struct ci_hdrc *ci)
  1656. {
  1657. if (ci->is_otg)
  1658. /* Clear and enable BSV irq */
  1659. hw_write_otgsc(ci, OTGSC_BSVIS | OTGSC_BSVIE,
  1660. OTGSC_BSVIS | OTGSC_BSVIE);
  1661. return 0;
  1662. }
  1663. static void udc_id_switch_for_host(struct ci_hdrc *ci)
  1664. {
  1665. /*
  1666. * host doesn't care B_SESSION_VALID event
  1667. * so clear and disbale BSV irq
  1668. */
  1669. if (ci->is_otg)
  1670. hw_write_otgsc(ci, OTGSC_BSVIE | OTGSC_BSVIS, OTGSC_BSVIS);
  1671. }
  1672. /**
  1673. * ci_hdrc_gadget_init - initialize device related bits
  1674. * ci: the controller
  1675. *
  1676. * This function initializes the gadget, if the device is "device capable".
  1677. */
  1678. int ci_hdrc_gadget_init(struct ci_hdrc *ci)
  1679. {
  1680. struct ci_role_driver *rdrv;
  1681. int ret;
  1682. if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DC))
  1683. return -ENXIO;
  1684. rdrv = devm_kzalloc(ci->dev, sizeof(*rdrv), GFP_KERNEL);
  1685. if (!rdrv)
  1686. return -ENOMEM;
  1687. rdrv->start = udc_id_switch_for_device;
  1688. rdrv->stop = udc_id_switch_for_host;
  1689. rdrv->irq = udc_irq;
  1690. rdrv->name = "gadget";
  1691. ret = udc_start(ci);
  1692. if (!ret)
  1693. ci->roles[CI_ROLE_GADGET] = rdrv;
  1694. return ret;
  1695. }