gdth.c 174 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: unused
  87. * buffer: unused
  88. * dma_handle: unused
  89. * buffers_residual: unused
  90. * Status: unused
  91. * Message: unused
  92. * have_data_in: unused
  93. * sent_command: unused
  94. * phase: unused
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #include <linux/mutex.h>
  117. #include <linux/slab.h>
  118. #ifdef GDTH_RTC
  119. #include <linux/mc146818rtc.h>
  120. #endif
  121. #include <linux/reboot.h>
  122. #include <asm/dma.h>
  123. #include <asm/io.h>
  124. #include <asm/uaccess.h>
  125. #include <linux/spinlock.h>
  126. #include <linux/blkdev.h>
  127. #include <linux/scatterlist.h>
  128. #include "scsi.h"
  129. #include <scsi/scsi_host.h>
  130. #include "gdth.h"
  131. static DEFINE_MUTEX(gdth_mutex);
  132. static void gdth_delay(int milliseconds);
  133. static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs);
  134. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  135. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  136. int gdth_from_wait, int* pIndex);
  137. static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
  138. Scsi_Cmnd *scp);
  139. static int gdth_async_event(gdth_ha_str *ha);
  140. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  141. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority);
  142. static void gdth_next(gdth_ha_str *ha);
  143. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b);
  144. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  145. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
  146. u16 idx, gdth_evt_data *evt);
  147. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  148. static void gdth_readapp_event(gdth_ha_str *ha, u8 application,
  149. gdth_evt_str *estr);
  150. static void gdth_clear_events(void);
  151. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  152. char *buffer, u16 count);
  153. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  154. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive);
  155. static void gdth_enable_int(gdth_ha_str *ha);
  156. static int gdth_test_busy(gdth_ha_str *ha);
  157. static int gdth_get_cmd_index(gdth_ha_str *ha);
  158. static void gdth_release_event(gdth_ha_str *ha);
  159. static int gdth_wait(gdth_ha_str *ha, int index,u32 time);
  160. static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
  161. u32 p1, u64 p2,u64 p3);
  162. static int gdth_search_drives(gdth_ha_str *ha);
  163. static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive);
  164. static const char *gdth_ctr_name(gdth_ha_str *ha);
  165. static int gdth_open(struct inode *inode, struct file *filep);
  166. static int gdth_close(struct inode *inode, struct file *filep);
  167. static long gdth_unlocked_ioctl(struct file *filep, unsigned int cmd,
  168. unsigned long arg);
  169. static void gdth_flush(gdth_ha_str *ha);
  170. static int gdth_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  171. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  172. struct gdth_cmndinfo *cmndinfo);
  173. static void gdth_scsi_done(struct scsi_cmnd *scp);
  174. #ifdef DEBUG_GDTH
  175. static u8 DebugState = DEBUG_GDTH;
  176. #ifdef __SERIAL__
  177. #define MAX_SERBUF 160
  178. static void ser_init(void);
  179. static void ser_puts(char *str);
  180. static void ser_putc(char c);
  181. static int ser_printk(const char *fmt, ...);
  182. static char strbuf[MAX_SERBUF+1];
  183. #ifdef __COM2__
  184. #define COM_BASE 0x2f8
  185. #else
  186. #define COM_BASE 0x3f8
  187. #endif
  188. static void ser_init()
  189. {
  190. unsigned port=COM_BASE;
  191. outb(0x80,port+3);
  192. outb(0,port+1);
  193. /* 19200 Baud, if 9600: outb(12,port) */
  194. outb(6, port);
  195. outb(3,port+3);
  196. outb(0,port+1);
  197. /*
  198. ser_putc('I');
  199. ser_putc(' ');
  200. */
  201. }
  202. static void ser_puts(char *str)
  203. {
  204. char *ptr;
  205. ser_init();
  206. for (ptr=str;*ptr;++ptr)
  207. ser_putc(*ptr);
  208. }
  209. static void ser_putc(char c)
  210. {
  211. unsigned port=COM_BASE;
  212. while ((inb(port+5) & 0x20)==0);
  213. outb(c,port);
  214. if (c==0x0a)
  215. {
  216. while ((inb(port+5) & 0x20)==0);
  217. outb(0x0d,port);
  218. }
  219. }
  220. static int ser_printk(const char *fmt, ...)
  221. {
  222. va_list args;
  223. int i;
  224. va_start(args,fmt);
  225. i = vsprintf(strbuf,fmt,args);
  226. ser_puts(strbuf);
  227. va_end(args);
  228. return i;
  229. }
  230. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  231. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  232. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  233. #else /* !__SERIAL__ */
  234. #define TRACE(a) {if (DebugState==1) {printk a;}}
  235. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  236. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  237. #endif
  238. #else /* !DEBUG */
  239. #define TRACE(a)
  240. #define TRACE2(a)
  241. #define TRACE3(a)
  242. #endif
  243. #ifdef GDTH_STATISTICS
  244. static u32 max_rq=0, max_index=0, max_sg=0;
  245. #ifdef INT_COAL
  246. static u32 max_int_coal=0;
  247. #endif
  248. static u32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  249. static struct timer_list gdth_timer;
  250. #endif
  251. #define PTR2USHORT(a) (u16)(unsigned long)(a)
  252. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  253. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  254. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  255. #ifdef CONFIG_ISA
  256. static u8 gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  257. #endif
  258. #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
  259. static u8 gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  260. #endif
  261. static u8 gdth_polling; /* polling if TRUE */
  262. static int gdth_ctr_count = 0; /* controller count */
  263. static LIST_HEAD(gdth_instances); /* controller list */
  264. static u8 gdth_write_through = FALSE; /* write through */
  265. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  266. static int elastidx;
  267. static int eoldidx;
  268. static int major;
  269. #define DIN 1 /* IN data direction */
  270. #define DOU 2 /* OUT data direction */
  271. #define DNO DIN /* no data transfer */
  272. #define DUN DIN /* unknown data direction */
  273. static u8 gdth_direction_tab[0x100] = {
  274. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  275. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  276. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  277. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  278. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  279. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  283. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  284. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  285. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  288. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  289. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  290. };
  291. /* LILO and modprobe/insmod parameters */
  292. /* IRQ list for GDT3000/3020 EISA controllers */
  293. static int irq[MAXHA] __initdata =
  294. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  295. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  296. /* disable driver flag */
  297. static int disable __initdata = 0;
  298. /* reserve flag */
  299. static int reserve_mode = 1;
  300. /* reserve list */
  301. static int reserve_list[MAX_RES_ARGS] =
  302. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  303. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  304. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  305. /* scan order for PCI controllers */
  306. static int reverse_scan = 0;
  307. /* virtual channel for the host drives */
  308. static int hdr_channel = 0;
  309. /* max. IDs per channel */
  310. static int max_ids = MAXID;
  311. /* rescan all IDs */
  312. static int rescan = 0;
  313. /* shared access */
  314. static int shared_access = 1;
  315. /* enable support for EISA and ISA controllers */
  316. static int probe_eisa_isa = 0;
  317. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  318. static int force_dma32 = 0;
  319. /* parameters for modprobe/insmod */
  320. module_param_array(irq, int, NULL, 0);
  321. module_param(disable, int, 0);
  322. module_param(reserve_mode, int, 0);
  323. module_param_array(reserve_list, int, NULL, 0);
  324. module_param(reverse_scan, int, 0);
  325. module_param(hdr_channel, int, 0);
  326. module_param(max_ids, int, 0);
  327. module_param(rescan, int, 0);
  328. module_param(shared_access, int, 0);
  329. module_param(probe_eisa_isa, int, 0);
  330. module_param(force_dma32, int, 0);
  331. MODULE_AUTHOR("Achim Leubner");
  332. MODULE_LICENSE("GPL");
  333. /* ioctl interface */
  334. static const struct file_operations gdth_fops = {
  335. .unlocked_ioctl = gdth_unlocked_ioctl,
  336. .open = gdth_open,
  337. .release = gdth_close,
  338. .llseek = noop_llseek,
  339. };
  340. #include "gdth_proc.h"
  341. #include "gdth_proc.c"
  342. static gdth_ha_str *gdth_find_ha(int hanum)
  343. {
  344. gdth_ha_str *ha;
  345. list_for_each_entry(ha, &gdth_instances, list)
  346. if (hanum == ha->hanum)
  347. return ha;
  348. return NULL;
  349. }
  350. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  351. {
  352. struct gdth_cmndinfo *priv = NULL;
  353. unsigned long flags;
  354. int i;
  355. spin_lock_irqsave(&ha->smp_lock, flags);
  356. for (i=0; i<GDTH_MAXCMDS; ++i) {
  357. if (ha->cmndinfo[i].index == 0) {
  358. priv = &ha->cmndinfo[i];
  359. memset(priv, 0, sizeof(*priv));
  360. priv->index = i+1;
  361. break;
  362. }
  363. }
  364. spin_unlock_irqrestore(&ha->smp_lock, flags);
  365. return priv;
  366. }
  367. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  368. {
  369. BUG_ON(!priv);
  370. priv->index = 0;
  371. }
  372. static void gdth_delay(int milliseconds)
  373. {
  374. if (milliseconds == 0) {
  375. udelay(1);
  376. } else {
  377. mdelay(milliseconds);
  378. }
  379. }
  380. static void gdth_scsi_done(struct scsi_cmnd *scp)
  381. {
  382. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  383. int internal_command = cmndinfo->internal_command;
  384. TRACE2(("gdth_scsi_done()\n"));
  385. gdth_put_cmndinfo(cmndinfo);
  386. scp->host_scribble = NULL;
  387. if (internal_command)
  388. complete((struct completion *)scp->request);
  389. else
  390. scp->scsi_done(scp);
  391. }
  392. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  393. int timeout, u32 *info)
  394. {
  395. gdth_ha_str *ha = shost_priv(sdev->host);
  396. Scsi_Cmnd *scp;
  397. struct gdth_cmndinfo cmndinfo;
  398. DECLARE_COMPLETION_ONSTACK(wait);
  399. int rval;
  400. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  401. if (!scp)
  402. return -ENOMEM;
  403. scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  404. if (!scp->sense_buffer) {
  405. kfree(scp);
  406. return -ENOMEM;
  407. }
  408. scp->device = sdev;
  409. memset(&cmndinfo, 0, sizeof(cmndinfo));
  410. /* use request field to save the ptr. to completion struct. */
  411. scp->request = (struct request *)&wait;
  412. scp->cmd_len = 12;
  413. scp->cmnd = cmnd;
  414. cmndinfo.priority = IOCTL_PRI;
  415. cmndinfo.internal_cmd_str = gdtcmd;
  416. cmndinfo.internal_command = 1;
  417. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  418. __gdth_queuecommand(ha, scp, &cmndinfo);
  419. wait_for_completion(&wait);
  420. rval = cmndinfo.status;
  421. if (info)
  422. *info = cmndinfo.info;
  423. kfree(scp->sense_buffer);
  424. kfree(scp);
  425. return rval;
  426. }
  427. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  428. int timeout, u32 *info)
  429. {
  430. struct scsi_device *sdev = scsi_get_host_dev(shost);
  431. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  432. scsi_free_host_dev(sdev);
  433. return rval;
  434. }
  435. static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs)
  436. {
  437. *cyls = size /HEADS/SECS;
  438. if (*cyls <= MAXCYLS) {
  439. *heads = HEADS;
  440. *secs = SECS;
  441. } else { /* too high for 64*32 */
  442. *cyls = size /MEDHEADS/MEDSECS;
  443. if (*cyls <= MAXCYLS) {
  444. *heads = MEDHEADS;
  445. *secs = MEDSECS;
  446. } else { /* too high for 127*63 */
  447. *cyls = size /BIGHEADS/BIGSECS;
  448. *heads = BIGHEADS;
  449. *secs = BIGSECS;
  450. }
  451. }
  452. }
  453. /* controller search and initialization functions */
  454. #ifdef CONFIG_EISA
  455. static int __init gdth_search_eisa(u16 eisa_adr)
  456. {
  457. u32 id;
  458. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  459. id = inl(eisa_adr+ID0REG);
  460. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  461. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  462. return 0; /* not EISA configured */
  463. return 1;
  464. }
  465. if (id == GDT3_ID) /* GDT3000 */
  466. return 1;
  467. return 0;
  468. }
  469. #endif /* CONFIG_EISA */
  470. #ifdef CONFIG_ISA
  471. static int __init gdth_search_isa(u32 bios_adr)
  472. {
  473. void __iomem *addr;
  474. u32 id;
  475. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  476. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(u32))) != NULL) {
  477. id = readl(addr);
  478. iounmap(addr);
  479. if (id == GDT2_ID) /* GDT2000 */
  480. return 1;
  481. }
  482. return 0;
  483. }
  484. #endif /* CONFIG_ISA */
  485. #ifdef CONFIG_PCI
  486. static bool gdth_search_vortex(u16 device)
  487. {
  488. if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
  489. return true;
  490. if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP &&
  491. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP)
  492. return true;
  493. if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX ||
  494. device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2)
  495. return true;
  496. return false;
  497. }
  498. static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out);
  499. static int gdth_pci_init_one(struct pci_dev *pdev,
  500. const struct pci_device_id *ent);
  501. static void gdth_pci_remove_one(struct pci_dev *pdev);
  502. static void gdth_remove_one(gdth_ha_str *ha);
  503. /* Vortex only makes RAID controllers.
  504. * We do not really want to specify all 550 ids here, so wildcard match.
  505. */
  506. static const struct pci_device_id gdthtable[] = {
  507. { PCI_VDEVICE(VORTEX, PCI_ANY_ID) },
  508. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) },
  509. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) },
  510. { } /* terminate list */
  511. };
  512. MODULE_DEVICE_TABLE(pci, gdthtable);
  513. static struct pci_driver gdth_pci_driver = {
  514. .name = "gdth",
  515. .id_table = gdthtable,
  516. .probe = gdth_pci_init_one,
  517. .remove = gdth_pci_remove_one,
  518. };
  519. static void gdth_pci_remove_one(struct pci_dev *pdev)
  520. {
  521. gdth_ha_str *ha = pci_get_drvdata(pdev);
  522. list_del(&ha->list);
  523. gdth_remove_one(ha);
  524. pci_disable_device(pdev);
  525. }
  526. static int gdth_pci_init_one(struct pci_dev *pdev,
  527. const struct pci_device_id *ent)
  528. {
  529. u16 vendor = pdev->vendor;
  530. u16 device = pdev->device;
  531. unsigned long base0, base1, base2;
  532. int rc;
  533. gdth_pci_str gdth_pcistr;
  534. gdth_ha_str *ha = NULL;
  535. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  536. gdth_ctr_count, vendor, device));
  537. memset(&gdth_pcistr, 0, sizeof(gdth_pcistr));
  538. if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device))
  539. return -ENODEV;
  540. rc = pci_enable_device(pdev);
  541. if (rc)
  542. return rc;
  543. if (gdth_ctr_count >= MAXHA)
  544. return -EBUSY;
  545. /* GDT PCI controller found, resources are already in pdev */
  546. gdth_pcistr.pdev = pdev;
  547. base0 = pci_resource_flags(pdev, 0);
  548. base1 = pci_resource_flags(pdev, 1);
  549. base2 = pci_resource_flags(pdev, 2);
  550. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  551. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  552. if (!(base0 & IORESOURCE_MEM))
  553. return -ENODEV;
  554. gdth_pcistr.dpmem = pci_resource_start(pdev, 0);
  555. } else { /* GDT6110, GDT6120, .. */
  556. if (!(base0 & IORESOURCE_MEM) ||
  557. !(base2 & IORESOURCE_MEM) ||
  558. !(base1 & IORESOURCE_IO))
  559. return -ENODEV;
  560. gdth_pcistr.dpmem = pci_resource_start(pdev, 2);
  561. gdth_pcistr.io = pci_resource_start(pdev, 1);
  562. }
  563. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  564. gdth_pcistr.pdev->bus->number,
  565. PCI_SLOT(gdth_pcistr.pdev->devfn),
  566. gdth_pcistr.irq,
  567. gdth_pcistr.dpmem));
  568. rc = gdth_pci_probe_one(&gdth_pcistr, &ha);
  569. if (rc)
  570. return rc;
  571. return 0;
  572. }
  573. #endif /* CONFIG_PCI */
  574. #ifdef CONFIG_EISA
  575. static int __init gdth_init_eisa(u16 eisa_adr,gdth_ha_str *ha)
  576. {
  577. u32 retries,id;
  578. u8 prot_ver,eisacf,i,irq_found;
  579. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  580. /* disable board interrupts, deinitialize services */
  581. outb(0xff,eisa_adr+EDOORREG);
  582. outb(0x00,eisa_adr+EDENABREG);
  583. outb(0x00,eisa_adr+EINTENABREG);
  584. outb(0xff,eisa_adr+LDOORREG);
  585. retries = INIT_RETRIES;
  586. gdth_delay(20);
  587. while (inb(eisa_adr+EDOORREG) != 0xff) {
  588. if (--retries == 0) {
  589. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  590. return 0;
  591. }
  592. gdth_delay(1);
  593. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  594. }
  595. prot_ver = inb(eisa_adr+MAILBOXREG);
  596. outb(0xff,eisa_adr+EDOORREG);
  597. if (prot_ver != PROTOCOL_VERSION) {
  598. printk("GDT-EISA: Illegal protocol version\n");
  599. return 0;
  600. }
  601. ha->bmic = eisa_adr;
  602. ha->brd_phys = (u32)eisa_adr >> 12;
  603. outl(0,eisa_adr+MAILBOXREG);
  604. outl(0,eisa_adr+MAILBOXREG+4);
  605. outl(0,eisa_adr+MAILBOXREG+8);
  606. outl(0,eisa_adr+MAILBOXREG+12);
  607. /* detect IRQ */
  608. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  609. ha->oem_id = OEM_ID_ICP;
  610. ha->type = GDT_EISA;
  611. ha->stype = id;
  612. outl(1,eisa_adr+MAILBOXREG+8);
  613. outb(0xfe,eisa_adr+LDOORREG);
  614. retries = INIT_RETRIES;
  615. gdth_delay(20);
  616. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  617. if (--retries == 0) {
  618. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  619. return 0;
  620. }
  621. gdth_delay(1);
  622. }
  623. ha->irq = inb(eisa_adr+MAILBOXREG);
  624. outb(0xff,eisa_adr+EDOORREG);
  625. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  626. /* check the result */
  627. if (ha->irq == 0) {
  628. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  629. for (i = 0, irq_found = FALSE;
  630. i < MAXHA && irq[i] != 0xff; ++i) {
  631. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  632. irq_found = TRUE;
  633. break;
  634. }
  635. }
  636. if (irq_found) {
  637. ha->irq = irq[i];
  638. irq[i] = 0;
  639. printk("GDT-EISA: Can not detect controller IRQ,\n");
  640. printk("Use IRQ setting from command line (IRQ = %d)\n",
  641. ha->irq);
  642. } else {
  643. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  644. printk("the controller BIOS or use command line parameters\n");
  645. return 0;
  646. }
  647. }
  648. } else {
  649. eisacf = inb(eisa_adr+EISAREG) & 7;
  650. if (eisacf > 4) /* level triggered */
  651. eisacf -= 4;
  652. ha->irq = gdth_irq_tab[eisacf];
  653. ha->oem_id = OEM_ID_ICP;
  654. ha->type = GDT_EISA;
  655. ha->stype = id;
  656. }
  657. ha->dma64_support = 0;
  658. return 1;
  659. }
  660. #endif /* CONFIG_EISA */
  661. #ifdef CONFIG_ISA
  662. static int __init gdth_init_isa(u32 bios_adr,gdth_ha_str *ha)
  663. {
  664. register gdt2_dpram_str __iomem *dp2_ptr;
  665. int i;
  666. u8 irq_drq,prot_ver;
  667. u32 retries;
  668. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  669. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  670. if (ha->brd == NULL) {
  671. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  672. return 0;
  673. }
  674. dp2_ptr = ha->brd;
  675. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  676. /* reset interface area */
  677. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  678. if (readl(&dp2_ptr->u) != 0) {
  679. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  680. iounmap(ha->brd);
  681. return 0;
  682. }
  683. /* disable board interrupts, read DRQ and IRQ */
  684. writeb(0xff, &dp2_ptr->io.irqdel);
  685. writeb(0x00, &dp2_ptr->io.irqen);
  686. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  687. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  688. irq_drq = readb(&dp2_ptr->io.rq);
  689. for (i=0; i<3; ++i) {
  690. if ((irq_drq & 1)==0)
  691. break;
  692. irq_drq >>= 1;
  693. }
  694. ha->drq = gdth_drq_tab[i];
  695. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  696. for (i=1; i<5; ++i) {
  697. if ((irq_drq & 1)==0)
  698. break;
  699. irq_drq >>= 1;
  700. }
  701. ha->irq = gdth_irq_tab[i];
  702. /* deinitialize services */
  703. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  704. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  705. writeb(0, &dp2_ptr->io.event);
  706. retries = INIT_RETRIES;
  707. gdth_delay(20);
  708. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  709. if (--retries == 0) {
  710. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  711. iounmap(ha->brd);
  712. return 0;
  713. }
  714. gdth_delay(1);
  715. }
  716. prot_ver = (u8)readl(&dp2_ptr->u.ic.S_Info[0]);
  717. writeb(0, &dp2_ptr->u.ic.Status);
  718. writeb(0xff, &dp2_ptr->io.irqdel);
  719. if (prot_ver != PROTOCOL_VERSION) {
  720. printk("GDT-ISA: Illegal protocol version\n");
  721. iounmap(ha->brd);
  722. return 0;
  723. }
  724. ha->oem_id = OEM_ID_ICP;
  725. ha->type = GDT_ISA;
  726. ha->ic_all_size = sizeof(dp2_ptr->u);
  727. ha->stype= GDT2_ID;
  728. ha->brd_phys = bios_adr >> 4;
  729. /* special request to controller BIOS */
  730. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  731. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  732. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  733. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  734. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  735. writeb(0, &dp2_ptr->io.event);
  736. retries = INIT_RETRIES;
  737. gdth_delay(20);
  738. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  739. if (--retries == 0) {
  740. printk("GDT-ISA: Initialization error\n");
  741. iounmap(ha->brd);
  742. return 0;
  743. }
  744. gdth_delay(1);
  745. }
  746. writeb(0, &dp2_ptr->u.ic.Status);
  747. writeb(0xff, &dp2_ptr->io.irqdel);
  748. ha->dma64_support = 0;
  749. return 1;
  750. }
  751. #endif /* CONFIG_ISA */
  752. #ifdef CONFIG_PCI
  753. static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
  754. gdth_ha_str *ha)
  755. {
  756. register gdt6_dpram_str __iomem *dp6_ptr;
  757. register gdt6c_dpram_str __iomem *dp6c_ptr;
  758. register gdt6m_dpram_str __iomem *dp6m_ptr;
  759. u32 retries;
  760. u8 prot_ver;
  761. u16 command;
  762. int i, found = FALSE;
  763. TRACE(("gdth_init_pci()\n"));
  764. if (pdev->vendor == PCI_VENDOR_ID_INTEL)
  765. ha->oem_id = OEM_ID_INTEL;
  766. else
  767. ha->oem_id = OEM_ID_ICP;
  768. ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8);
  769. ha->stype = (u32)pdev->device;
  770. ha->irq = pdev->irq;
  771. ha->pdev = pdev;
  772. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  773. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  774. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  775. if (ha->brd == NULL) {
  776. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  777. return 0;
  778. }
  779. /* check and reset interface area */
  780. dp6_ptr = ha->brd;
  781. writel(DPMEM_MAGIC, &dp6_ptr->u);
  782. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  783. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  784. pcistr->dpmem);
  785. found = FALSE;
  786. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  787. iounmap(ha->brd);
  788. ha->brd = ioremap(i, sizeof(u16));
  789. if (ha->brd == NULL) {
  790. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  791. return 0;
  792. }
  793. if (readw(ha->brd) != 0xffff) {
  794. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  795. continue;
  796. }
  797. iounmap(ha->brd);
  798. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  799. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  800. if (ha->brd == NULL) {
  801. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  802. return 0;
  803. }
  804. dp6_ptr = ha->brd;
  805. writel(DPMEM_MAGIC, &dp6_ptr->u);
  806. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  807. printk("GDT-PCI: Use free address at 0x%x\n", i);
  808. found = TRUE;
  809. break;
  810. }
  811. }
  812. if (!found) {
  813. printk("GDT-PCI: No free address found!\n");
  814. iounmap(ha->brd);
  815. return 0;
  816. }
  817. }
  818. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  819. if (readl(&dp6_ptr->u) != 0) {
  820. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  821. iounmap(ha->brd);
  822. return 0;
  823. }
  824. /* disable board interrupts, deinit services */
  825. writeb(0xff, &dp6_ptr->io.irqdel);
  826. writeb(0x00, &dp6_ptr->io.irqen);
  827. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  828. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  829. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  830. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  831. writeb(0, &dp6_ptr->io.event);
  832. retries = INIT_RETRIES;
  833. gdth_delay(20);
  834. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  835. if (--retries == 0) {
  836. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  837. iounmap(ha->brd);
  838. return 0;
  839. }
  840. gdth_delay(1);
  841. }
  842. prot_ver = (u8)readl(&dp6_ptr->u.ic.S_Info[0]);
  843. writeb(0, &dp6_ptr->u.ic.S_Status);
  844. writeb(0xff, &dp6_ptr->io.irqdel);
  845. if (prot_ver != PROTOCOL_VERSION) {
  846. printk("GDT-PCI: Illegal protocol version\n");
  847. iounmap(ha->brd);
  848. return 0;
  849. }
  850. ha->type = GDT_PCI;
  851. ha->ic_all_size = sizeof(dp6_ptr->u);
  852. /* special command to controller BIOS */
  853. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  854. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  855. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  856. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  857. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  858. writeb(0, &dp6_ptr->io.event);
  859. retries = INIT_RETRIES;
  860. gdth_delay(20);
  861. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  862. if (--retries == 0) {
  863. printk("GDT-PCI: Initialization error\n");
  864. iounmap(ha->brd);
  865. return 0;
  866. }
  867. gdth_delay(1);
  868. }
  869. writeb(0, &dp6_ptr->u.ic.S_Status);
  870. writeb(0xff, &dp6_ptr->io.irqdel);
  871. ha->dma64_support = 0;
  872. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  873. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  874. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  875. pcistr->dpmem,ha->irq));
  876. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  877. if (ha->brd == NULL) {
  878. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  879. iounmap(ha->brd);
  880. return 0;
  881. }
  882. /* check and reset interface area */
  883. dp6c_ptr = ha->brd;
  884. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  885. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  886. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  887. pcistr->dpmem);
  888. found = FALSE;
  889. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  890. iounmap(ha->brd);
  891. ha->brd = ioremap(i, sizeof(u16));
  892. if (ha->brd == NULL) {
  893. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  894. return 0;
  895. }
  896. if (readw(ha->brd) != 0xffff) {
  897. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  898. continue;
  899. }
  900. iounmap(ha->brd);
  901. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i);
  902. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  903. if (ha->brd == NULL) {
  904. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  905. return 0;
  906. }
  907. dp6c_ptr = ha->brd;
  908. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  909. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  910. printk("GDT-PCI: Use free address at 0x%x\n", i);
  911. found = TRUE;
  912. break;
  913. }
  914. }
  915. if (!found) {
  916. printk("GDT-PCI: No free address found!\n");
  917. iounmap(ha->brd);
  918. return 0;
  919. }
  920. }
  921. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  922. if (readl(&dp6c_ptr->u) != 0) {
  923. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  924. iounmap(ha->brd);
  925. return 0;
  926. }
  927. /* disable board interrupts, deinit services */
  928. outb(0x00,PTR2USHORT(&ha->plx->control1));
  929. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  930. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  931. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  932. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  933. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  934. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  935. retries = INIT_RETRIES;
  936. gdth_delay(20);
  937. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  938. if (--retries == 0) {
  939. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  940. iounmap(ha->brd);
  941. return 0;
  942. }
  943. gdth_delay(1);
  944. }
  945. prot_ver = (u8)readl(&dp6c_ptr->u.ic.S_Info[0]);
  946. writeb(0, &dp6c_ptr->u.ic.Status);
  947. if (prot_ver != PROTOCOL_VERSION) {
  948. printk("GDT-PCI: Illegal protocol version\n");
  949. iounmap(ha->brd);
  950. return 0;
  951. }
  952. ha->type = GDT_PCINEW;
  953. ha->ic_all_size = sizeof(dp6c_ptr->u);
  954. /* special command to controller BIOS */
  955. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  956. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  957. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  958. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  959. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  960. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  961. retries = INIT_RETRIES;
  962. gdth_delay(20);
  963. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  964. if (--retries == 0) {
  965. printk("GDT-PCI: Initialization error\n");
  966. iounmap(ha->brd);
  967. return 0;
  968. }
  969. gdth_delay(1);
  970. }
  971. writeb(0, &dp6c_ptr->u.ic.S_Status);
  972. ha->dma64_support = 0;
  973. } else { /* MPR */
  974. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  975. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  976. if (ha->brd == NULL) {
  977. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  978. return 0;
  979. }
  980. /* manipulate config. space to enable DPMEM, start RP controller */
  981. pci_read_config_word(pdev, PCI_COMMAND, &command);
  982. command |= 6;
  983. pci_write_config_word(pdev, PCI_COMMAND, command);
  984. gdth_delay(1);
  985. dp6m_ptr = ha->brd;
  986. /* Ensure that it is safe to access the non HW portions of DPMEM.
  987. * Aditional check needed for Xscale based RAID controllers */
  988. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  989. gdth_delay(1);
  990. /* check and reset interface area */
  991. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  992. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  993. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  994. pcistr->dpmem);
  995. found = FALSE;
  996. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  997. iounmap(ha->brd);
  998. ha->brd = ioremap(i, sizeof(u16));
  999. if (ha->brd == NULL) {
  1000. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1001. return 0;
  1002. }
  1003. if (readw(ha->brd) != 0xffff) {
  1004. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1005. continue;
  1006. }
  1007. iounmap(ha->brd);
  1008. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  1009. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1010. if (ha->brd == NULL) {
  1011. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1012. return 0;
  1013. }
  1014. dp6m_ptr = ha->brd;
  1015. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1016. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1017. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1018. found = TRUE;
  1019. break;
  1020. }
  1021. }
  1022. if (!found) {
  1023. printk("GDT-PCI: No free address found!\n");
  1024. iounmap(ha->brd);
  1025. return 0;
  1026. }
  1027. }
  1028. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1029. /* disable board interrupts, deinit services */
  1030. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1031. &dp6m_ptr->i960r.edoor_en_reg);
  1032. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1033. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1034. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1035. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1036. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1037. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1038. retries = INIT_RETRIES;
  1039. gdth_delay(20);
  1040. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1041. if (--retries == 0) {
  1042. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1043. iounmap(ha->brd);
  1044. return 0;
  1045. }
  1046. gdth_delay(1);
  1047. }
  1048. prot_ver = (u8)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1049. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1050. if (prot_ver != PROTOCOL_VERSION) {
  1051. printk("GDT-PCI: Illegal protocol version\n");
  1052. iounmap(ha->brd);
  1053. return 0;
  1054. }
  1055. ha->type = GDT_PCIMPR;
  1056. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1057. /* special command to controller BIOS */
  1058. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1059. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1060. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1061. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1062. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1063. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1064. retries = INIT_RETRIES;
  1065. gdth_delay(20);
  1066. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1067. if (--retries == 0) {
  1068. printk("GDT-PCI: Initialization error\n");
  1069. iounmap(ha->brd);
  1070. return 0;
  1071. }
  1072. gdth_delay(1);
  1073. }
  1074. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1075. /* read FW version to detect 64-bit DMA support */
  1076. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1077. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1078. retries = INIT_RETRIES;
  1079. gdth_delay(20);
  1080. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1081. if (--retries == 0) {
  1082. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1083. iounmap(ha->brd);
  1084. return 0;
  1085. }
  1086. gdth_delay(1);
  1087. }
  1088. prot_ver = (u8)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1089. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1090. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1091. ha->dma64_support = 0;
  1092. else
  1093. ha->dma64_support = 1;
  1094. }
  1095. return 1;
  1096. }
  1097. #endif /* CONFIG_PCI */
  1098. /* controller protocol functions */
  1099. static void gdth_enable_int(gdth_ha_str *ha)
  1100. {
  1101. unsigned long flags;
  1102. gdt2_dpram_str __iomem *dp2_ptr;
  1103. gdt6_dpram_str __iomem *dp6_ptr;
  1104. gdt6m_dpram_str __iomem *dp6m_ptr;
  1105. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1106. spin_lock_irqsave(&ha->smp_lock, flags);
  1107. if (ha->type == GDT_EISA) {
  1108. outb(0xff, ha->bmic + EDOORREG);
  1109. outb(0xff, ha->bmic + EDENABREG);
  1110. outb(0x01, ha->bmic + EINTENABREG);
  1111. } else if (ha->type == GDT_ISA) {
  1112. dp2_ptr = ha->brd;
  1113. writeb(1, &dp2_ptr->io.irqdel);
  1114. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1115. writeb(1, &dp2_ptr->io.irqen);
  1116. } else if (ha->type == GDT_PCI) {
  1117. dp6_ptr = ha->brd;
  1118. writeb(1, &dp6_ptr->io.irqdel);
  1119. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1120. writeb(1, &dp6_ptr->io.irqen);
  1121. } else if (ha->type == GDT_PCINEW) {
  1122. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1123. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1124. } else if (ha->type == GDT_PCIMPR) {
  1125. dp6m_ptr = ha->brd;
  1126. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1127. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1128. &dp6m_ptr->i960r.edoor_en_reg);
  1129. }
  1130. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1131. }
  1132. /* return IStatus if interrupt was from this card else 0 */
  1133. static u8 gdth_get_status(gdth_ha_str *ha)
  1134. {
  1135. u8 IStatus = 0;
  1136. TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
  1137. if (ha->type == GDT_EISA)
  1138. IStatus = inb((u16)ha->bmic + EDOORREG);
  1139. else if (ha->type == GDT_ISA)
  1140. IStatus =
  1141. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1142. else if (ha->type == GDT_PCI)
  1143. IStatus =
  1144. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1145. else if (ha->type == GDT_PCINEW)
  1146. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1147. else if (ha->type == GDT_PCIMPR)
  1148. IStatus =
  1149. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1150. return IStatus;
  1151. }
  1152. static int gdth_test_busy(gdth_ha_str *ha)
  1153. {
  1154. register int gdtsema0 = 0;
  1155. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1156. if (ha->type == GDT_EISA)
  1157. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1158. else if (ha->type == GDT_ISA)
  1159. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1160. else if (ha->type == GDT_PCI)
  1161. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1162. else if (ha->type == GDT_PCINEW)
  1163. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1164. else if (ha->type == GDT_PCIMPR)
  1165. gdtsema0 =
  1166. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1167. return (gdtsema0 & 1);
  1168. }
  1169. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1170. {
  1171. int i;
  1172. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1173. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1174. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1175. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1176. ha->cmd_tab[i].service = ha->pccb->Service;
  1177. ha->pccb->CommandIndex = (u32)i+2;
  1178. return (i+2);
  1179. }
  1180. }
  1181. return 0;
  1182. }
  1183. static void gdth_set_sema0(gdth_ha_str *ha)
  1184. {
  1185. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1186. if (ha->type == GDT_EISA) {
  1187. outb(1, ha->bmic + SEMA0REG);
  1188. } else if (ha->type == GDT_ISA) {
  1189. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1190. } else if (ha->type == GDT_PCI) {
  1191. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1192. } else if (ha->type == GDT_PCINEW) {
  1193. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1194. } else if (ha->type == GDT_PCIMPR) {
  1195. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1196. }
  1197. }
  1198. static void gdth_copy_command(gdth_ha_str *ha)
  1199. {
  1200. register gdth_cmd_str *cmd_ptr;
  1201. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1202. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1203. gdt6_dpram_str __iomem *dp6_ptr;
  1204. gdt2_dpram_str __iomem *dp2_ptr;
  1205. u16 cp_count,dp_offset,cmd_no;
  1206. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1207. cp_count = ha->cmd_len;
  1208. dp_offset= ha->cmd_offs_dpmem;
  1209. cmd_no = ha->cmd_cnt;
  1210. cmd_ptr = ha->pccb;
  1211. ++ha->cmd_cnt;
  1212. if (ha->type == GDT_EISA)
  1213. return; /* no DPMEM, no copy */
  1214. /* set cpcount dword aligned */
  1215. if (cp_count & 3)
  1216. cp_count += (4 - (cp_count & 3));
  1217. ha->cmd_offs_dpmem += cp_count;
  1218. /* set offset and service, copy command to DPMEM */
  1219. if (ha->type == GDT_ISA) {
  1220. dp2_ptr = ha->brd;
  1221. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1222. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1223. writew((u16)cmd_ptr->Service,
  1224. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1225. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1226. } else if (ha->type == GDT_PCI) {
  1227. dp6_ptr = ha->brd;
  1228. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1229. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1230. writew((u16)cmd_ptr->Service,
  1231. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1232. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1233. } else if (ha->type == GDT_PCINEW) {
  1234. dp6c_ptr = ha->brd;
  1235. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1236. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1237. writew((u16)cmd_ptr->Service,
  1238. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1239. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1240. } else if (ha->type == GDT_PCIMPR) {
  1241. dp6m_ptr = ha->brd;
  1242. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1243. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1244. writew((u16)cmd_ptr->Service,
  1245. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1246. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1247. }
  1248. }
  1249. static void gdth_release_event(gdth_ha_str *ha)
  1250. {
  1251. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1252. #ifdef GDTH_STATISTICS
  1253. {
  1254. u32 i,j;
  1255. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1256. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1257. ++i;
  1258. }
  1259. if (max_index < i) {
  1260. max_index = i;
  1261. TRACE3(("GDT: max_index = %d\n",(u16)i));
  1262. }
  1263. }
  1264. #endif
  1265. if (ha->pccb->OpCode == GDT_INIT)
  1266. ha->pccb->Service |= 0x80;
  1267. if (ha->type == GDT_EISA) {
  1268. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1269. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1270. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1271. } else if (ha->type == GDT_ISA) {
  1272. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1273. } else if (ha->type == GDT_PCI) {
  1274. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1275. } else if (ha->type == GDT_PCINEW) {
  1276. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1277. } else if (ha->type == GDT_PCIMPR) {
  1278. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1279. }
  1280. }
  1281. static int gdth_wait(gdth_ha_str *ha, int index, u32 time)
  1282. {
  1283. int answer_found = FALSE;
  1284. int wait_index = 0;
  1285. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1286. if (index == 0)
  1287. return 1; /* no wait required */
  1288. do {
  1289. __gdth_interrupt(ha, true, &wait_index);
  1290. if (wait_index == index) {
  1291. answer_found = TRUE;
  1292. break;
  1293. }
  1294. gdth_delay(1);
  1295. } while (--time);
  1296. while (gdth_test_busy(ha))
  1297. gdth_delay(0);
  1298. return (answer_found);
  1299. }
  1300. static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
  1301. u32 p1, u64 p2, u64 p3)
  1302. {
  1303. register gdth_cmd_str *cmd_ptr;
  1304. int retries,index;
  1305. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1306. cmd_ptr = ha->pccb;
  1307. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1308. /* make command */
  1309. for (retries = INIT_RETRIES;;) {
  1310. cmd_ptr->Service = service;
  1311. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1312. if (!(index=gdth_get_cmd_index(ha))) {
  1313. TRACE(("GDT: No free command index found\n"));
  1314. return 0;
  1315. }
  1316. gdth_set_sema0(ha);
  1317. cmd_ptr->OpCode = opcode;
  1318. cmd_ptr->BoardNode = LOCALBOARD;
  1319. if (service == CACHESERVICE) {
  1320. if (opcode == GDT_IOCTL) {
  1321. cmd_ptr->u.ioctl.subfunc = p1;
  1322. cmd_ptr->u.ioctl.channel = (u32)p2;
  1323. cmd_ptr->u.ioctl.param_size = (u16)p3;
  1324. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1325. } else {
  1326. if (ha->cache_feat & GDT_64BIT) {
  1327. cmd_ptr->u.cache64.DeviceNo = (u16)p1;
  1328. cmd_ptr->u.cache64.BlockNo = p2;
  1329. } else {
  1330. cmd_ptr->u.cache.DeviceNo = (u16)p1;
  1331. cmd_ptr->u.cache.BlockNo = (u32)p2;
  1332. }
  1333. }
  1334. } else if (service == SCSIRAWSERVICE) {
  1335. if (ha->raw_feat & GDT_64BIT) {
  1336. cmd_ptr->u.raw64.direction = p1;
  1337. cmd_ptr->u.raw64.bus = (u8)p2;
  1338. cmd_ptr->u.raw64.target = (u8)p3;
  1339. cmd_ptr->u.raw64.lun = (u8)(p3 >> 8);
  1340. } else {
  1341. cmd_ptr->u.raw.direction = p1;
  1342. cmd_ptr->u.raw.bus = (u8)p2;
  1343. cmd_ptr->u.raw.target = (u8)p3;
  1344. cmd_ptr->u.raw.lun = (u8)(p3 >> 8);
  1345. }
  1346. } else if (service == SCREENSERVICE) {
  1347. if (opcode == GDT_REALTIME) {
  1348. *(u32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1349. *(u32 *)&cmd_ptr->u.screen.su.data[4] = (u32)p2;
  1350. *(u32 *)&cmd_ptr->u.screen.su.data[8] = (u32)p3;
  1351. }
  1352. }
  1353. ha->cmd_len = sizeof(gdth_cmd_str);
  1354. ha->cmd_offs_dpmem = 0;
  1355. ha->cmd_cnt = 0;
  1356. gdth_copy_command(ha);
  1357. gdth_release_event(ha);
  1358. gdth_delay(20);
  1359. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1360. printk("GDT: Initialization error (timeout service %d)\n",service);
  1361. return 0;
  1362. }
  1363. if (ha->status != S_BSY || --retries == 0)
  1364. break;
  1365. gdth_delay(1);
  1366. }
  1367. return (ha->status != S_OK ? 0:1);
  1368. }
  1369. /* search for devices */
  1370. static int gdth_search_drives(gdth_ha_str *ha)
  1371. {
  1372. u16 cdev_cnt, i;
  1373. int ok;
  1374. u32 bus_no, drv_cnt, drv_no, j;
  1375. gdth_getch_str *chn;
  1376. gdth_drlist_str *drl;
  1377. gdth_iochan_str *ioc;
  1378. gdth_raw_iochan_str *iocr;
  1379. gdth_arcdl_str *alst;
  1380. gdth_alist_str *alst2;
  1381. gdth_oem_str_ioctl *oemstr;
  1382. #ifdef INT_COAL
  1383. gdth_perf_modes *pmod;
  1384. #endif
  1385. #ifdef GDTH_RTC
  1386. u8 rtc[12];
  1387. unsigned long flags;
  1388. #endif
  1389. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1390. ok = 0;
  1391. /* initialize controller services, at first: screen service */
  1392. ha->screen_feat = 0;
  1393. if (!force_dma32) {
  1394. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1395. if (ok)
  1396. ha->screen_feat = GDT_64BIT;
  1397. }
  1398. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1399. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1400. if (!ok) {
  1401. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1402. ha->hanum, ha->status);
  1403. return 0;
  1404. }
  1405. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1406. #ifdef GDTH_RTC
  1407. /* read realtime clock info, send to controller */
  1408. /* 1. wait for the falling edge of update flag */
  1409. spin_lock_irqsave(&rtc_lock, flags);
  1410. for (j = 0; j < 1000000; ++j)
  1411. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1412. break;
  1413. for (j = 0; j < 1000000; ++j)
  1414. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1415. break;
  1416. /* 2. read info */
  1417. do {
  1418. for (j = 0; j < 12; ++j)
  1419. rtc[j] = CMOS_READ(j);
  1420. } while (rtc[0] != CMOS_READ(0));
  1421. spin_unlock_irqrestore(&rtc_lock, flags);
  1422. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(u32 *)&rtc[0],
  1423. *(u32 *)&rtc[4], *(u32 *)&rtc[8]));
  1424. /* 3. send to controller firmware */
  1425. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(u32 *)&rtc[0],
  1426. *(u32 *)&rtc[4], *(u32 *)&rtc[8]);
  1427. #endif
  1428. /* unfreeze all IOs */
  1429. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1430. /* initialize cache service */
  1431. ha->cache_feat = 0;
  1432. if (!force_dma32) {
  1433. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1434. 0, 0);
  1435. if (ok)
  1436. ha->cache_feat = GDT_64BIT;
  1437. }
  1438. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1439. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1440. if (!ok) {
  1441. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1442. ha->hanum, ha->status);
  1443. return 0;
  1444. }
  1445. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1446. cdev_cnt = (u16)ha->info;
  1447. ha->fw_vers = ha->service;
  1448. #ifdef INT_COAL
  1449. if (ha->type == GDT_PCIMPR) {
  1450. /* set perf. modes */
  1451. pmod = (gdth_perf_modes *)ha->pscratch;
  1452. pmod->version = 1;
  1453. pmod->st_mode = 1; /* enable one status buffer */
  1454. *((u64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1455. pmod->st_buff_indx1 = COALINDEX;
  1456. pmod->st_buff_addr2 = 0;
  1457. pmod->st_buff_u_addr2 = 0;
  1458. pmod->st_buff_indx2 = 0;
  1459. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1460. pmod->cmd_mode = 0; // disable all cmd buffers
  1461. pmod->cmd_buff_addr1 = 0;
  1462. pmod->cmd_buff_u_addr1 = 0;
  1463. pmod->cmd_buff_indx1 = 0;
  1464. pmod->cmd_buff_addr2 = 0;
  1465. pmod->cmd_buff_u_addr2 = 0;
  1466. pmod->cmd_buff_indx2 = 0;
  1467. pmod->cmd_buff_size = 0;
  1468. pmod->reserved1 = 0;
  1469. pmod->reserved2 = 0;
  1470. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1471. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1472. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1473. }
  1474. }
  1475. #endif
  1476. /* detect number of buses - try new IOCTL */
  1477. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1478. iocr->hdr.version = 0xffffffff;
  1479. iocr->hdr.list_entries = MAXBUS;
  1480. iocr->hdr.first_chan = 0;
  1481. iocr->hdr.last_chan = MAXBUS-1;
  1482. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1483. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1484. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1485. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1486. ha->bus_cnt = iocr->hdr.chan_count;
  1487. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1488. if (iocr->list[bus_no].proc_id < MAXID)
  1489. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1490. else
  1491. ha->bus_id[bus_no] = 0xff;
  1492. }
  1493. } else {
  1494. /* old method */
  1495. chn = (gdth_getch_str *)ha->pscratch;
  1496. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1497. chn->channel_no = bus_no;
  1498. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1499. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1500. IO_CHANNEL | INVALID_CHANNEL,
  1501. sizeof(gdth_getch_str))) {
  1502. if (bus_no == 0) {
  1503. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1504. ha->hanum, ha->status);
  1505. return 0;
  1506. }
  1507. break;
  1508. }
  1509. if (chn->siop_id < MAXID)
  1510. ha->bus_id[bus_no] = chn->siop_id;
  1511. else
  1512. ha->bus_id[bus_no] = 0xff;
  1513. }
  1514. ha->bus_cnt = (u8)bus_no;
  1515. }
  1516. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1517. /* read cache configuration */
  1518. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1519. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1520. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1521. ha->hanum, ha->status);
  1522. return 0;
  1523. }
  1524. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1525. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1526. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1527. ha->cpar.write_back,ha->cpar.block_size));
  1528. /* read board info and features */
  1529. ha->more_proc = FALSE;
  1530. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1531. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1532. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1533. sizeof(gdth_binfo_str));
  1534. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1535. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1536. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1537. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1538. ha->more_proc = TRUE;
  1539. }
  1540. } else {
  1541. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1542. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1543. }
  1544. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1545. /* read more informations */
  1546. if (ha->more_proc) {
  1547. /* physical drives, channel addresses */
  1548. ioc = (gdth_iochan_str *)ha->pscratch;
  1549. ioc->hdr.version = 0xffffffff;
  1550. ioc->hdr.list_entries = MAXBUS;
  1551. ioc->hdr.first_chan = 0;
  1552. ioc->hdr.last_chan = MAXBUS-1;
  1553. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1554. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1555. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1556. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1557. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1558. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1559. }
  1560. } else {
  1561. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1562. ha->raw[bus_no].address = IO_CHANNEL;
  1563. ha->raw[bus_no].local_no = bus_no;
  1564. }
  1565. }
  1566. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1567. chn = (gdth_getch_str *)ha->pscratch;
  1568. chn->channel_no = ha->raw[bus_no].local_no;
  1569. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1570. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1571. ha->raw[bus_no].address | INVALID_CHANNEL,
  1572. sizeof(gdth_getch_str))) {
  1573. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1574. TRACE2(("Channel %d: %d phys. drives\n",
  1575. bus_no,chn->drive_cnt));
  1576. }
  1577. if (ha->raw[bus_no].pdev_cnt > 0) {
  1578. drl = (gdth_drlist_str *)ha->pscratch;
  1579. drl->sc_no = ha->raw[bus_no].local_no;
  1580. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1581. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1582. SCSI_DR_LIST | L_CTRL_PATTERN,
  1583. ha->raw[bus_no].address | INVALID_CHANNEL,
  1584. sizeof(gdth_drlist_str))) {
  1585. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1586. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1587. } else {
  1588. ha->raw[bus_no].pdev_cnt = 0;
  1589. }
  1590. }
  1591. }
  1592. /* logical drives */
  1593. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1594. INVALID_CHANNEL,sizeof(u32))) {
  1595. drv_cnt = *(u32 *)ha->pscratch;
  1596. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1597. INVALID_CHANNEL,drv_cnt * sizeof(u32))) {
  1598. for (j = 0; j < drv_cnt; ++j) {
  1599. drv_no = ((u32 *)ha->pscratch)[j];
  1600. if (drv_no < MAX_LDRIVES) {
  1601. ha->hdr[drv_no].is_logdrv = TRUE;
  1602. TRACE2(("Drive %d is log. drive\n",drv_no));
  1603. }
  1604. }
  1605. }
  1606. alst = (gdth_arcdl_str *)ha->pscratch;
  1607. alst->entries_avail = MAX_LDRIVES;
  1608. alst->first_entry = 0;
  1609. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1610. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1611. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1612. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1613. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1614. for (j = 0; j < alst->entries_init; ++j) {
  1615. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1616. ha->hdr[j].is_master = alst->list[j].is_master;
  1617. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1618. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1619. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1620. }
  1621. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1622. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1623. 0, 35 * sizeof(gdth_alist_str))) {
  1624. for (j = 0; j < 35; ++j) {
  1625. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1626. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1627. ha->hdr[j].is_master = alst2->is_master;
  1628. ha->hdr[j].is_parity = alst2->is_parity;
  1629. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1630. ha->hdr[j].master_no = alst2->cd_handle;
  1631. }
  1632. }
  1633. }
  1634. }
  1635. /* initialize raw service */
  1636. ha->raw_feat = 0;
  1637. if (!force_dma32) {
  1638. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1639. if (ok)
  1640. ha->raw_feat = GDT_64BIT;
  1641. }
  1642. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1643. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1644. if (!ok) {
  1645. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1646. ha->hanum, ha->status);
  1647. return 0;
  1648. }
  1649. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1650. /* set/get features raw service (scatter/gather) */
  1651. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1652. 0, 0)) {
  1653. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1654. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1655. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1656. ha->info));
  1657. ha->raw_feat |= (u16)ha->info;
  1658. }
  1659. }
  1660. /* set/get features cache service (equal to raw service) */
  1661. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1662. SCATTER_GATHER,0)) {
  1663. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1664. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1665. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1666. ha->info));
  1667. ha->cache_feat |= (u16)ha->info;
  1668. }
  1669. }
  1670. /* reserve drives for raw service */
  1671. if (reserve_mode != 0) {
  1672. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1673. reserve_mode == 1 ? 1 : 3, 0, 0);
  1674. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1675. ha->status));
  1676. }
  1677. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1678. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1679. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1680. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1681. reserve_list[i], reserve_list[i+1],
  1682. reserve_list[i+2], reserve_list[i+3]));
  1683. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1684. reserve_list[i+1], reserve_list[i+2] |
  1685. (reserve_list[i+3] << 8))) {
  1686. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1687. ha->hanum, ha->status);
  1688. }
  1689. }
  1690. }
  1691. /* Determine OEM string using IOCTL */
  1692. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1693. oemstr->params.ctl_version = 0x01;
  1694. oemstr->params.buffer_size = sizeof(oemstr->text);
  1695. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1696. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1697. sizeof(gdth_oem_str_ioctl))) {
  1698. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1699. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1700. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1701. /* Save the Host Drive inquiry data */
  1702. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1703. sizeof(ha->oem_name));
  1704. } else {
  1705. /* Old method, based on PCI ID */
  1706. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1707. printk("GDT-HA %d: Name: %s\n",
  1708. ha->hanum, ha->binfo.type_string);
  1709. if (ha->oem_id == OEM_ID_INTEL)
  1710. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1711. else
  1712. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1713. }
  1714. /* scanning for host drives */
  1715. for (i = 0; i < cdev_cnt; ++i)
  1716. gdth_analyse_hdrive(ha, i);
  1717. TRACE(("gdth_search_drives() OK\n"));
  1718. return 1;
  1719. }
  1720. static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive)
  1721. {
  1722. u32 drv_cyls;
  1723. int drv_hds, drv_secs;
  1724. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1725. if (hdrive >= MAX_HDRIVES)
  1726. return 0;
  1727. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1728. return 0;
  1729. ha->hdr[hdrive].present = TRUE;
  1730. ha->hdr[hdrive].size = ha->info;
  1731. /* evaluate mapping (sectors per head, heads per cylinder) */
  1732. ha->hdr[hdrive].size &= ~SECS32;
  1733. if (ha->info2 == 0) {
  1734. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1735. } else {
  1736. drv_hds = ha->info2 & 0xff;
  1737. drv_secs = (ha->info2 >> 8) & 0xff;
  1738. drv_cyls = (u32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1739. }
  1740. ha->hdr[hdrive].heads = (u8)drv_hds;
  1741. ha->hdr[hdrive].secs = (u8)drv_secs;
  1742. /* round size */
  1743. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1744. if (ha->cache_feat & GDT_64BIT) {
  1745. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1746. && ha->info2 != 0) {
  1747. ha->hdr[hdrive].size = ((u64)ha->info2 << 32) | ha->info;
  1748. }
  1749. }
  1750. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1751. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1752. /* get informations about device */
  1753. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1754. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1755. hdrive,ha->info));
  1756. ha->hdr[hdrive].devtype = (u16)ha->info;
  1757. }
  1758. /* cluster info */
  1759. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1760. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1761. hdrive,ha->info));
  1762. if (!shared_access)
  1763. ha->hdr[hdrive].cluster_type = (u8)ha->info;
  1764. }
  1765. /* R/W attributes */
  1766. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1767. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1768. hdrive,ha->info));
  1769. ha->hdr[hdrive].rw_attribs = (u8)ha->info;
  1770. }
  1771. return 1;
  1772. }
  1773. /* command queueing/sending functions */
  1774. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority)
  1775. {
  1776. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1777. register Scsi_Cmnd *pscp;
  1778. register Scsi_Cmnd *nscp;
  1779. unsigned long flags;
  1780. TRACE(("gdth_putq() priority %d\n",priority));
  1781. spin_lock_irqsave(&ha->smp_lock, flags);
  1782. if (!cmndinfo->internal_command)
  1783. cmndinfo->priority = priority;
  1784. if (ha->req_first==NULL) {
  1785. ha->req_first = scp; /* queue was empty */
  1786. scp->SCp.ptr = NULL;
  1787. } else { /* queue not empty */
  1788. pscp = ha->req_first;
  1789. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1790. /* priority: 0-highest,..,0xff-lowest */
  1791. while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
  1792. pscp = nscp;
  1793. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1794. }
  1795. pscp->SCp.ptr = (char *)scp;
  1796. scp->SCp.ptr = (char *)nscp;
  1797. }
  1798. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1799. #ifdef GDTH_STATISTICS
  1800. flags = 0;
  1801. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1802. ++flags;
  1803. if (max_rq < flags) {
  1804. max_rq = flags;
  1805. TRACE3(("GDT: max_rq = %d\n",(u16)max_rq));
  1806. }
  1807. #endif
  1808. }
  1809. static void gdth_next(gdth_ha_str *ha)
  1810. {
  1811. register Scsi_Cmnd *pscp;
  1812. register Scsi_Cmnd *nscp;
  1813. u8 b, t, l, firsttime;
  1814. u8 this_cmd, next_cmd;
  1815. unsigned long flags = 0;
  1816. int cmd_index;
  1817. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1818. if (!gdth_polling)
  1819. spin_lock_irqsave(&ha->smp_lock, flags);
  1820. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1821. this_cmd = firsttime = TRUE;
  1822. next_cmd = gdth_polling ? FALSE:TRUE;
  1823. cmd_index = 0;
  1824. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1825. struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
  1826. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1827. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1828. if (!nscp_cmndinfo->internal_command) {
  1829. b = nscp->device->channel;
  1830. t = nscp->device->id;
  1831. l = nscp->device->lun;
  1832. if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
  1833. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1834. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1835. continue;
  1836. }
  1837. } else
  1838. b = t = l = 0;
  1839. if (firsttime) {
  1840. if (gdth_test_busy(ha)) { /* controller busy ? */
  1841. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1842. if (!gdth_polling) {
  1843. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1844. return;
  1845. }
  1846. while (gdth_test_busy(ha))
  1847. gdth_delay(1);
  1848. }
  1849. firsttime = FALSE;
  1850. }
  1851. if (!nscp_cmndinfo->internal_command) {
  1852. if (nscp_cmndinfo->phase == -1) {
  1853. nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
  1854. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1855. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1856. b, t, l));
  1857. /* TEST_UNIT_READY -> set scan mode */
  1858. if ((ha->scan_mode & 0x0f) == 0) {
  1859. if (b == 0 && t == 0 && l == 0) {
  1860. ha->scan_mode |= 1;
  1861. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1862. }
  1863. } else if ((ha->scan_mode & 0x0f) == 1) {
  1864. if (b == 0 && ((t == 0 && l == 1) ||
  1865. (t == 1 && l == 0))) {
  1866. nscp_cmndinfo->OpCode = GDT_SCAN_START;
  1867. nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1868. | SCSIRAWSERVICE;
  1869. ha->scan_mode = 0x12;
  1870. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1871. ha->scan_mode));
  1872. } else {
  1873. ha->scan_mode &= 0x10;
  1874. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1875. }
  1876. } else if (ha->scan_mode == 0x12) {
  1877. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1878. nscp_cmndinfo->phase = SCSIRAWSERVICE;
  1879. nscp_cmndinfo->OpCode = GDT_SCAN_END;
  1880. ha->scan_mode &= 0x10;
  1881. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1882. ha->scan_mode));
  1883. }
  1884. }
  1885. }
  1886. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1887. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1888. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1889. /* always GDT_CLUST_INFO! */
  1890. nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
  1891. }
  1892. }
  1893. }
  1894. if (nscp_cmndinfo->OpCode != -1) {
  1895. if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
  1896. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1897. this_cmd = FALSE;
  1898. next_cmd = FALSE;
  1899. } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
  1900. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1901. this_cmd = FALSE;
  1902. next_cmd = FALSE;
  1903. } else {
  1904. memset((char*)nscp->sense_buffer,0,16);
  1905. nscp->sense_buffer[0] = 0x70;
  1906. nscp->sense_buffer[2] = NOT_READY;
  1907. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1908. if (!nscp_cmndinfo->wait_for_completion)
  1909. nscp_cmndinfo->wait_for_completion++;
  1910. else
  1911. gdth_scsi_done(nscp);
  1912. }
  1913. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1914. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1915. this_cmd = FALSE;
  1916. next_cmd = FALSE;
  1917. } else if (b != ha->virt_bus) {
  1918. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1919. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1920. this_cmd = FALSE;
  1921. else
  1922. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1923. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1924. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1925. nscp->cmnd[0], b, t, l));
  1926. nscp->result = DID_BAD_TARGET << 16;
  1927. if (!nscp_cmndinfo->wait_for_completion)
  1928. nscp_cmndinfo->wait_for_completion++;
  1929. else
  1930. gdth_scsi_done(nscp);
  1931. } else {
  1932. switch (nscp->cmnd[0]) {
  1933. case TEST_UNIT_READY:
  1934. case INQUIRY:
  1935. case REQUEST_SENSE:
  1936. case READ_CAPACITY:
  1937. case VERIFY:
  1938. case START_STOP:
  1939. case MODE_SENSE:
  1940. case SERVICE_ACTION_IN_16:
  1941. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1942. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1943. nscp->cmnd[4],nscp->cmnd[5]));
  1944. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  1945. /* return UNIT_ATTENTION */
  1946. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1947. nscp->cmnd[0], t));
  1948. ha->hdr[t].media_changed = FALSE;
  1949. memset((char*)nscp->sense_buffer,0,16);
  1950. nscp->sense_buffer[0] = 0x70;
  1951. nscp->sense_buffer[2] = UNIT_ATTENTION;
  1952. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1953. if (!nscp_cmndinfo->wait_for_completion)
  1954. nscp_cmndinfo->wait_for_completion++;
  1955. else
  1956. gdth_scsi_done(nscp);
  1957. } else if (gdth_internal_cache_cmd(ha, nscp))
  1958. gdth_scsi_done(nscp);
  1959. break;
  1960. case ALLOW_MEDIUM_REMOVAL:
  1961. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1962. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1963. nscp->cmnd[4],nscp->cmnd[5]));
  1964. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  1965. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  1966. nscp->result = DID_OK << 16;
  1967. nscp->sense_buffer[0] = 0;
  1968. if (!nscp_cmndinfo->wait_for_completion)
  1969. nscp_cmndinfo->wait_for_completion++;
  1970. else
  1971. gdth_scsi_done(nscp);
  1972. } else {
  1973. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  1974. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  1975. nscp->cmnd[4],nscp->cmnd[3]));
  1976. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1977. this_cmd = FALSE;
  1978. }
  1979. break;
  1980. case RESERVE:
  1981. case RELEASE:
  1982. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  1983. "RESERVE" : "RELEASE"));
  1984. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1985. this_cmd = FALSE;
  1986. break;
  1987. case READ_6:
  1988. case WRITE_6:
  1989. case READ_10:
  1990. case WRITE_10:
  1991. case READ_16:
  1992. case WRITE_16:
  1993. if (ha->hdr[t].media_changed) {
  1994. /* return UNIT_ATTENTION */
  1995. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1996. nscp->cmnd[0], t));
  1997. ha->hdr[t].media_changed = FALSE;
  1998. memset((char*)nscp->sense_buffer,0,16);
  1999. nscp->sense_buffer[0] = 0x70;
  2000. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2001. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2002. if (!nscp_cmndinfo->wait_for_completion)
  2003. nscp_cmndinfo->wait_for_completion++;
  2004. else
  2005. gdth_scsi_done(nscp);
  2006. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2007. this_cmd = FALSE;
  2008. break;
  2009. default:
  2010. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2011. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2012. nscp->cmnd[4],nscp->cmnd[5]));
  2013. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2014. ha->hanum, nscp->cmnd[0]);
  2015. nscp->result = DID_ABORT << 16;
  2016. if (!nscp_cmndinfo->wait_for_completion)
  2017. nscp_cmndinfo->wait_for_completion++;
  2018. else
  2019. gdth_scsi_done(nscp);
  2020. break;
  2021. }
  2022. }
  2023. if (!this_cmd)
  2024. break;
  2025. if (nscp == ha->req_first)
  2026. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2027. else
  2028. pscp->SCp.ptr = nscp->SCp.ptr;
  2029. if (!next_cmd)
  2030. break;
  2031. }
  2032. if (ha->cmd_cnt > 0) {
  2033. gdth_release_event(ha);
  2034. }
  2035. if (!gdth_polling)
  2036. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2037. if (gdth_polling && ha->cmd_cnt > 0) {
  2038. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2039. printk("GDT-HA %d: Command %d timed out !\n",
  2040. ha->hanum, cmd_index);
  2041. }
  2042. }
  2043. /*
  2044. * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
  2045. * buffers, kmap_atomic() as needed.
  2046. */
  2047. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2048. char *buffer, u16 count)
  2049. {
  2050. u16 cpcount,i, max_sg = scsi_sg_count(scp);
  2051. u16 cpsum,cpnow;
  2052. struct scatterlist *sl;
  2053. char *address;
  2054. cpcount = min_t(u16, count, scsi_bufflen(scp));
  2055. if (cpcount) {
  2056. cpsum=0;
  2057. scsi_for_each_sg(scp, sl, max_sg, i) {
  2058. unsigned long flags;
  2059. cpnow = (u16)sl->length;
  2060. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2061. cpnow, cpsum, cpcount, scsi_bufflen(scp)));
  2062. if (cpsum+cpnow > cpcount)
  2063. cpnow = cpcount - cpsum;
  2064. cpsum += cpnow;
  2065. if (!sg_page(sl)) {
  2066. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2067. ha->hanum);
  2068. return;
  2069. }
  2070. local_irq_save(flags);
  2071. address = kmap_atomic(sg_page(sl)) + sl->offset;
  2072. memcpy(address, buffer, cpnow);
  2073. flush_dcache_page(sg_page(sl));
  2074. kunmap_atomic(address);
  2075. local_irq_restore(flags);
  2076. if (cpsum == cpcount)
  2077. break;
  2078. buffer += cpnow;
  2079. }
  2080. } else if (count) {
  2081. printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
  2082. ha->hanum);
  2083. WARN_ON(1);
  2084. }
  2085. }
  2086. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2087. {
  2088. u8 t;
  2089. gdth_inq_data inq;
  2090. gdth_rdcap_data rdc;
  2091. gdth_sense_data sd;
  2092. gdth_modep_data mpd;
  2093. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2094. t = scp->device->id;
  2095. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2096. scp->cmnd[0],t));
  2097. scp->result = DID_OK << 16;
  2098. scp->sense_buffer[0] = 0;
  2099. switch (scp->cmnd[0]) {
  2100. case TEST_UNIT_READY:
  2101. case VERIFY:
  2102. case START_STOP:
  2103. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2104. break;
  2105. case INQUIRY:
  2106. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2107. t,ha->hdr[t].devtype));
  2108. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2109. /* you can here set all disks to removable, if you want to do
  2110. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2111. inq.modif_rmb = 0x00;
  2112. if ((ha->hdr[t].devtype & 1) ||
  2113. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2114. inq.modif_rmb = 0x80;
  2115. inq.version = 2;
  2116. inq.resp_aenc = 2;
  2117. inq.add_length= 32;
  2118. strcpy(inq.vendor,ha->oem_name);
  2119. sprintf(inq.product,"Host Drive #%02d",t);
  2120. strcpy(inq.revision," ");
  2121. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
  2122. break;
  2123. case REQUEST_SENSE:
  2124. TRACE2(("Request sense hdrive %d\n",t));
  2125. sd.errorcode = 0x70;
  2126. sd.segno = 0x00;
  2127. sd.key = NO_SENSE;
  2128. sd.info = 0;
  2129. sd.add_length= 0;
  2130. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
  2131. break;
  2132. case MODE_SENSE:
  2133. TRACE2(("Mode sense hdrive %d\n",t));
  2134. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2135. mpd.hd.data_length = sizeof(gdth_modep_data);
  2136. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2137. mpd.hd.bd_length = sizeof(mpd.bd);
  2138. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2139. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2140. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2141. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
  2142. break;
  2143. case READ_CAPACITY:
  2144. TRACE2(("Read capacity hdrive %d\n",t));
  2145. if (ha->hdr[t].size > (u64)0xffffffff)
  2146. rdc.last_block_no = 0xffffffff;
  2147. else
  2148. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2149. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2150. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
  2151. break;
  2152. case SERVICE_ACTION_IN_16:
  2153. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2154. (ha->cache_feat & GDT_64BIT)) {
  2155. gdth_rdcap16_data rdc16;
  2156. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2157. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2158. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2159. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2160. sizeof(gdth_rdcap16_data));
  2161. } else {
  2162. scp->result = DID_ABORT << 16;
  2163. }
  2164. break;
  2165. default:
  2166. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2167. break;
  2168. }
  2169. if (!cmndinfo->wait_for_completion)
  2170. cmndinfo->wait_for_completion++;
  2171. else
  2172. return 1;
  2173. return 0;
  2174. }
  2175. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive)
  2176. {
  2177. register gdth_cmd_str *cmdp;
  2178. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2179. u32 cnt, blockcnt;
  2180. u64 no, blockno;
  2181. int i, cmd_index, read_write, sgcnt, mode64;
  2182. cmdp = ha->pccb;
  2183. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2184. scp->cmnd[0],scp->cmd_len,hdrive));
  2185. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2186. return 0;
  2187. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2188. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2189. not required, should not occur due to error return on
  2190. READ_CAPACITY_16 */
  2191. cmdp->Service = CACHESERVICE;
  2192. cmdp->RequestBuffer = scp;
  2193. /* search free command index */
  2194. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2195. TRACE(("GDT: No free command index found\n"));
  2196. return 0;
  2197. }
  2198. /* if it's the first command, set command semaphore */
  2199. if (ha->cmd_cnt == 0)
  2200. gdth_set_sema0(ha);
  2201. /* fill command */
  2202. read_write = 0;
  2203. if (cmndinfo->OpCode != -1)
  2204. cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
  2205. else if (scp->cmnd[0] == RESERVE)
  2206. cmdp->OpCode = GDT_RESERVE_DRV;
  2207. else if (scp->cmnd[0] == RELEASE)
  2208. cmdp->OpCode = GDT_RELEASE_DRV;
  2209. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2210. if (scp->cmnd[4] & 1) /* prevent ? */
  2211. cmdp->OpCode = GDT_MOUNT;
  2212. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2213. cmdp->OpCode = GDT_UNMOUNT;
  2214. else
  2215. cmdp->OpCode = GDT_FLUSH;
  2216. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2217. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2218. ) {
  2219. read_write = 1;
  2220. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2221. (ha->cache_feat & GDT_WR_THROUGH)))
  2222. cmdp->OpCode = GDT_WRITE_THR;
  2223. else
  2224. cmdp->OpCode = GDT_WRITE;
  2225. } else {
  2226. read_write = 2;
  2227. cmdp->OpCode = GDT_READ;
  2228. }
  2229. cmdp->BoardNode = LOCALBOARD;
  2230. if (mode64) {
  2231. cmdp->u.cache64.DeviceNo = hdrive;
  2232. cmdp->u.cache64.BlockNo = 1;
  2233. cmdp->u.cache64.sg_canz = 0;
  2234. } else {
  2235. cmdp->u.cache.DeviceNo = hdrive;
  2236. cmdp->u.cache.BlockNo = 1;
  2237. cmdp->u.cache.sg_canz = 0;
  2238. }
  2239. if (read_write) {
  2240. if (scp->cmd_len == 16) {
  2241. memcpy(&no, &scp->cmnd[2], sizeof(u64));
  2242. blockno = be64_to_cpu(no);
  2243. memcpy(&cnt, &scp->cmnd[10], sizeof(u32));
  2244. blockcnt = be32_to_cpu(cnt);
  2245. } else if (scp->cmd_len == 10) {
  2246. memcpy(&no, &scp->cmnd[2], sizeof(u32));
  2247. blockno = be32_to_cpu(no);
  2248. memcpy(&cnt, &scp->cmnd[7], sizeof(u16));
  2249. blockcnt = be16_to_cpu(cnt);
  2250. } else {
  2251. memcpy(&no, &scp->cmnd[0], sizeof(u32));
  2252. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2253. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2254. }
  2255. if (mode64) {
  2256. cmdp->u.cache64.BlockNo = blockno;
  2257. cmdp->u.cache64.BlockCnt = blockcnt;
  2258. } else {
  2259. cmdp->u.cache.BlockNo = (u32)blockno;
  2260. cmdp->u.cache.BlockCnt = blockcnt;
  2261. }
  2262. if (scsi_bufflen(scp)) {
  2263. cmndinfo->dma_dir = (read_write == 1 ?
  2264. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2265. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2266. cmndinfo->dma_dir);
  2267. if (mode64) {
  2268. struct scatterlist *sl;
  2269. cmdp->u.cache64.DestAddr= (u64)-1;
  2270. cmdp->u.cache64.sg_canz = sgcnt;
  2271. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2272. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2273. #ifdef GDTH_DMA_STATISTICS
  2274. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (u64)0xffffffff)
  2275. ha->dma64_cnt++;
  2276. else
  2277. ha->dma32_cnt++;
  2278. #endif
  2279. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2280. }
  2281. } else {
  2282. struct scatterlist *sl;
  2283. cmdp->u.cache.DestAddr= 0xffffffff;
  2284. cmdp->u.cache.sg_canz = sgcnt;
  2285. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2286. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2287. #ifdef GDTH_DMA_STATISTICS
  2288. ha->dma32_cnt++;
  2289. #endif
  2290. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2291. }
  2292. }
  2293. #ifdef GDTH_STATISTICS
  2294. if (max_sg < (u32)sgcnt) {
  2295. max_sg = (u32)sgcnt;
  2296. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2297. }
  2298. #endif
  2299. }
  2300. }
  2301. /* evaluate command size, check space */
  2302. if (mode64) {
  2303. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2304. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2305. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2306. cmdp->u.cache64.sg_lst[0].sg_len));
  2307. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2308. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2309. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2310. (u16)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2311. } else {
  2312. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2313. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2314. cmdp->u.cache.sg_lst[0].sg_ptr,
  2315. cmdp->u.cache.sg_lst[0].sg_len));
  2316. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2317. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2318. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2319. (u16)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2320. }
  2321. if (ha->cmd_len & 3)
  2322. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2323. if (ha->cmd_cnt > 0) {
  2324. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2325. ha->ic_all_size) {
  2326. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2327. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2328. return 0;
  2329. }
  2330. }
  2331. /* copy command */
  2332. gdth_copy_command(ha);
  2333. return cmd_index;
  2334. }
  2335. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b)
  2336. {
  2337. register gdth_cmd_str *cmdp;
  2338. u16 i;
  2339. dma_addr_t sense_paddr;
  2340. int cmd_index, sgcnt, mode64;
  2341. u8 t,l;
  2342. struct page *page;
  2343. unsigned long offset;
  2344. struct gdth_cmndinfo *cmndinfo;
  2345. t = scp->device->id;
  2346. l = scp->device->lun;
  2347. cmdp = ha->pccb;
  2348. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2349. scp->cmnd[0],b,t,l));
  2350. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2351. return 0;
  2352. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2353. cmdp->Service = SCSIRAWSERVICE;
  2354. cmdp->RequestBuffer = scp;
  2355. /* search free command index */
  2356. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2357. TRACE(("GDT: No free command index found\n"));
  2358. return 0;
  2359. }
  2360. /* if it's the first command, set command semaphore */
  2361. if (ha->cmd_cnt == 0)
  2362. gdth_set_sema0(ha);
  2363. cmndinfo = gdth_cmnd_priv(scp);
  2364. /* fill command */
  2365. if (cmndinfo->OpCode != -1) {
  2366. cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
  2367. cmdp->BoardNode = LOCALBOARD;
  2368. if (mode64) {
  2369. cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
  2370. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2371. cmdp->OpCode, cmdp->u.raw64.direction));
  2372. /* evaluate command size */
  2373. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2374. } else {
  2375. cmdp->u.raw.direction = (cmndinfo->phase >> 8);
  2376. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2377. cmdp->OpCode, cmdp->u.raw.direction));
  2378. /* evaluate command size */
  2379. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2380. }
  2381. } else {
  2382. page = virt_to_page(scp->sense_buffer);
  2383. offset = (unsigned long)scp->sense_buffer & ~PAGE_MASK;
  2384. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2385. 16,PCI_DMA_FROMDEVICE);
  2386. cmndinfo->sense_paddr = sense_paddr;
  2387. cmdp->OpCode = GDT_WRITE; /* always */
  2388. cmdp->BoardNode = LOCALBOARD;
  2389. if (mode64) {
  2390. cmdp->u.raw64.reserved = 0;
  2391. cmdp->u.raw64.mdisc_time = 0;
  2392. cmdp->u.raw64.mcon_time = 0;
  2393. cmdp->u.raw64.clen = scp->cmd_len;
  2394. cmdp->u.raw64.target = t;
  2395. cmdp->u.raw64.lun = l;
  2396. cmdp->u.raw64.bus = b;
  2397. cmdp->u.raw64.priority = 0;
  2398. cmdp->u.raw64.sdlen = scsi_bufflen(scp);
  2399. cmdp->u.raw64.sense_len = 16;
  2400. cmdp->u.raw64.sense_data = sense_paddr;
  2401. cmdp->u.raw64.direction =
  2402. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2403. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2404. cmdp->u.raw64.sg_ranz = 0;
  2405. } else {
  2406. cmdp->u.raw.reserved = 0;
  2407. cmdp->u.raw.mdisc_time = 0;
  2408. cmdp->u.raw.mcon_time = 0;
  2409. cmdp->u.raw.clen = scp->cmd_len;
  2410. cmdp->u.raw.target = t;
  2411. cmdp->u.raw.lun = l;
  2412. cmdp->u.raw.bus = b;
  2413. cmdp->u.raw.priority = 0;
  2414. cmdp->u.raw.link_p = 0;
  2415. cmdp->u.raw.sdlen = scsi_bufflen(scp);
  2416. cmdp->u.raw.sense_len = 16;
  2417. cmdp->u.raw.sense_data = sense_paddr;
  2418. cmdp->u.raw.direction =
  2419. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2420. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2421. cmdp->u.raw.sg_ranz = 0;
  2422. }
  2423. if (scsi_bufflen(scp)) {
  2424. cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
  2425. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2426. cmndinfo->dma_dir);
  2427. if (mode64) {
  2428. struct scatterlist *sl;
  2429. cmdp->u.raw64.sdata = (u64)-1;
  2430. cmdp->u.raw64.sg_ranz = sgcnt;
  2431. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2432. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2433. #ifdef GDTH_DMA_STATISTICS
  2434. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (u64)0xffffffff)
  2435. ha->dma64_cnt++;
  2436. else
  2437. ha->dma32_cnt++;
  2438. #endif
  2439. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2440. }
  2441. } else {
  2442. struct scatterlist *sl;
  2443. cmdp->u.raw.sdata = 0xffffffff;
  2444. cmdp->u.raw.sg_ranz = sgcnt;
  2445. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2446. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2447. #ifdef GDTH_DMA_STATISTICS
  2448. ha->dma32_cnt++;
  2449. #endif
  2450. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2451. }
  2452. }
  2453. #ifdef GDTH_STATISTICS
  2454. if (max_sg < sgcnt) {
  2455. max_sg = sgcnt;
  2456. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2457. }
  2458. #endif
  2459. }
  2460. if (mode64) {
  2461. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2462. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2463. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2464. cmdp->u.raw64.sg_lst[0].sg_len));
  2465. /* evaluate command size */
  2466. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2467. (u16)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2468. } else {
  2469. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2470. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2471. cmdp->u.raw.sg_lst[0].sg_ptr,
  2472. cmdp->u.raw.sg_lst[0].sg_len));
  2473. /* evaluate command size */
  2474. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2475. (u16)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2476. }
  2477. }
  2478. /* check space */
  2479. if (ha->cmd_len & 3)
  2480. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2481. if (ha->cmd_cnt > 0) {
  2482. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2483. ha->ic_all_size) {
  2484. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2485. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2486. return 0;
  2487. }
  2488. }
  2489. /* copy command */
  2490. gdth_copy_command(ha);
  2491. return cmd_index;
  2492. }
  2493. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2494. {
  2495. register gdth_cmd_str *cmdp;
  2496. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2497. int cmd_index;
  2498. cmdp= ha->pccb;
  2499. TRACE2(("gdth_special_cmd(): "));
  2500. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2501. return 0;
  2502. *cmdp = *cmndinfo->internal_cmd_str;
  2503. cmdp->RequestBuffer = scp;
  2504. /* search free command index */
  2505. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2506. TRACE(("GDT: No free command index found\n"));
  2507. return 0;
  2508. }
  2509. /* if it's the first command, set command semaphore */
  2510. if (ha->cmd_cnt == 0)
  2511. gdth_set_sema0(ha);
  2512. /* evaluate command size, check space */
  2513. if (cmdp->OpCode == GDT_IOCTL) {
  2514. TRACE2(("IOCTL\n"));
  2515. ha->cmd_len =
  2516. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(u64);
  2517. } else if (cmdp->Service == CACHESERVICE) {
  2518. TRACE2(("cache command %d\n",cmdp->OpCode));
  2519. if (ha->cache_feat & GDT_64BIT)
  2520. ha->cmd_len =
  2521. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2522. else
  2523. ha->cmd_len =
  2524. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2525. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2526. TRACE2(("raw command %d\n",cmdp->OpCode));
  2527. if (ha->raw_feat & GDT_64BIT)
  2528. ha->cmd_len =
  2529. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2530. else
  2531. ha->cmd_len =
  2532. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2533. }
  2534. if (ha->cmd_len & 3)
  2535. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2536. if (ha->cmd_cnt > 0) {
  2537. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2538. ha->ic_all_size) {
  2539. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2540. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2541. return 0;
  2542. }
  2543. }
  2544. /* copy command */
  2545. gdth_copy_command(ha);
  2546. return cmd_index;
  2547. }
  2548. /* Controller event handling functions */
  2549. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
  2550. u16 idx, gdth_evt_data *evt)
  2551. {
  2552. gdth_evt_str *e;
  2553. /* no GDTH_LOCK_HA() ! */
  2554. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2555. if (source == 0) /* no source -> no event */
  2556. return NULL;
  2557. if (ebuffer[elastidx].event_source == source &&
  2558. ebuffer[elastidx].event_idx == idx &&
  2559. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2560. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2561. (char *)&evt->eu, evt->size)) ||
  2562. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2563. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2564. (char *)&evt->event_string)))) {
  2565. e = &ebuffer[elastidx];
  2566. e->last_stamp = (u32)ktime_get_real_seconds();
  2567. ++e->same_count;
  2568. } else {
  2569. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2570. ++elastidx;
  2571. if (elastidx == MAX_EVENTS)
  2572. elastidx = 0;
  2573. if (elastidx == eoldidx) { /* reached mark ? */
  2574. ++eoldidx;
  2575. if (eoldidx == MAX_EVENTS)
  2576. eoldidx = 0;
  2577. }
  2578. }
  2579. e = &ebuffer[elastidx];
  2580. e->event_source = source;
  2581. e->event_idx = idx;
  2582. e->first_stamp = e->last_stamp = (u32)ktime_get_real_seconds();
  2583. e->same_count = 1;
  2584. e->event_data = *evt;
  2585. e->application = 0;
  2586. }
  2587. return e;
  2588. }
  2589. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2590. {
  2591. gdth_evt_str *e;
  2592. int eindex;
  2593. unsigned long flags;
  2594. TRACE2(("gdth_read_event() handle %d\n", handle));
  2595. spin_lock_irqsave(&ha->smp_lock, flags);
  2596. if (handle == -1)
  2597. eindex = eoldidx;
  2598. else
  2599. eindex = handle;
  2600. estr->event_source = 0;
  2601. if (eindex < 0 || eindex >= MAX_EVENTS) {
  2602. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2603. return eindex;
  2604. }
  2605. e = &ebuffer[eindex];
  2606. if (e->event_source != 0) {
  2607. if (eindex != elastidx) {
  2608. if (++eindex == MAX_EVENTS)
  2609. eindex = 0;
  2610. } else {
  2611. eindex = -1;
  2612. }
  2613. memcpy(estr, e, sizeof(gdth_evt_str));
  2614. }
  2615. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2616. return eindex;
  2617. }
  2618. static void gdth_readapp_event(gdth_ha_str *ha,
  2619. u8 application, gdth_evt_str *estr)
  2620. {
  2621. gdth_evt_str *e;
  2622. int eindex;
  2623. unsigned long flags;
  2624. u8 found = FALSE;
  2625. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2626. spin_lock_irqsave(&ha->smp_lock, flags);
  2627. eindex = eoldidx;
  2628. for (;;) {
  2629. e = &ebuffer[eindex];
  2630. if (e->event_source == 0)
  2631. break;
  2632. if ((e->application & application) == 0) {
  2633. e->application |= application;
  2634. found = TRUE;
  2635. break;
  2636. }
  2637. if (eindex == elastidx)
  2638. break;
  2639. if (++eindex == MAX_EVENTS)
  2640. eindex = 0;
  2641. }
  2642. if (found)
  2643. memcpy(estr, e, sizeof(gdth_evt_str));
  2644. else
  2645. estr->event_source = 0;
  2646. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2647. }
  2648. static void gdth_clear_events(void)
  2649. {
  2650. TRACE(("gdth_clear_events()"));
  2651. eoldidx = elastidx = 0;
  2652. ebuffer[0].event_source = 0;
  2653. }
  2654. /* SCSI interface functions */
  2655. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  2656. int gdth_from_wait, int* pIndex)
  2657. {
  2658. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2659. gdt6_dpram_str __iomem *dp6_ptr;
  2660. gdt2_dpram_str __iomem *dp2_ptr;
  2661. Scsi_Cmnd *scp;
  2662. int rval, i;
  2663. u8 IStatus;
  2664. u16 Service;
  2665. unsigned long flags = 0;
  2666. #ifdef INT_COAL
  2667. int coalesced = FALSE;
  2668. int next = FALSE;
  2669. gdth_coal_status *pcs = NULL;
  2670. int act_int_coal = 0;
  2671. #endif
  2672. TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
  2673. /* if polling and not from gdth_wait() -> return */
  2674. if (gdth_polling) {
  2675. if (!gdth_from_wait) {
  2676. return IRQ_HANDLED;
  2677. }
  2678. }
  2679. if (!gdth_polling)
  2680. spin_lock_irqsave(&ha->smp_lock, flags);
  2681. /* search controller */
  2682. IStatus = gdth_get_status(ha);
  2683. if (IStatus == 0) {
  2684. /* spurious interrupt */
  2685. if (!gdth_polling)
  2686. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2687. return IRQ_HANDLED;
  2688. }
  2689. #ifdef GDTH_STATISTICS
  2690. ++act_ints;
  2691. #endif
  2692. #ifdef INT_COAL
  2693. /* See if the fw is returning coalesced status */
  2694. if (IStatus == COALINDEX) {
  2695. /* Coalesced status. Setup the initial status
  2696. buffer pointer and flags */
  2697. pcs = ha->coal_stat;
  2698. coalesced = TRUE;
  2699. next = TRUE;
  2700. }
  2701. do {
  2702. if (coalesced) {
  2703. /* For coalesced requests all status
  2704. information is found in the status buffer */
  2705. IStatus = (u8)(pcs->status & 0xff);
  2706. }
  2707. #endif
  2708. if (ha->type == GDT_EISA) {
  2709. if (IStatus & 0x80) { /* error flag */
  2710. IStatus &= ~0x80;
  2711. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2712. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2713. } else /* no error */
  2714. ha->status = S_OK;
  2715. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2716. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2717. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2718. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2719. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2720. } else if (ha->type == GDT_ISA) {
  2721. dp2_ptr = ha->brd;
  2722. if (IStatus & 0x80) { /* error flag */
  2723. IStatus &= ~0x80;
  2724. ha->status = readw(&dp2_ptr->u.ic.Status);
  2725. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2726. } else /* no error */
  2727. ha->status = S_OK;
  2728. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2729. ha->service = readw(&dp2_ptr->u.ic.Service);
  2730. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2731. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2732. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2733. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2734. } else if (ha->type == GDT_PCI) {
  2735. dp6_ptr = ha->brd;
  2736. if (IStatus & 0x80) { /* error flag */
  2737. IStatus &= ~0x80;
  2738. ha->status = readw(&dp6_ptr->u.ic.Status);
  2739. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2740. } else /* no error */
  2741. ha->status = S_OK;
  2742. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2743. ha->service = readw(&dp6_ptr->u.ic.Service);
  2744. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2745. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2746. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2747. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2748. } else if (ha->type == GDT_PCINEW) {
  2749. if (IStatus & 0x80) { /* error flag */
  2750. IStatus &= ~0x80;
  2751. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2752. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2753. } else
  2754. ha->status = S_OK;
  2755. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2756. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2757. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2758. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2759. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2760. } else if (ha->type == GDT_PCIMPR) {
  2761. dp6m_ptr = ha->brd;
  2762. if (IStatus & 0x80) { /* error flag */
  2763. IStatus &= ~0x80;
  2764. #ifdef INT_COAL
  2765. if (coalesced)
  2766. ha->status = pcs->ext_status & 0xffff;
  2767. else
  2768. #endif
  2769. ha->status = readw(&dp6m_ptr->i960r.status);
  2770. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2771. } else /* no error */
  2772. ha->status = S_OK;
  2773. #ifdef INT_COAL
  2774. /* get information */
  2775. if (coalesced) {
  2776. ha->info = pcs->info0;
  2777. ha->info2 = pcs->info1;
  2778. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2779. } else
  2780. #endif
  2781. {
  2782. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2783. ha->service = readw(&dp6m_ptr->i960r.service);
  2784. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2785. }
  2786. /* event string */
  2787. if (IStatus == ASYNCINDEX) {
  2788. if (ha->service != SCREENSERVICE &&
  2789. (ha->fw_vers & 0xff) >= 0x1a) {
  2790. ha->dvr.severity = readb
  2791. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2792. for (i = 0; i < 256; ++i) {
  2793. ha->dvr.event_string[i] = readb
  2794. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2795. if (ha->dvr.event_string[i] == 0)
  2796. break;
  2797. }
  2798. }
  2799. }
  2800. #ifdef INT_COAL
  2801. /* Make sure that non coalesced interrupts get cleared
  2802. before being handled by gdth_async_event/gdth_sync_event */
  2803. if (!coalesced)
  2804. #endif
  2805. {
  2806. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2807. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2808. }
  2809. } else {
  2810. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2811. if (!gdth_polling)
  2812. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2813. return IRQ_HANDLED;
  2814. }
  2815. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2816. IStatus,ha->status,ha->info));
  2817. if (gdth_from_wait) {
  2818. *pIndex = (int)IStatus;
  2819. }
  2820. if (IStatus == ASYNCINDEX) {
  2821. TRACE2(("gdth_interrupt() async. event\n"));
  2822. gdth_async_event(ha);
  2823. if (!gdth_polling)
  2824. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2825. gdth_next(ha);
  2826. return IRQ_HANDLED;
  2827. }
  2828. if (IStatus == SPEZINDEX) {
  2829. TRACE2(("Service unknown or not initialized !\n"));
  2830. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2831. ha->dvr.eu.driver.ionode = ha->hanum;
  2832. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2833. if (!gdth_polling)
  2834. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2835. return IRQ_HANDLED;
  2836. }
  2837. scp = ha->cmd_tab[IStatus-2].cmnd;
  2838. Service = ha->cmd_tab[IStatus-2].service;
  2839. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2840. if (scp == UNUSED_CMND) {
  2841. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2842. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2843. ha->dvr.eu.driver.ionode = ha->hanum;
  2844. ha->dvr.eu.driver.index = IStatus;
  2845. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2846. if (!gdth_polling)
  2847. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2848. return IRQ_HANDLED;
  2849. }
  2850. if (scp == INTERNAL_CMND) {
  2851. TRACE(("gdth_interrupt() answer to internal command\n"));
  2852. if (!gdth_polling)
  2853. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2854. return IRQ_HANDLED;
  2855. }
  2856. TRACE(("gdth_interrupt() sync. status\n"));
  2857. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2858. if (!gdth_polling)
  2859. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2860. if (rval == 2) {
  2861. gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
  2862. } else if (rval == 1) {
  2863. gdth_scsi_done(scp);
  2864. }
  2865. #ifdef INT_COAL
  2866. if (coalesced) {
  2867. /* go to the next status in the status buffer */
  2868. ++pcs;
  2869. #ifdef GDTH_STATISTICS
  2870. ++act_int_coal;
  2871. if (act_int_coal > max_int_coal) {
  2872. max_int_coal = act_int_coal;
  2873. printk("GDT: max_int_coal = %d\n",(u16)max_int_coal);
  2874. }
  2875. #endif
  2876. /* see if there is another status */
  2877. if (pcs->status == 0)
  2878. /* Stop the coalesce loop */
  2879. next = FALSE;
  2880. }
  2881. } while (next);
  2882. /* coalescing only for new GDT_PCIMPR controllers available */
  2883. if (ha->type == GDT_PCIMPR && coalesced) {
  2884. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2885. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2886. }
  2887. #endif
  2888. gdth_next(ha);
  2889. return IRQ_HANDLED;
  2890. }
  2891. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2892. {
  2893. gdth_ha_str *ha = dev_id;
  2894. return __gdth_interrupt(ha, false, NULL);
  2895. }
  2896. static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
  2897. Scsi_Cmnd *scp)
  2898. {
  2899. gdth_msg_str *msg;
  2900. gdth_cmd_str *cmdp;
  2901. u8 b, t;
  2902. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2903. cmdp = ha->pccb;
  2904. TRACE(("gdth_sync_event() serv %d status %d\n",
  2905. service,ha->status));
  2906. if (service == SCREENSERVICE) {
  2907. msg = ha->pmsg;
  2908. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2909. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2910. if (msg->msg_len > MSGLEN+1)
  2911. msg->msg_len = MSGLEN+1;
  2912. if (msg->msg_len)
  2913. if (!(msg->msg_answer && msg->msg_ext)) {
  2914. msg->msg_text[msg->msg_len] = '\0';
  2915. printk("%s",msg->msg_text);
  2916. }
  2917. if (msg->msg_ext && !msg->msg_answer) {
  2918. while (gdth_test_busy(ha))
  2919. gdth_delay(0);
  2920. cmdp->Service = SCREENSERVICE;
  2921. cmdp->RequestBuffer = SCREEN_CMND;
  2922. gdth_get_cmd_index(ha);
  2923. gdth_set_sema0(ha);
  2924. cmdp->OpCode = GDT_READ;
  2925. cmdp->BoardNode = LOCALBOARD;
  2926. cmdp->u.screen.reserved = 0;
  2927. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2928. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2929. ha->cmd_offs_dpmem = 0;
  2930. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2931. + sizeof(u64);
  2932. ha->cmd_cnt = 0;
  2933. gdth_copy_command(ha);
  2934. gdth_release_event(ha);
  2935. return 0;
  2936. }
  2937. if (msg->msg_answer && msg->msg_alen) {
  2938. /* default answers (getchar() not possible) */
  2939. if (msg->msg_alen == 1) {
  2940. msg->msg_alen = 0;
  2941. msg->msg_len = 1;
  2942. msg->msg_text[0] = 0;
  2943. } else {
  2944. msg->msg_alen -= 2;
  2945. msg->msg_len = 2;
  2946. msg->msg_text[0] = 1;
  2947. msg->msg_text[1] = 0;
  2948. }
  2949. msg->msg_ext = 0;
  2950. msg->msg_answer = 0;
  2951. while (gdth_test_busy(ha))
  2952. gdth_delay(0);
  2953. cmdp->Service = SCREENSERVICE;
  2954. cmdp->RequestBuffer = SCREEN_CMND;
  2955. gdth_get_cmd_index(ha);
  2956. gdth_set_sema0(ha);
  2957. cmdp->OpCode = GDT_WRITE;
  2958. cmdp->BoardNode = LOCALBOARD;
  2959. cmdp->u.screen.reserved = 0;
  2960. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2961. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2962. ha->cmd_offs_dpmem = 0;
  2963. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2964. + sizeof(u64);
  2965. ha->cmd_cnt = 0;
  2966. gdth_copy_command(ha);
  2967. gdth_release_event(ha);
  2968. return 0;
  2969. }
  2970. printk("\n");
  2971. } else {
  2972. b = scp->device->channel;
  2973. t = scp->device->id;
  2974. if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
  2975. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  2976. }
  2977. /* cache or raw service */
  2978. if (ha->status == S_BSY) {
  2979. TRACE2(("Controller busy -> retry !\n"));
  2980. if (cmndinfo->OpCode == GDT_MOUNT)
  2981. cmndinfo->OpCode = GDT_CLUST_INFO;
  2982. /* retry */
  2983. return 2;
  2984. }
  2985. if (scsi_bufflen(scp))
  2986. pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2987. cmndinfo->dma_dir);
  2988. if (cmndinfo->sense_paddr)
  2989. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  2990. PCI_DMA_FROMDEVICE);
  2991. if (ha->status == S_OK) {
  2992. cmndinfo->status = S_OK;
  2993. cmndinfo->info = ha->info;
  2994. if (cmndinfo->OpCode != -1) {
  2995. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  2996. cmndinfo->OpCode));
  2997. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  2998. if (cmndinfo->OpCode == GDT_CLUST_INFO) {
  2999. ha->hdr[t].cluster_type = (u8)ha->info;
  3000. if (!(ha->hdr[t].cluster_type &
  3001. CLUSTER_MOUNTED)) {
  3002. /* NOT MOUNTED -> MOUNT */
  3003. cmndinfo->OpCode = GDT_MOUNT;
  3004. if (ha->hdr[t].cluster_type &
  3005. CLUSTER_RESERVED) {
  3006. /* cluster drive RESERVED (on the other node) */
  3007. cmndinfo->phase = -2; /* reservation conflict */
  3008. }
  3009. } else {
  3010. cmndinfo->OpCode = -1;
  3011. }
  3012. } else {
  3013. if (cmndinfo->OpCode == GDT_MOUNT) {
  3014. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3015. ha->hdr[t].media_changed = TRUE;
  3016. } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
  3017. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3018. ha->hdr[t].media_changed = TRUE;
  3019. }
  3020. cmndinfo->OpCode = -1;
  3021. }
  3022. /* retry */
  3023. cmndinfo->priority = HIGH_PRI;
  3024. return 2;
  3025. } else {
  3026. /* RESERVE/RELEASE ? */
  3027. if (scp->cmnd[0] == RESERVE) {
  3028. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3029. } else if (scp->cmnd[0] == RELEASE) {
  3030. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3031. }
  3032. scp->result = DID_OK << 16;
  3033. scp->sense_buffer[0] = 0;
  3034. }
  3035. } else {
  3036. cmndinfo->status = ha->status;
  3037. cmndinfo->info = ha->info;
  3038. if (cmndinfo->OpCode != -1) {
  3039. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3040. cmndinfo->OpCode, ha->status));
  3041. if (cmndinfo->OpCode == GDT_SCAN_START ||
  3042. cmndinfo->OpCode == GDT_SCAN_END) {
  3043. cmndinfo->OpCode = -1;
  3044. /* retry */
  3045. cmndinfo->priority = HIGH_PRI;
  3046. return 2;
  3047. }
  3048. memset((char*)scp->sense_buffer,0,16);
  3049. scp->sense_buffer[0] = 0x70;
  3050. scp->sense_buffer[2] = NOT_READY;
  3051. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3052. } else if (service == CACHESERVICE) {
  3053. if (ha->status == S_CACHE_UNKNOWN &&
  3054. (ha->hdr[t].cluster_type &
  3055. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3056. /* bus reset -> force GDT_CLUST_INFO */
  3057. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3058. }
  3059. memset((char*)scp->sense_buffer,0,16);
  3060. if (ha->status == (u16)S_CACHE_RESERV) {
  3061. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3062. } else {
  3063. scp->sense_buffer[0] = 0x70;
  3064. scp->sense_buffer[2] = NOT_READY;
  3065. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3066. }
  3067. if (!cmndinfo->internal_command) {
  3068. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3069. ha->dvr.eu.sync.ionode = ha->hanum;
  3070. ha->dvr.eu.sync.service = service;
  3071. ha->dvr.eu.sync.status = ha->status;
  3072. ha->dvr.eu.sync.info = ha->info;
  3073. ha->dvr.eu.sync.hostdrive = t;
  3074. if (ha->status >= 0x8000)
  3075. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3076. else
  3077. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3078. }
  3079. } else {
  3080. /* sense buffer filled from controller firmware (DMA) */
  3081. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3082. scp->result = DID_BAD_TARGET << 16;
  3083. } else {
  3084. scp->result = (DID_OK << 16) | ha->info;
  3085. }
  3086. }
  3087. }
  3088. if (!cmndinfo->wait_for_completion)
  3089. cmndinfo->wait_for_completion++;
  3090. else
  3091. return 1;
  3092. }
  3093. return 0;
  3094. }
  3095. static char *async_cache_tab[] = {
  3096. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3097. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3098. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3099. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3100. /* 2*/ "\005\000\002\006\004"
  3101. "GDT HA %u, Host Drive %lu not ready",
  3102. /* 3*/ "\005\000\002\006\004"
  3103. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3104. /* 4*/ "\005\000\002\006\004"
  3105. "GDT HA %u, mirror update on Host Drive %lu failed",
  3106. /* 5*/ "\005\000\002\006\004"
  3107. "GDT HA %u, Mirror Drive %lu failed",
  3108. /* 6*/ "\005\000\002\006\004"
  3109. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3110. /* 7*/ "\005\000\002\006\004"
  3111. "GDT HA %u, Host Drive %lu write protected",
  3112. /* 8*/ "\005\000\002\006\004"
  3113. "GDT HA %u, media changed in Host Drive %lu",
  3114. /* 9*/ "\005\000\002\006\004"
  3115. "GDT HA %u, Host Drive %lu is offline",
  3116. /*10*/ "\005\000\002\006\004"
  3117. "GDT HA %u, media change of Mirror Drive %lu",
  3118. /*11*/ "\005\000\002\006\004"
  3119. "GDT HA %u, Mirror Drive %lu is write protected",
  3120. /*12*/ "\005\000\002\006\004"
  3121. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3122. /*13*/ "\007\000\002\006\002\010\002"
  3123. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3124. /*14*/ "\005\000\002\006\002"
  3125. "GDT HA %u, Array Drive %u: FAIL state entered",
  3126. /*15*/ "\005\000\002\006\002"
  3127. "GDT HA %u, Array Drive %u: error",
  3128. /*16*/ "\007\000\002\006\002\010\002"
  3129. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3130. /*17*/ "\005\000\002\006\002"
  3131. "GDT HA %u, Array Drive %u: parity build failed",
  3132. /*18*/ "\005\000\002\006\002"
  3133. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3134. /*19*/ "\005\000\002\010\002"
  3135. "GDT HA %u, Test of Hot Fix %u failed",
  3136. /*20*/ "\005\000\002\006\002"
  3137. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3138. /*21*/ "\005\000\002\006\002"
  3139. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3140. /*22*/ "\007\000\002\006\002\010\002"
  3141. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3142. /*23*/ "\005\000\002\006\002"
  3143. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3144. /*24*/ "\005\000\002\010\002"
  3145. "GDT HA %u, mirror update on Cache Drive %u completed",
  3146. /*25*/ "\005\000\002\010\002"
  3147. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3148. /*26*/ "\005\000\002\006\002"
  3149. "GDT HA %u, Array Drive %u: drive rebuild started",
  3150. /*27*/ "\005\000\002\012\001"
  3151. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3152. /*28*/ "\005\000\002\012\001"
  3153. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3154. /*29*/ "\007\000\002\012\001\013\001"
  3155. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3156. /*30*/ "\007\000\002\012\001\013\001"
  3157. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3158. /*31*/ "\007\000\002\012\001\013\001"
  3159. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3160. /*32*/ "\007\000\002\012\001\013\001"
  3161. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3162. /*33*/ "\007\000\002\012\001\013\001"
  3163. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3164. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3165. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3166. /*35*/ "\007\000\002\012\001\013\001"
  3167. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3168. /*36*/ "\007\000\002\012\001\013\001"
  3169. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3170. /*37*/ "\007\000\002\012\001\006\004"
  3171. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3172. /*38*/ "\007\000\002\012\001\013\001"
  3173. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3174. /*39*/ "\007\000\002\012\001\013\001"
  3175. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3176. /*40*/ "\007\000\002\012\001\013\001"
  3177. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3178. /*41*/ "\007\000\002\012\001\013\001"
  3179. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3180. /*42*/ "\005\000\002\006\002"
  3181. "GDT HA %u, Array Drive %u: drive build started",
  3182. /*43*/ "\003\000\002"
  3183. "GDT HA %u, DRAM parity error detected",
  3184. /*44*/ "\005\000\002\006\002"
  3185. "GDT HA %u, Mirror Drive %u: update started",
  3186. /*45*/ "\007\000\002\006\002\010\002"
  3187. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3188. /*46*/ "\005\000\002\006\002"
  3189. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3190. /*47*/ "\005\000\002\006\002"
  3191. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3192. /*48*/ "\005\000\002\006\002"
  3193. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3194. /*49*/ "\005\000\002\006\002"
  3195. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3196. /*50*/ "\007\000\002\012\001\013\001"
  3197. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3198. /*51*/ "\005\000\002\006\002"
  3199. "GDT HA %u, Array Drive %u: expand started",
  3200. /*52*/ "\005\000\002\006\002"
  3201. "GDT HA %u, Array Drive %u: expand finished successfully",
  3202. /*53*/ "\005\000\002\006\002"
  3203. "GDT HA %u, Array Drive %u: expand failed",
  3204. /*54*/ "\003\000\002"
  3205. "GDT HA %u, CPU temperature critical",
  3206. /*55*/ "\003\000\002"
  3207. "GDT HA %u, CPU temperature OK",
  3208. /*56*/ "\005\000\002\006\004"
  3209. "GDT HA %u, Host drive %lu created",
  3210. /*57*/ "\005\000\002\006\002"
  3211. "GDT HA %u, Array Drive %u: expand restarted",
  3212. /*58*/ "\005\000\002\006\002"
  3213. "GDT HA %u, Array Drive %u: expand stopped",
  3214. /*59*/ "\005\000\002\010\002"
  3215. "GDT HA %u, Mirror Drive %u: drive build quited",
  3216. /*60*/ "\005\000\002\006\002"
  3217. "GDT HA %u, Array Drive %u: parity build quited",
  3218. /*61*/ "\005\000\002\006\002"
  3219. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3220. /*62*/ "\005\000\002\006\002"
  3221. "GDT HA %u, Array Drive %u: parity verify started",
  3222. /*63*/ "\005\000\002\006\002"
  3223. "GDT HA %u, Array Drive %u: parity verify done",
  3224. /*64*/ "\005\000\002\006\002"
  3225. "GDT HA %u, Array Drive %u: parity verify failed",
  3226. /*65*/ "\005\000\002\006\002"
  3227. "GDT HA %u, Array Drive %u: parity error detected",
  3228. /*66*/ "\005\000\002\006\002"
  3229. "GDT HA %u, Array Drive %u: parity verify quited",
  3230. /*67*/ "\005\000\002\006\002"
  3231. "GDT HA %u, Host Drive %u reserved",
  3232. /*68*/ "\005\000\002\006\002"
  3233. "GDT HA %u, Host Drive %u mounted and released",
  3234. /*69*/ "\005\000\002\006\002"
  3235. "GDT HA %u, Host Drive %u released",
  3236. /*70*/ "\003\000\002"
  3237. "GDT HA %u, DRAM error detected and corrected with ECC",
  3238. /*71*/ "\003\000\002"
  3239. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3240. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3241. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3242. /*73*/ "\005\000\002\006\002"
  3243. "GDT HA %u, Host drive %u resetted locally",
  3244. /*74*/ "\005\000\002\006\002"
  3245. "GDT HA %u, Host drive %u resetted remotely",
  3246. /*75*/ "\003\000\002"
  3247. "GDT HA %u, async. status 75 unknown",
  3248. };
  3249. static int gdth_async_event(gdth_ha_str *ha)
  3250. {
  3251. gdth_cmd_str *cmdp;
  3252. int cmd_index;
  3253. cmdp= ha->pccb;
  3254. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3255. ha->hanum, ha->service));
  3256. if (ha->service == SCREENSERVICE) {
  3257. if (ha->status == MSG_REQUEST) {
  3258. while (gdth_test_busy(ha))
  3259. gdth_delay(0);
  3260. cmdp->Service = SCREENSERVICE;
  3261. cmdp->RequestBuffer = SCREEN_CMND;
  3262. cmd_index = gdth_get_cmd_index(ha);
  3263. gdth_set_sema0(ha);
  3264. cmdp->OpCode = GDT_READ;
  3265. cmdp->BoardNode = LOCALBOARD;
  3266. cmdp->u.screen.reserved = 0;
  3267. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3268. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3269. ha->cmd_offs_dpmem = 0;
  3270. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3271. + sizeof(u64);
  3272. ha->cmd_cnt = 0;
  3273. gdth_copy_command(ha);
  3274. if (ha->type == GDT_EISA)
  3275. printk("[EISA slot %d] ",(u16)ha->brd_phys);
  3276. else if (ha->type == GDT_ISA)
  3277. printk("[DPMEM 0x%4X] ",(u16)ha->brd_phys);
  3278. else
  3279. printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8),
  3280. (u16)((ha->brd_phys>>3)&0x1f));
  3281. gdth_release_event(ha);
  3282. }
  3283. } else {
  3284. if (ha->type == GDT_PCIMPR &&
  3285. (ha->fw_vers & 0xff) >= 0x1a) {
  3286. ha->dvr.size = 0;
  3287. ha->dvr.eu.async.ionode = ha->hanum;
  3288. ha->dvr.eu.async.status = ha->status;
  3289. /* severity and event_string already set! */
  3290. } else {
  3291. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3292. ha->dvr.eu.async.ionode = ha->hanum;
  3293. ha->dvr.eu.async.service = ha->service;
  3294. ha->dvr.eu.async.status = ha->status;
  3295. ha->dvr.eu.async.info = ha->info;
  3296. *(u32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3297. }
  3298. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3299. gdth_log_event( &ha->dvr, NULL );
  3300. /* new host drive from expand? */
  3301. if (ha->service == CACHESERVICE && ha->status == 56) {
  3302. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3303. (u16)ha->info));
  3304. /* gdth_analyse_hdrive(hanum, (u16)ha->info); */
  3305. }
  3306. }
  3307. return 1;
  3308. }
  3309. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3310. {
  3311. gdth_stackframe stack;
  3312. char *f = NULL;
  3313. int i,j;
  3314. TRACE2(("gdth_log_event()\n"));
  3315. if (dvr->size == 0) {
  3316. if (buffer == NULL) {
  3317. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3318. } else {
  3319. sprintf(buffer,"Adapter %d: %s\n",
  3320. dvr->eu.async.ionode,dvr->event_string);
  3321. }
  3322. } else if (dvr->eu.async.service == CACHESERVICE &&
  3323. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3324. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3325. dvr->eu.async.status));
  3326. f = async_cache_tab[dvr->eu.async.status];
  3327. /* i: parameter to push, j: stack element to fill */
  3328. for (j=0,i=1; i < f[0]; i+=2) {
  3329. switch (f[i+1]) {
  3330. case 4:
  3331. stack.b[j++] = *(u32*)&dvr->eu.stream[(int)f[i]];
  3332. break;
  3333. case 2:
  3334. stack.b[j++] = *(u16*)&dvr->eu.stream[(int)f[i]];
  3335. break;
  3336. case 1:
  3337. stack.b[j++] = *(u8*)&dvr->eu.stream[(int)f[i]];
  3338. break;
  3339. default:
  3340. break;
  3341. }
  3342. }
  3343. if (buffer == NULL) {
  3344. printk(&f[(int)f[0]],stack);
  3345. printk("\n");
  3346. } else {
  3347. sprintf(buffer,&f[(int)f[0]],stack);
  3348. }
  3349. } else {
  3350. if (buffer == NULL) {
  3351. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3352. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3353. } else {
  3354. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3355. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3356. }
  3357. }
  3358. }
  3359. #ifdef GDTH_STATISTICS
  3360. static u8 gdth_timer_running;
  3361. static void gdth_timeout(unsigned long data)
  3362. {
  3363. u32 i;
  3364. Scsi_Cmnd *nscp;
  3365. gdth_ha_str *ha;
  3366. unsigned long flags;
  3367. if(unlikely(list_empty(&gdth_instances))) {
  3368. gdth_timer_running = 0;
  3369. return;
  3370. }
  3371. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3372. spin_lock_irqsave(&ha->smp_lock, flags);
  3373. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3374. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3375. ++act_stats;
  3376. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3377. ++act_rq;
  3378. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3379. act_ints, act_ios, act_stats, act_rq));
  3380. act_ints = act_ios = 0;
  3381. gdth_timer.expires = jiffies + 30 * HZ;
  3382. add_timer(&gdth_timer);
  3383. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3384. }
  3385. static void gdth_timer_init(void)
  3386. {
  3387. if (gdth_timer_running)
  3388. return;
  3389. gdth_timer_running = 1;
  3390. TRACE2(("gdth_detect(): Initializing timer !\n"));
  3391. gdth_timer.expires = jiffies + HZ;
  3392. gdth_timer.data = 0L;
  3393. gdth_timer.function = gdth_timeout;
  3394. add_timer(&gdth_timer);
  3395. }
  3396. #else
  3397. static inline void gdth_timer_init(void)
  3398. {
  3399. }
  3400. #endif
  3401. static void __init internal_setup(char *str,int *ints)
  3402. {
  3403. int i, argc;
  3404. char *cur_str, *argv;
  3405. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3406. str ? str:"NULL", ints ? ints[0]:0));
  3407. /* read irq[] from ints[] */
  3408. if (ints) {
  3409. argc = ints[0];
  3410. if (argc > 0) {
  3411. if (argc > MAXHA)
  3412. argc = MAXHA;
  3413. for (i = 0; i < argc; ++i)
  3414. irq[i] = ints[i+1];
  3415. }
  3416. }
  3417. /* analyse string */
  3418. argv = str;
  3419. while (argv && (cur_str = strchr(argv, ':'))) {
  3420. int val = 0, c = *++cur_str;
  3421. if (c == 'n' || c == 'N')
  3422. val = 0;
  3423. else if (c == 'y' || c == 'Y')
  3424. val = 1;
  3425. else
  3426. val = (int)simple_strtoul(cur_str, NULL, 0);
  3427. if (!strncmp(argv, "disable:", 8))
  3428. disable = val;
  3429. else if (!strncmp(argv, "reserve_mode:", 13))
  3430. reserve_mode = val;
  3431. else if (!strncmp(argv, "reverse_scan:", 13))
  3432. reverse_scan = val;
  3433. else if (!strncmp(argv, "hdr_channel:", 12))
  3434. hdr_channel = val;
  3435. else if (!strncmp(argv, "max_ids:", 8))
  3436. max_ids = val;
  3437. else if (!strncmp(argv, "rescan:", 7))
  3438. rescan = val;
  3439. else if (!strncmp(argv, "shared_access:", 14))
  3440. shared_access = val;
  3441. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3442. probe_eisa_isa = val;
  3443. else if (!strncmp(argv, "reserve_list:", 13)) {
  3444. reserve_list[0] = val;
  3445. for (i = 1; i < MAX_RES_ARGS; i++) {
  3446. cur_str = strchr(cur_str, ',');
  3447. if (!cur_str)
  3448. break;
  3449. if (!isdigit((int)*++cur_str)) {
  3450. --cur_str;
  3451. break;
  3452. }
  3453. reserve_list[i] =
  3454. (int)simple_strtoul(cur_str, NULL, 0);
  3455. }
  3456. if (!cur_str)
  3457. break;
  3458. argv = ++cur_str;
  3459. continue;
  3460. }
  3461. if ((argv = strchr(argv, ',')))
  3462. ++argv;
  3463. }
  3464. }
  3465. int __init option_setup(char *str)
  3466. {
  3467. int ints[MAXHA];
  3468. char *cur = str;
  3469. int i = 1;
  3470. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3471. while (cur && isdigit(*cur) && i < MAXHA) {
  3472. ints[i++] = simple_strtoul(cur, NULL, 0);
  3473. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3474. }
  3475. ints[0] = i - 1;
  3476. internal_setup(cur, ints);
  3477. return 1;
  3478. }
  3479. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3480. {
  3481. TRACE2(("gdth_ctr_name()\n"));
  3482. if (ha->type == GDT_EISA) {
  3483. switch (ha->stype) {
  3484. case GDT3_ID:
  3485. return("GDT3000/3020");
  3486. case GDT3A_ID:
  3487. return("GDT3000A/3020A/3050A");
  3488. case GDT3B_ID:
  3489. return("GDT3000B/3010A");
  3490. }
  3491. } else if (ha->type == GDT_ISA) {
  3492. return("GDT2000/2020");
  3493. } else if (ha->type == GDT_PCI) {
  3494. switch (ha->pdev->device) {
  3495. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3496. return("GDT6000/6020/6050");
  3497. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3498. return("GDT6000B/6010");
  3499. }
  3500. }
  3501. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3502. return("");
  3503. }
  3504. static const char *gdth_info(struct Scsi_Host *shp)
  3505. {
  3506. gdth_ha_str *ha = shost_priv(shp);
  3507. TRACE2(("gdth_info()\n"));
  3508. return ((const char *)ha->binfo.type_string);
  3509. }
  3510. static enum blk_eh_timer_return gdth_timed_out(struct scsi_cmnd *scp)
  3511. {
  3512. gdth_ha_str *ha = shost_priv(scp->device->host);
  3513. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  3514. u8 b, t;
  3515. unsigned long flags;
  3516. enum blk_eh_timer_return retval = BLK_EH_NOT_HANDLED;
  3517. TRACE(("%s() cmd 0x%x\n", scp->cmnd[0], __func__));
  3518. b = scp->device->channel;
  3519. t = scp->device->id;
  3520. /*
  3521. * We don't really honor the command timeout, but we try to
  3522. * honor 6 times of the actual command timeout! So reset the
  3523. * timer if this is less than 6th timeout on this command!
  3524. */
  3525. if (++cmndinfo->timeout_count < 6)
  3526. retval = BLK_EH_RESET_TIMER;
  3527. /* Reset the timeout if it is locked IO */
  3528. spin_lock_irqsave(&ha->smp_lock, flags);
  3529. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha, b)].lock) ||
  3530. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
  3531. TRACE2(("%s(): locked IO, reset timeout\n", __func__));
  3532. retval = BLK_EH_RESET_TIMER;
  3533. }
  3534. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3535. return retval;
  3536. }
  3537. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3538. {
  3539. gdth_ha_str *ha = shost_priv(scp->device->host);
  3540. int i;
  3541. unsigned long flags;
  3542. Scsi_Cmnd *cmnd;
  3543. u8 b;
  3544. TRACE2(("gdth_eh_bus_reset()\n"));
  3545. b = scp->device->channel;
  3546. /* clear command tab */
  3547. spin_lock_irqsave(&ha->smp_lock, flags);
  3548. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3549. cmnd = ha->cmd_tab[i].cmnd;
  3550. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3551. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3552. }
  3553. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3554. if (b == ha->virt_bus) {
  3555. /* host drives */
  3556. for (i = 0; i < MAX_HDRIVES; ++i) {
  3557. if (ha->hdr[i].present) {
  3558. spin_lock_irqsave(&ha->smp_lock, flags);
  3559. gdth_polling = TRUE;
  3560. while (gdth_test_busy(ha))
  3561. gdth_delay(0);
  3562. if (gdth_internal_cmd(ha, CACHESERVICE,
  3563. GDT_CLUST_RESET, i, 0, 0))
  3564. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3565. gdth_polling = FALSE;
  3566. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3567. }
  3568. }
  3569. } else {
  3570. /* raw devices */
  3571. spin_lock_irqsave(&ha->smp_lock, flags);
  3572. for (i = 0; i < MAXID; ++i)
  3573. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3574. gdth_polling = TRUE;
  3575. while (gdth_test_busy(ha))
  3576. gdth_delay(0);
  3577. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3578. BUS_L2P(ha,b), 0, 0);
  3579. gdth_polling = FALSE;
  3580. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3581. }
  3582. return SUCCESS;
  3583. }
  3584. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3585. {
  3586. u8 b, t;
  3587. gdth_ha_str *ha = shost_priv(sdev->host);
  3588. struct scsi_device *sd;
  3589. unsigned capacity;
  3590. sd = sdev;
  3591. capacity = cap;
  3592. b = sd->channel;
  3593. t = sd->id;
  3594. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3595. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3596. /* raw device or host drive without mapping information */
  3597. TRACE2(("Evaluate mapping\n"));
  3598. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3599. } else {
  3600. ip[0] = ha->hdr[t].heads;
  3601. ip[1] = ha->hdr[t].secs;
  3602. ip[2] = capacity / ip[0] / ip[1];
  3603. }
  3604. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3605. ip[0],ip[1],ip[2]));
  3606. return 0;
  3607. }
  3608. static int gdth_queuecommand_lck(struct scsi_cmnd *scp,
  3609. void (*done)(struct scsi_cmnd *))
  3610. {
  3611. gdth_ha_str *ha = shost_priv(scp->device->host);
  3612. struct gdth_cmndinfo *cmndinfo;
  3613. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3614. cmndinfo = gdth_get_cmndinfo(ha);
  3615. BUG_ON(!cmndinfo);
  3616. scp->scsi_done = done;
  3617. cmndinfo->timeout_count = 0;
  3618. cmndinfo->priority = DEFAULT_PRI;
  3619. return __gdth_queuecommand(ha, scp, cmndinfo);
  3620. }
  3621. static DEF_SCSI_QCMD(gdth_queuecommand)
  3622. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3623. struct gdth_cmndinfo *cmndinfo)
  3624. {
  3625. scp->host_scribble = (unsigned char *)cmndinfo;
  3626. cmndinfo->wait_for_completion = 1;
  3627. cmndinfo->phase = -1;
  3628. cmndinfo->OpCode = -1;
  3629. #ifdef GDTH_STATISTICS
  3630. ++act_ios;
  3631. #endif
  3632. gdth_putq(ha, scp, cmndinfo->priority);
  3633. gdth_next(ha);
  3634. return 0;
  3635. }
  3636. static int gdth_open(struct inode *inode, struct file *filep)
  3637. {
  3638. gdth_ha_str *ha;
  3639. mutex_lock(&gdth_mutex);
  3640. list_for_each_entry(ha, &gdth_instances, list) {
  3641. if (!ha->sdev)
  3642. ha->sdev = scsi_get_host_dev(ha->shost);
  3643. }
  3644. mutex_unlock(&gdth_mutex);
  3645. TRACE(("gdth_open()\n"));
  3646. return 0;
  3647. }
  3648. static int gdth_close(struct inode *inode, struct file *filep)
  3649. {
  3650. TRACE(("gdth_close()\n"));
  3651. return 0;
  3652. }
  3653. static int ioc_event(void __user *arg)
  3654. {
  3655. gdth_ioctl_event evt;
  3656. gdth_ha_str *ha;
  3657. unsigned long flags;
  3658. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3659. return -EFAULT;
  3660. ha = gdth_find_ha(evt.ionode);
  3661. if (!ha)
  3662. return -EFAULT;
  3663. if (evt.erase == 0xff) {
  3664. if (evt.event.event_source == ES_TEST)
  3665. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3666. else if (evt.event.event_source == ES_DRIVER)
  3667. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3668. else if (evt.event.event_source == ES_SYNC)
  3669. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3670. else
  3671. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3672. spin_lock_irqsave(&ha->smp_lock, flags);
  3673. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3674. &evt.event.event_data);
  3675. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3676. } else if (evt.erase == 0xfe) {
  3677. gdth_clear_events();
  3678. } else if (evt.erase == 0) {
  3679. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3680. } else {
  3681. gdth_readapp_event(ha, evt.erase, &evt.event);
  3682. }
  3683. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3684. return -EFAULT;
  3685. return 0;
  3686. }
  3687. static int ioc_lockdrv(void __user *arg)
  3688. {
  3689. gdth_ioctl_lockdrv ldrv;
  3690. u8 i, j;
  3691. unsigned long flags;
  3692. gdth_ha_str *ha;
  3693. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3694. return -EFAULT;
  3695. ha = gdth_find_ha(ldrv.ionode);
  3696. if (!ha)
  3697. return -EFAULT;
  3698. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3699. j = ldrv.drives[i];
  3700. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3701. continue;
  3702. if (ldrv.lock) {
  3703. spin_lock_irqsave(&ha->smp_lock, flags);
  3704. ha->hdr[j].lock = 1;
  3705. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3706. gdth_wait_completion(ha, ha->bus_cnt, j);
  3707. } else {
  3708. spin_lock_irqsave(&ha->smp_lock, flags);
  3709. ha->hdr[j].lock = 0;
  3710. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3711. gdth_next(ha);
  3712. }
  3713. }
  3714. return 0;
  3715. }
  3716. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3717. {
  3718. gdth_ioctl_reset res;
  3719. gdth_cmd_str cmd;
  3720. gdth_ha_str *ha;
  3721. int rval;
  3722. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3723. res.number >= MAX_HDRIVES)
  3724. return -EFAULT;
  3725. ha = gdth_find_ha(res.ionode);
  3726. if (!ha)
  3727. return -EFAULT;
  3728. if (!ha->hdr[res.number].present)
  3729. return 0;
  3730. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3731. cmd.Service = CACHESERVICE;
  3732. cmd.OpCode = GDT_CLUST_RESET;
  3733. if (ha->cache_feat & GDT_64BIT)
  3734. cmd.u.cache64.DeviceNo = res.number;
  3735. else
  3736. cmd.u.cache.DeviceNo = res.number;
  3737. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3738. if (rval < 0)
  3739. return rval;
  3740. res.status = rval;
  3741. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3742. return -EFAULT;
  3743. return 0;
  3744. }
  3745. static int ioc_general(void __user *arg, char *cmnd)
  3746. {
  3747. gdth_ioctl_general gen;
  3748. char *buf = NULL;
  3749. u64 paddr;
  3750. gdth_ha_str *ha;
  3751. int rval;
  3752. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3753. return -EFAULT;
  3754. ha = gdth_find_ha(gen.ionode);
  3755. if (!ha)
  3756. return -EFAULT;
  3757. if (gen.data_len > INT_MAX)
  3758. return -EINVAL;
  3759. if (gen.sense_len > INT_MAX)
  3760. return -EINVAL;
  3761. if (gen.data_len + gen.sense_len > INT_MAX)
  3762. return -EINVAL;
  3763. if (gen.data_len + gen.sense_len != 0) {
  3764. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3765. FALSE, &paddr)))
  3766. return -EFAULT;
  3767. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3768. gen.data_len + gen.sense_len)) {
  3769. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3770. return -EFAULT;
  3771. }
  3772. if (gen.command.OpCode == GDT_IOCTL) {
  3773. gen.command.u.ioctl.p_param = paddr;
  3774. } else if (gen.command.Service == CACHESERVICE) {
  3775. if (ha->cache_feat & GDT_64BIT) {
  3776. /* copy elements from 32-bit IOCTL structure */
  3777. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3778. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3779. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3780. /* addresses */
  3781. if (ha->cache_feat & SCATTER_GATHER) {
  3782. gen.command.u.cache64.DestAddr = (u64)-1;
  3783. gen.command.u.cache64.sg_canz = 1;
  3784. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3785. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3786. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3787. } else {
  3788. gen.command.u.cache64.DestAddr = paddr;
  3789. gen.command.u.cache64.sg_canz = 0;
  3790. }
  3791. } else {
  3792. if (ha->cache_feat & SCATTER_GATHER) {
  3793. gen.command.u.cache.DestAddr = 0xffffffff;
  3794. gen.command.u.cache.sg_canz = 1;
  3795. gen.command.u.cache.sg_lst[0].sg_ptr = (u32)paddr;
  3796. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3797. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3798. } else {
  3799. gen.command.u.cache.DestAddr = paddr;
  3800. gen.command.u.cache.sg_canz = 0;
  3801. }
  3802. }
  3803. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3804. if (ha->raw_feat & GDT_64BIT) {
  3805. /* copy elements from 32-bit IOCTL structure */
  3806. char cmd[16];
  3807. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3808. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3809. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3810. gen.command.u.raw64.target = gen.command.u.raw.target;
  3811. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3812. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3813. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3814. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3815. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3816. /* addresses */
  3817. if (ha->raw_feat & SCATTER_GATHER) {
  3818. gen.command.u.raw64.sdata = (u64)-1;
  3819. gen.command.u.raw64.sg_ranz = 1;
  3820. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3821. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3822. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3823. } else {
  3824. gen.command.u.raw64.sdata = paddr;
  3825. gen.command.u.raw64.sg_ranz = 0;
  3826. }
  3827. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3828. } else {
  3829. if (ha->raw_feat & SCATTER_GATHER) {
  3830. gen.command.u.raw.sdata = 0xffffffff;
  3831. gen.command.u.raw.sg_ranz = 1;
  3832. gen.command.u.raw.sg_lst[0].sg_ptr = (u32)paddr;
  3833. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3834. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3835. } else {
  3836. gen.command.u.raw.sdata = paddr;
  3837. gen.command.u.raw.sg_ranz = 0;
  3838. }
  3839. gen.command.u.raw.sense_data = (u32)paddr + gen.data_len;
  3840. }
  3841. } else {
  3842. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3843. return -EFAULT;
  3844. }
  3845. }
  3846. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3847. if (rval < 0) {
  3848. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3849. return rval;
  3850. }
  3851. gen.status = rval;
  3852. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3853. gen.data_len + gen.sense_len)) {
  3854. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3855. return -EFAULT;
  3856. }
  3857. if (copy_to_user(arg, &gen,
  3858. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3859. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3860. return -EFAULT;
  3861. }
  3862. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3863. return 0;
  3864. }
  3865. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3866. {
  3867. gdth_ioctl_rescan *rsc;
  3868. gdth_cmd_str *cmd;
  3869. gdth_ha_str *ha;
  3870. u8 i;
  3871. int rc = -ENOMEM;
  3872. u32 cluster_type = 0;
  3873. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3874. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3875. if (!rsc || !cmd)
  3876. goto free_fail;
  3877. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3878. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3879. rc = -EFAULT;
  3880. goto free_fail;
  3881. }
  3882. memset(cmd, 0, sizeof(gdth_cmd_str));
  3883. for (i = 0; i < MAX_HDRIVES; ++i) {
  3884. if (!ha->hdr[i].present) {
  3885. rsc->hdr_list[i].bus = 0xff;
  3886. continue;
  3887. }
  3888. rsc->hdr_list[i].bus = ha->virt_bus;
  3889. rsc->hdr_list[i].target = i;
  3890. rsc->hdr_list[i].lun = 0;
  3891. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3892. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3893. cmd->Service = CACHESERVICE;
  3894. cmd->OpCode = GDT_CLUST_INFO;
  3895. if (ha->cache_feat & GDT_64BIT)
  3896. cmd->u.cache64.DeviceNo = i;
  3897. else
  3898. cmd->u.cache.DeviceNo = i;
  3899. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3900. rsc->hdr_list[i].cluster_type = cluster_type;
  3901. }
  3902. }
  3903. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3904. rc = -EFAULT;
  3905. else
  3906. rc = 0;
  3907. free_fail:
  3908. kfree(rsc);
  3909. kfree(cmd);
  3910. return rc;
  3911. }
  3912. static int ioc_rescan(void __user *arg, char *cmnd)
  3913. {
  3914. gdth_ioctl_rescan *rsc;
  3915. gdth_cmd_str *cmd;
  3916. u16 i, status, hdr_cnt;
  3917. u32 info;
  3918. int cyls, hds, secs;
  3919. int rc = -ENOMEM;
  3920. unsigned long flags;
  3921. gdth_ha_str *ha;
  3922. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3923. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3924. if (!cmd || !rsc)
  3925. goto free_fail;
  3926. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3927. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3928. rc = -EFAULT;
  3929. goto free_fail;
  3930. }
  3931. memset(cmd, 0, sizeof(gdth_cmd_str));
  3932. if (rsc->flag == 0) {
  3933. /* old method: re-init. cache service */
  3934. cmd->Service = CACHESERVICE;
  3935. if (ha->cache_feat & GDT_64BIT) {
  3936. cmd->OpCode = GDT_X_INIT_HOST;
  3937. cmd->u.cache64.DeviceNo = LINUX_OS;
  3938. } else {
  3939. cmd->OpCode = GDT_INIT;
  3940. cmd->u.cache.DeviceNo = LINUX_OS;
  3941. }
  3942. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3943. i = 0;
  3944. hdr_cnt = (status == S_OK ? (u16)info : 0);
  3945. } else {
  3946. i = rsc->hdr_no;
  3947. hdr_cnt = i + 1;
  3948. }
  3949. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3950. cmd->Service = CACHESERVICE;
  3951. cmd->OpCode = GDT_INFO;
  3952. if (ha->cache_feat & GDT_64BIT)
  3953. cmd->u.cache64.DeviceNo = i;
  3954. else
  3955. cmd->u.cache.DeviceNo = i;
  3956. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3957. spin_lock_irqsave(&ha->smp_lock, flags);
  3958. rsc->hdr_list[i].bus = ha->virt_bus;
  3959. rsc->hdr_list[i].target = i;
  3960. rsc->hdr_list[i].lun = 0;
  3961. if (status != S_OK) {
  3962. ha->hdr[i].present = FALSE;
  3963. } else {
  3964. ha->hdr[i].present = TRUE;
  3965. ha->hdr[i].size = info;
  3966. /* evaluate mapping */
  3967. ha->hdr[i].size &= ~SECS32;
  3968. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3969. ha->hdr[i].heads = hds;
  3970. ha->hdr[i].secs = secs;
  3971. /* round size */
  3972. ha->hdr[i].size = cyls * hds * secs;
  3973. }
  3974. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3975. if (status != S_OK)
  3976. continue;
  3977. /* extended info, if GDT_64BIT, for drives > 2 TB */
  3978. /* but we need ha->info2, not yet stored in scp->SCp */
  3979. /* devtype, cluster info, R/W attribs */
  3980. cmd->Service = CACHESERVICE;
  3981. cmd->OpCode = GDT_DEVTYPE;
  3982. if (ha->cache_feat & GDT_64BIT)
  3983. cmd->u.cache64.DeviceNo = i;
  3984. else
  3985. cmd->u.cache.DeviceNo = i;
  3986. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3987. spin_lock_irqsave(&ha->smp_lock, flags);
  3988. ha->hdr[i].devtype = (status == S_OK ? (u16)info : 0);
  3989. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3990. cmd->Service = CACHESERVICE;
  3991. cmd->OpCode = GDT_CLUST_INFO;
  3992. if (ha->cache_feat & GDT_64BIT)
  3993. cmd->u.cache64.DeviceNo = i;
  3994. else
  3995. cmd->u.cache.DeviceNo = i;
  3996. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3997. spin_lock_irqsave(&ha->smp_lock, flags);
  3998. ha->hdr[i].cluster_type =
  3999. ((status == S_OK && !shared_access) ? (u16)info : 0);
  4000. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4001. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4002. cmd->Service = CACHESERVICE;
  4003. cmd->OpCode = GDT_RW_ATTRIBS;
  4004. if (ha->cache_feat & GDT_64BIT)
  4005. cmd->u.cache64.DeviceNo = i;
  4006. else
  4007. cmd->u.cache.DeviceNo = i;
  4008. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4009. spin_lock_irqsave(&ha->smp_lock, flags);
  4010. ha->hdr[i].rw_attribs = (status == S_OK ? (u16)info : 0);
  4011. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4012. }
  4013. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4014. rc = -EFAULT;
  4015. else
  4016. rc = 0;
  4017. free_fail:
  4018. kfree(rsc);
  4019. kfree(cmd);
  4020. return rc;
  4021. }
  4022. static int gdth_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
  4023. {
  4024. gdth_ha_str *ha;
  4025. Scsi_Cmnd *scp;
  4026. unsigned long flags;
  4027. char cmnd[MAX_COMMAND_SIZE];
  4028. void __user *argp = (void __user *)arg;
  4029. memset(cmnd, 0xff, 12);
  4030. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4031. switch (cmd) {
  4032. case GDTIOCTL_CTRCNT:
  4033. {
  4034. int cnt = gdth_ctr_count;
  4035. if (put_user(cnt, (int __user *)argp))
  4036. return -EFAULT;
  4037. break;
  4038. }
  4039. case GDTIOCTL_DRVERS:
  4040. {
  4041. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4042. if (put_user(ver, (int __user *)argp))
  4043. return -EFAULT;
  4044. break;
  4045. }
  4046. case GDTIOCTL_OSVERS:
  4047. {
  4048. gdth_ioctl_osvers osv;
  4049. osv.version = (u8)(LINUX_VERSION_CODE >> 16);
  4050. osv.subversion = (u8)(LINUX_VERSION_CODE >> 8);
  4051. osv.revision = (u16)(LINUX_VERSION_CODE & 0xff);
  4052. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4053. return -EFAULT;
  4054. break;
  4055. }
  4056. case GDTIOCTL_CTRTYPE:
  4057. {
  4058. gdth_ioctl_ctrtype ctrt;
  4059. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4060. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4061. return -EFAULT;
  4062. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4063. ctrt.type = (u8)((ha->stype>>20) - 0x10);
  4064. } else {
  4065. if (ha->type != GDT_PCIMPR) {
  4066. ctrt.type = (u8)((ha->stype<<4) + 6);
  4067. } else {
  4068. ctrt.type =
  4069. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4070. if (ha->stype >= 0x300)
  4071. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4072. else
  4073. ctrt.ext_type = 0x6000 | ha->stype;
  4074. }
  4075. ctrt.device_id = ha->pdev->device;
  4076. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4077. }
  4078. ctrt.info = ha->brd_phys;
  4079. ctrt.oem_id = ha->oem_id;
  4080. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4081. return -EFAULT;
  4082. break;
  4083. }
  4084. case GDTIOCTL_GENERAL:
  4085. return ioc_general(argp, cmnd);
  4086. case GDTIOCTL_EVENT:
  4087. return ioc_event(argp);
  4088. case GDTIOCTL_LOCKDRV:
  4089. return ioc_lockdrv(argp);
  4090. case GDTIOCTL_LOCKCHN:
  4091. {
  4092. gdth_ioctl_lockchn lchn;
  4093. u8 i, j;
  4094. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4095. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4096. return -EFAULT;
  4097. i = lchn.channel;
  4098. if (i < ha->bus_cnt) {
  4099. if (lchn.lock) {
  4100. spin_lock_irqsave(&ha->smp_lock, flags);
  4101. ha->raw[i].lock = 1;
  4102. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4103. for (j = 0; j < ha->tid_cnt; ++j)
  4104. gdth_wait_completion(ha, i, j);
  4105. } else {
  4106. spin_lock_irqsave(&ha->smp_lock, flags);
  4107. ha->raw[i].lock = 0;
  4108. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4109. for (j = 0; j < ha->tid_cnt; ++j)
  4110. gdth_next(ha);
  4111. }
  4112. }
  4113. break;
  4114. }
  4115. case GDTIOCTL_RESCAN:
  4116. return ioc_rescan(argp, cmnd);
  4117. case GDTIOCTL_HDRLIST:
  4118. return ioc_hdrlist(argp, cmnd);
  4119. case GDTIOCTL_RESET_BUS:
  4120. {
  4121. gdth_ioctl_reset res;
  4122. int rval;
  4123. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4124. (NULL == (ha = gdth_find_ha(res.ionode))))
  4125. return -EFAULT;
  4126. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4127. if (!scp)
  4128. return -ENOMEM;
  4129. scp->device = ha->sdev;
  4130. scp->cmd_len = 12;
  4131. scp->device->channel = res.number;
  4132. rval = gdth_eh_bus_reset(scp);
  4133. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4134. kfree(scp);
  4135. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4136. return -EFAULT;
  4137. break;
  4138. }
  4139. case GDTIOCTL_RESET_DRV:
  4140. return ioc_resetdrv(argp, cmnd);
  4141. default:
  4142. break;
  4143. }
  4144. return 0;
  4145. }
  4146. static long gdth_unlocked_ioctl(struct file *file, unsigned int cmd,
  4147. unsigned long arg)
  4148. {
  4149. int ret;
  4150. mutex_lock(&gdth_mutex);
  4151. ret = gdth_ioctl(file, cmd, arg);
  4152. mutex_unlock(&gdth_mutex);
  4153. return ret;
  4154. }
  4155. /* flush routine */
  4156. static void gdth_flush(gdth_ha_str *ha)
  4157. {
  4158. int i;
  4159. gdth_cmd_str gdtcmd;
  4160. char cmnd[MAX_COMMAND_SIZE];
  4161. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4162. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4163. for (i = 0; i < MAX_HDRIVES; ++i) {
  4164. if (ha->hdr[i].present) {
  4165. gdtcmd.BoardNode = LOCALBOARD;
  4166. gdtcmd.Service = CACHESERVICE;
  4167. gdtcmd.OpCode = GDT_FLUSH;
  4168. if (ha->cache_feat & GDT_64BIT) {
  4169. gdtcmd.u.cache64.DeviceNo = i;
  4170. gdtcmd.u.cache64.BlockNo = 1;
  4171. gdtcmd.u.cache64.sg_canz = 0;
  4172. } else {
  4173. gdtcmd.u.cache.DeviceNo = i;
  4174. gdtcmd.u.cache.BlockNo = 1;
  4175. gdtcmd.u.cache.sg_canz = 0;
  4176. }
  4177. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4178. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4179. }
  4180. }
  4181. }
  4182. /* configure lun */
  4183. static int gdth_slave_configure(struct scsi_device *sdev)
  4184. {
  4185. sdev->skip_ms_page_3f = 1;
  4186. sdev->skip_ms_page_8 = 1;
  4187. return 0;
  4188. }
  4189. static struct scsi_host_template gdth_template = {
  4190. .name = "GDT SCSI Disk Array Controller",
  4191. .info = gdth_info,
  4192. .queuecommand = gdth_queuecommand,
  4193. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4194. .slave_configure = gdth_slave_configure,
  4195. .bios_param = gdth_bios_param,
  4196. .show_info = gdth_show_info,
  4197. .write_info = gdth_set_info,
  4198. .eh_timed_out = gdth_timed_out,
  4199. .proc_name = "gdth",
  4200. .can_queue = GDTH_MAXCMDS,
  4201. .this_id = -1,
  4202. .sg_tablesize = GDTH_MAXSG,
  4203. .cmd_per_lun = GDTH_MAXC_P_L,
  4204. .unchecked_isa_dma = 1,
  4205. .use_clustering = ENABLE_CLUSTERING,
  4206. .no_write_same = 1,
  4207. };
  4208. #ifdef CONFIG_ISA
  4209. static int __init gdth_isa_probe_one(u32 isa_bios)
  4210. {
  4211. struct Scsi_Host *shp;
  4212. gdth_ha_str *ha;
  4213. dma_addr_t scratch_dma_handle = 0;
  4214. int error, i;
  4215. if (!gdth_search_isa(isa_bios))
  4216. return -ENXIO;
  4217. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4218. if (!shp)
  4219. return -ENOMEM;
  4220. ha = shost_priv(shp);
  4221. error = -ENODEV;
  4222. if (!gdth_init_isa(isa_bios,ha))
  4223. goto out_host_put;
  4224. /* controller found and initialized */
  4225. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4226. isa_bios, ha->irq, ha->drq);
  4227. error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha);
  4228. if (error) {
  4229. printk("GDT-ISA: Unable to allocate IRQ\n");
  4230. goto out_host_put;
  4231. }
  4232. error = request_dma(ha->drq, "gdth");
  4233. if (error) {
  4234. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4235. goto out_free_irq;
  4236. }
  4237. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4238. enable_dma(ha->drq);
  4239. shp->unchecked_isa_dma = 1;
  4240. shp->irq = ha->irq;
  4241. shp->dma_channel = ha->drq;
  4242. ha->hanum = gdth_ctr_count++;
  4243. ha->shost = shp;
  4244. ha->pccb = &ha->cmdext;
  4245. ha->ccb_phys = 0L;
  4246. ha->pdev = NULL;
  4247. error = -ENOMEM;
  4248. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4249. &scratch_dma_handle);
  4250. if (!ha->pscratch)
  4251. goto out_dec_counters;
  4252. ha->scratch_phys = scratch_dma_handle;
  4253. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4254. &scratch_dma_handle);
  4255. if (!ha->pmsg)
  4256. goto out_free_pscratch;
  4257. ha->msg_phys = scratch_dma_handle;
  4258. #ifdef INT_COAL
  4259. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4260. sizeof(gdth_coal_status) * MAXOFFSETS,
  4261. &scratch_dma_handle);
  4262. if (!ha->coal_stat)
  4263. goto out_free_pmsg;
  4264. ha->coal_stat_phys = scratch_dma_handle;
  4265. #endif
  4266. ha->scratch_busy = FALSE;
  4267. ha->req_first = NULL;
  4268. ha->tid_cnt = MAX_HDRIVES;
  4269. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4270. ha->tid_cnt = max_ids;
  4271. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4272. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4273. ha->scan_mode = rescan ? 0x10 : 0;
  4274. error = -ENODEV;
  4275. if (!gdth_search_drives(ha)) {
  4276. printk("GDT-ISA: Error during device scan\n");
  4277. goto out_free_coal_stat;
  4278. }
  4279. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4280. hdr_channel = ha->bus_cnt;
  4281. ha->virt_bus = hdr_channel;
  4282. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4283. shp->max_cmd_len = 16;
  4284. shp->max_id = ha->tid_cnt;
  4285. shp->max_lun = MAXLUN;
  4286. shp->max_channel = ha->bus_cnt;
  4287. spin_lock_init(&ha->smp_lock);
  4288. gdth_enable_int(ha);
  4289. error = scsi_add_host(shp, NULL);
  4290. if (error)
  4291. goto out_free_coal_stat;
  4292. list_add_tail(&ha->list, &gdth_instances);
  4293. gdth_timer_init();
  4294. scsi_scan_host(shp);
  4295. return 0;
  4296. out_free_coal_stat:
  4297. #ifdef INT_COAL
  4298. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4299. ha->coal_stat, ha->coal_stat_phys);
  4300. out_free_pmsg:
  4301. #endif
  4302. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4303. ha->pmsg, ha->msg_phys);
  4304. out_free_pscratch:
  4305. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4306. ha->pscratch, ha->scratch_phys);
  4307. out_dec_counters:
  4308. gdth_ctr_count--;
  4309. out_free_irq:
  4310. free_irq(ha->irq, ha);
  4311. out_host_put:
  4312. scsi_host_put(shp);
  4313. return error;
  4314. }
  4315. #endif /* CONFIG_ISA */
  4316. #ifdef CONFIG_EISA
  4317. static int __init gdth_eisa_probe_one(u16 eisa_slot)
  4318. {
  4319. struct Scsi_Host *shp;
  4320. gdth_ha_str *ha;
  4321. dma_addr_t scratch_dma_handle = 0;
  4322. int error, i;
  4323. if (!gdth_search_eisa(eisa_slot))
  4324. return -ENXIO;
  4325. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4326. if (!shp)
  4327. return -ENOMEM;
  4328. ha = shost_priv(shp);
  4329. error = -ENODEV;
  4330. if (!gdth_init_eisa(eisa_slot,ha))
  4331. goto out_host_put;
  4332. /* controller found and initialized */
  4333. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4334. eisa_slot >> 12, ha->irq);
  4335. error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha);
  4336. if (error) {
  4337. printk("GDT-EISA: Unable to allocate IRQ\n");
  4338. goto out_host_put;
  4339. }
  4340. shp->unchecked_isa_dma = 0;
  4341. shp->irq = ha->irq;
  4342. shp->dma_channel = 0xff;
  4343. ha->hanum = gdth_ctr_count++;
  4344. ha->shost = shp;
  4345. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4346. ha->pccb = &ha->cmdext;
  4347. ha->ccb_phys = 0L;
  4348. error = -ENOMEM;
  4349. ha->pdev = NULL;
  4350. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4351. &scratch_dma_handle);
  4352. if (!ha->pscratch)
  4353. goto out_free_irq;
  4354. ha->scratch_phys = scratch_dma_handle;
  4355. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4356. &scratch_dma_handle);
  4357. if (!ha->pmsg)
  4358. goto out_free_pscratch;
  4359. ha->msg_phys = scratch_dma_handle;
  4360. #ifdef INT_COAL
  4361. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4362. sizeof(gdth_coal_status) * MAXOFFSETS,
  4363. &scratch_dma_handle);
  4364. if (!ha->coal_stat)
  4365. goto out_free_pmsg;
  4366. ha->coal_stat_phys = scratch_dma_handle;
  4367. #endif
  4368. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4369. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4370. if (!ha->ccb_phys)
  4371. goto out_free_coal_stat;
  4372. ha->scratch_busy = FALSE;
  4373. ha->req_first = NULL;
  4374. ha->tid_cnt = MAX_HDRIVES;
  4375. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4376. ha->tid_cnt = max_ids;
  4377. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4378. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4379. ha->scan_mode = rescan ? 0x10 : 0;
  4380. if (!gdth_search_drives(ha)) {
  4381. printk("GDT-EISA: Error during device scan\n");
  4382. error = -ENODEV;
  4383. goto out_free_ccb_phys;
  4384. }
  4385. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4386. hdr_channel = ha->bus_cnt;
  4387. ha->virt_bus = hdr_channel;
  4388. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4389. shp->max_cmd_len = 16;
  4390. shp->max_id = ha->tid_cnt;
  4391. shp->max_lun = MAXLUN;
  4392. shp->max_channel = ha->bus_cnt;
  4393. spin_lock_init(&ha->smp_lock);
  4394. gdth_enable_int(ha);
  4395. error = scsi_add_host(shp, NULL);
  4396. if (error)
  4397. goto out_free_ccb_phys;
  4398. list_add_tail(&ha->list, &gdth_instances);
  4399. gdth_timer_init();
  4400. scsi_scan_host(shp);
  4401. return 0;
  4402. out_free_ccb_phys:
  4403. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4404. PCI_DMA_BIDIRECTIONAL);
  4405. out_free_coal_stat:
  4406. #ifdef INT_COAL
  4407. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4408. ha->coal_stat, ha->coal_stat_phys);
  4409. out_free_pmsg:
  4410. #endif
  4411. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4412. ha->pmsg, ha->msg_phys);
  4413. out_free_pscratch:
  4414. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4415. ha->pscratch, ha->scratch_phys);
  4416. out_free_irq:
  4417. free_irq(ha->irq, ha);
  4418. gdth_ctr_count--;
  4419. out_host_put:
  4420. scsi_host_put(shp);
  4421. return error;
  4422. }
  4423. #endif /* CONFIG_EISA */
  4424. #ifdef CONFIG_PCI
  4425. static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out)
  4426. {
  4427. struct Scsi_Host *shp;
  4428. gdth_ha_str *ha;
  4429. dma_addr_t scratch_dma_handle = 0;
  4430. int error, i;
  4431. struct pci_dev *pdev = pcistr->pdev;
  4432. *ha_out = NULL;
  4433. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4434. if (!shp)
  4435. return -ENOMEM;
  4436. ha = shost_priv(shp);
  4437. error = -ENODEV;
  4438. if (!gdth_init_pci(pdev, pcistr, ha))
  4439. goto out_host_put;
  4440. /* controller found and initialized */
  4441. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4442. pdev->bus->number,
  4443. PCI_SLOT(pdev->devfn),
  4444. ha->irq);
  4445. error = request_irq(ha->irq, gdth_interrupt,
  4446. IRQF_SHARED, "gdth", ha);
  4447. if (error) {
  4448. printk("GDT-PCI: Unable to allocate IRQ\n");
  4449. goto out_host_put;
  4450. }
  4451. shp->unchecked_isa_dma = 0;
  4452. shp->irq = ha->irq;
  4453. shp->dma_channel = 0xff;
  4454. ha->hanum = gdth_ctr_count++;
  4455. ha->shost = shp;
  4456. ha->pccb = &ha->cmdext;
  4457. ha->ccb_phys = 0L;
  4458. error = -ENOMEM;
  4459. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4460. &scratch_dma_handle);
  4461. if (!ha->pscratch)
  4462. goto out_free_irq;
  4463. ha->scratch_phys = scratch_dma_handle;
  4464. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4465. &scratch_dma_handle);
  4466. if (!ha->pmsg)
  4467. goto out_free_pscratch;
  4468. ha->msg_phys = scratch_dma_handle;
  4469. #ifdef INT_COAL
  4470. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4471. sizeof(gdth_coal_status) * MAXOFFSETS,
  4472. &scratch_dma_handle);
  4473. if (!ha->coal_stat)
  4474. goto out_free_pmsg;
  4475. ha->coal_stat_phys = scratch_dma_handle;
  4476. #endif
  4477. ha->scratch_busy = FALSE;
  4478. ha->req_first = NULL;
  4479. ha->tid_cnt = pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4480. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4481. ha->tid_cnt = max_ids;
  4482. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4483. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4484. ha->scan_mode = rescan ? 0x10 : 0;
  4485. error = -ENODEV;
  4486. if (!gdth_search_drives(ha)) {
  4487. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4488. goto out_free_coal_stat;
  4489. }
  4490. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4491. hdr_channel = ha->bus_cnt;
  4492. ha->virt_bus = hdr_channel;
  4493. /* 64-bit DMA only supported from FW >= x.43 */
  4494. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4495. !ha->dma64_support) {
  4496. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  4497. printk(KERN_WARNING "GDT-PCI %d: "
  4498. "Unable to set 32-bit DMA\n", ha->hanum);
  4499. goto out_free_coal_stat;
  4500. }
  4501. } else {
  4502. shp->max_cmd_len = 16;
  4503. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
  4504. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4505. } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  4506. printk(KERN_WARNING "GDT-PCI %d: "
  4507. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4508. goto out_free_coal_stat;
  4509. }
  4510. }
  4511. shp->max_id = ha->tid_cnt;
  4512. shp->max_lun = MAXLUN;
  4513. shp->max_channel = ha->bus_cnt;
  4514. spin_lock_init(&ha->smp_lock);
  4515. gdth_enable_int(ha);
  4516. error = scsi_add_host(shp, &pdev->dev);
  4517. if (error)
  4518. goto out_free_coal_stat;
  4519. list_add_tail(&ha->list, &gdth_instances);
  4520. pci_set_drvdata(ha->pdev, ha);
  4521. gdth_timer_init();
  4522. scsi_scan_host(shp);
  4523. *ha_out = ha;
  4524. return 0;
  4525. out_free_coal_stat:
  4526. #ifdef INT_COAL
  4527. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4528. ha->coal_stat, ha->coal_stat_phys);
  4529. out_free_pmsg:
  4530. #endif
  4531. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4532. ha->pmsg, ha->msg_phys);
  4533. out_free_pscratch:
  4534. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4535. ha->pscratch, ha->scratch_phys);
  4536. out_free_irq:
  4537. free_irq(ha->irq, ha);
  4538. gdth_ctr_count--;
  4539. out_host_put:
  4540. scsi_host_put(shp);
  4541. return error;
  4542. }
  4543. #endif /* CONFIG_PCI */
  4544. static void gdth_remove_one(gdth_ha_str *ha)
  4545. {
  4546. struct Scsi_Host *shp = ha->shost;
  4547. TRACE2(("gdth_remove_one()\n"));
  4548. scsi_remove_host(shp);
  4549. gdth_flush(ha);
  4550. if (ha->sdev) {
  4551. scsi_free_host_dev(ha->sdev);
  4552. ha->sdev = NULL;
  4553. }
  4554. if (shp->irq)
  4555. free_irq(shp->irq,ha);
  4556. #ifdef CONFIG_ISA
  4557. if (shp->dma_channel != 0xff)
  4558. free_dma(shp->dma_channel);
  4559. #endif
  4560. #ifdef INT_COAL
  4561. if (ha->coal_stat)
  4562. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4563. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4564. #endif
  4565. if (ha->pscratch)
  4566. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4567. ha->pscratch, ha->scratch_phys);
  4568. if (ha->pmsg)
  4569. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4570. ha->pmsg, ha->msg_phys);
  4571. if (ha->ccb_phys)
  4572. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4573. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4574. scsi_host_put(shp);
  4575. }
  4576. static int gdth_halt(struct notifier_block *nb, unsigned long event, void *buf)
  4577. {
  4578. gdth_ha_str *ha;
  4579. TRACE2(("gdth_halt() event %d\n", (int)event));
  4580. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4581. return NOTIFY_DONE;
  4582. list_for_each_entry(ha, &gdth_instances, list)
  4583. gdth_flush(ha);
  4584. return NOTIFY_OK;
  4585. }
  4586. static struct notifier_block gdth_notifier = {
  4587. gdth_halt, NULL, 0
  4588. };
  4589. static int __init gdth_init(void)
  4590. {
  4591. if (disable) {
  4592. printk("GDT-HA: Controller driver disabled from"
  4593. " command line !\n");
  4594. return 0;
  4595. }
  4596. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4597. GDTH_VERSION_STR);
  4598. /* initializations */
  4599. gdth_polling = TRUE;
  4600. gdth_clear_events();
  4601. init_timer(&gdth_timer);
  4602. /* As default we do not probe for EISA or ISA controllers */
  4603. if (probe_eisa_isa) {
  4604. /* scanning for controllers, at first: ISA controller */
  4605. #ifdef CONFIG_ISA
  4606. u32 isa_bios;
  4607. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4608. isa_bios += 0x8000UL)
  4609. gdth_isa_probe_one(isa_bios);
  4610. #endif
  4611. #ifdef CONFIG_EISA
  4612. {
  4613. u16 eisa_slot;
  4614. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4615. eisa_slot += 0x1000)
  4616. gdth_eisa_probe_one(eisa_slot);
  4617. }
  4618. #endif
  4619. }
  4620. #ifdef CONFIG_PCI
  4621. /* scanning for PCI controllers */
  4622. if (pci_register_driver(&gdth_pci_driver)) {
  4623. gdth_ha_str *ha;
  4624. list_for_each_entry(ha, &gdth_instances, list)
  4625. gdth_remove_one(ha);
  4626. return -ENODEV;
  4627. }
  4628. #endif /* CONFIG_PCI */
  4629. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4630. major = register_chrdev(0,"gdth", &gdth_fops);
  4631. register_reboot_notifier(&gdth_notifier);
  4632. gdth_polling = FALSE;
  4633. return 0;
  4634. }
  4635. static void __exit gdth_exit(void)
  4636. {
  4637. gdth_ha_str *ha;
  4638. unregister_chrdev(major, "gdth");
  4639. unregister_reboot_notifier(&gdth_notifier);
  4640. #ifdef GDTH_STATISTICS
  4641. del_timer_sync(&gdth_timer);
  4642. #endif
  4643. #ifdef CONFIG_PCI
  4644. pci_unregister_driver(&gdth_pci_driver);
  4645. #endif
  4646. list_for_each_entry(ha, &gdth_instances, list)
  4647. gdth_remove_one(ha);
  4648. }
  4649. module_init(gdth_init);
  4650. module_exit(gdth_exit);
  4651. #ifndef MODULE
  4652. __setup("gdth=", option_setup);
  4653. #endif