vnic_wq.h 4.7 KB

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  1. /*
  2. * Copyright 2008 Cisco Systems, Inc. All rights reserved.
  3. * Copyright 2007 Nuova Systems, Inc. All rights reserved.
  4. *
  5. * This program is free software; you may redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  10. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  11. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  12. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  13. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  14. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  15. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  16. * SOFTWARE.
  17. */
  18. #ifndef _VNIC_WQ_H_
  19. #define _VNIC_WQ_H_
  20. #include <linux/pci.h>
  21. #include "vnic_dev.h"
  22. #include "vnic_cq.h"
  23. /*
  24. * These defines avoid symbol clash between fnic and enic (Cisco 10G Eth
  25. * Driver) when both are built with CONFIG options =y
  26. */
  27. #define vnic_wq_desc_avail fnic_wq_desc_avail
  28. #define vnic_wq_desc_used fnic_wq_desc_used
  29. #define vnic_wq_next_desc fni_cwq_next_desc
  30. #define vnic_wq_post fnic_wq_post
  31. #define vnic_wq_service fnic_wq_service
  32. #define vnic_wq_free fnic_wq_free
  33. #define vnic_wq_alloc fnic_wq_alloc
  34. #define vnic_wq_init fnic_wq_init
  35. #define vnic_wq_error_status fnic_wq_error_status
  36. #define vnic_wq_enable fnic_wq_enable
  37. #define vnic_wq_disable fnic_wq_disable
  38. #define vnic_wq_clean fnic_wq_clean
  39. /* Work queue control */
  40. struct vnic_wq_ctrl {
  41. u64 ring_base; /* 0x00 */
  42. u32 ring_size; /* 0x08 */
  43. u32 pad0;
  44. u32 posted_index; /* 0x10 */
  45. u32 pad1;
  46. u32 cq_index; /* 0x18 */
  47. u32 pad2;
  48. u32 enable; /* 0x20 */
  49. u32 pad3;
  50. u32 running; /* 0x28 */
  51. u32 pad4;
  52. u32 fetch_index; /* 0x30 */
  53. u32 pad5;
  54. u32 dca_value; /* 0x38 */
  55. u32 pad6;
  56. u32 error_interrupt_enable; /* 0x40 */
  57. u32 pad7;
  58. u32 error_interrupt_offset; /* 0x48 */
  59. u32 pad8;
  60. u32 error_status; /* 0x50 */
  61. u32 pad9;
  62. };
  63. struct vnic_wq_buf {
  64. struct vnic_wq_buf *next;
  65. dma_addr_t dma_addr;
  66. void *os_buf;
  67. unsigned int len;
  68. unsigned int index;
  69. int sop;
  70. void *desc;
  71. };
  72. /* Break the vnic_wq_buf allocations into blocks of 64 entries */
  73. #define VNIC_WQ_BUF_BLK_ENTRIES 64
  74. #define VNIC_WQ_BUF_BLK_SZ \
  75. (VNIC_WQ_BUF_BLK_ENTRIES * sizeof(struct vnic_wq_buf))
  76. #define VNIC_WQ_BUF_BLKS_NEEDED(entries) \
  77. DIV_ROUND_UP(entries, VNIC_WQ_BUF_BLK_ENTRIES)
  78. #define VNIC_WQ_BUF_BLKS_MAX VNIC_WQ_BUF_BLKS_NEEDED(4096)
  79. struct vnic_wq {
  80. unsigned int index;
  81. struct vnic_dev *vdev;
  82. struct vnic_wq_ctrl __iomem *ctrl; /* memory-mapped */
  83. struct vnic_dev_ring ring;
  84. struct vnic_wq_buf *bufs[VNIC_WQ_BUF_BLKS_MAX];
  85. struct vnic_wq_buf *to_use;
  86. struct vnic_wq_buf *to_clean;
  87. unsigned int pkts_outstanding;
  88. };
  89. static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
  90. {
  91. /* how many does SW own? */
  92. return wq->ring.desc_avail;
  93. }
  94. static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
  95. {
  96. /* how many does HW own? */
  97. return wq->ring.desc_count - wq->ring.desc_avail - 1;
  98. }
  99. static inline void *vnic_wq_next_desc(struct vnic_wq *wq)
  100. {
  101. return wq->to_use->desc;
  102. }
  103. static inline void vnic_wq_post(struct vnic_wq *wq,
  104. void *os_buf, dma_addr_t dma_addr,
  105. unsigned int len, int sop, int eop)
  106. {
  107. struct vnic_wq_buf *buf = wq->to_use;
  108. buf->sop = sop;
  109. buf->os_buf = eop ? os_buf : NULL;
  110. buf->dma_addr = dma_addr;
  111. buf->len = len;
  112. buf = buf->next;
  113. if (eop) {
  114. /* Adding write memory barrier prevents compiler and/or CPU
  115. * reordering, thus avoiding descriptor posting before
  116. * descriptor is initialized. Otherwise, hardware can read
  117. * stale descriptor fields.
  118. */
  119. wmb();
  120. iowrite32(buf->index, &wq->ctrl->posted_index);
  121. }
  122. wq->to_use = buf;
  123. wq->ring.desc_avail--;
  124. }
  125. static inline void vnic_wq_service(struct vnic_wq *wq,
  126. struct cq_desc *cq_desc, u16 completed_index,
  127. void (*buf_service)(struct vnic_wq *wq,
  128. struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque),
  129. void *opaque)
  130. {
  131. struct vnic_wq_buf *buf;
  132. buf = wq->to_clean;
  133. while (1) {
  134. (*buf_service)(wq, cq_desc, buf, opaque);
  135. wq->ring.desc_avail++;
  136. wq->to_clean = buf->next;
  137. if (buf->index == completed_index)
  138. break;
  139. buf = wq->to_clean;
  140. }
  141. }
  142. void vnic_wq_free(struct vnic_wq *wq);
  143. int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,
  144. unsigned int desc_count, unsigned int desc_size);
  145. void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
  146. unsigned int error_interrupt_enable,
  147. unsigned int error_interrupt_offset);
  148. unsigned int vnic_wq_error_status(struct vnic_wq *wq);
  149. void vnic_wq_enable(struct vnic_wq *wq);
  150. int vnic_wq_disable(struct vnic_wq *wq);
  151. void vnic_wq_clean(struct vnic_wq *wq,
  152. void (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf));
  153. #endif /* _VNIC_WQ_H_ */