vnic_rq.h 6.1 KB

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  1. /*
  2. * Copyright 2008 Cisco Systems, Inc. All rights reserved.
  3. * Copyright 2007 Nuova Systems, Inc. All rights reserved.
  4. *
  5. * This program is free software; you may redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  10. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  11. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  12. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  13. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  14. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  15. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  16. * SOFTWARE.
  17. */
  18. #ifndef _VNIC_RQ_H_
  19. #define _VNIC_RQ_H_
  20. #include <linux/pci.h>
  21. #include "vnic_dev.h"
  22. #include "vnic_cq.h"
  23. /*
  24. * These defines avoid symbol clash between fnic and enic (Cisco 10G Eth
  25. * Driver) when both are built with CONFIG options =y
  26. */
  27. #define vnic_rq_desc_avail fnic_rq_desc_avail
  28. #define vnic_rq_desc_used fnic_rq_desc_used
  29. #define vnic_rq_next_desc fnic_rq_next_desc
  30. #define vnic_rq_next_index fnic_rq_next_index
  31. #define vnic_rq_next_buf_index fnic_rq_next_buf_index
  32. #define vnic_rq_post fnic_rq_post
  33. #define vnic_rq_posting_soon fnic_rq_posting_soon
  34. #define vnic_rq_return_descs fnic_rq_return_descs
  35. #define vnic_rq_service fnic_rq_service
  36. #define vnic_rq_fill fnic_rq_fill
  37. #define vnic_rq_free fnic_rq_free
  38. #define vnic_rq_alloc fnic_rq_alloc
  39. #define vnic_rq_init fnic_rq_init
  40. #define vnic_rq_error_status fnic_rq_error_status
  41. #define vnic_rq_enable fnic_rq_enable
  42. #define vnic_rq_disable fnic_rq_disable
  43. #define vnic_rq_clean fnic_rq_clean
  44. /* Receive queue control */
  45. struct vnic_rq_ctrl {
  46. u64 ring_base; /* 0x00 */
  47. u32 ring_size; /* 0x08 */
  48. u32 pad0;
  49. u32 posted_index; /* 0x10 */
  50. u32 pad1;
  51. u32 cq_index; /* 0x18 */
  52. u32 pad2;
  53. u32 enable; /* 0x20 */
  54. u32 pad3;
  55. u32 running; /* 0x28 */
  56. u32 pad4;
  57. u32 fetch_index; /* 0x30 */
  58. u32 pad5;
  59. u32 error_interrupt_enable; /* 0x38 */
  60. u32 pad6;
  61. u32 error_interrupt_offset; /* 0x40 */
  62. u32 pad7;
  63. u32 error_status; /* 0x48 */
  64. u32 pad8;
  65. u32 dropped_packet_count; /* 0x50 */
  66. u32 pad9;
  67. u32 dropped_packet_count_rc; /* 0x58 */
  68. u32 pad10;
  69. };
  70. /* Break the vnic_rq_buf allocations into blocks of 64 entries */
  71. #define VNIC_RQ_BUF_BLK_ENTRIES 64
  72. #define VNIC_RQ_BUF_BLK_SZ \
  73. (VNIC_RQ_BUF_BLK_ENTRIES * sizeof(struct vnic_rq_buf))
  74. #define VNIC_RQ_BUF_BLKS_NEEDED(entries) \
  75. DIV_ROUND_UP(entries, VNIC_RQ_BUF_BLK_ENTRIES)
  76. #define VNIC_RQ_BUF_BLKS_MAX VNIC_RQ_BUF_BLKS_NEEDED(4096)
  77. struct vnic_rq_buf {
  78. struct vnic_rq_buf *next;
  79. dma_addr_t dma_addr;
  80. void *os_buf;
  81. unsigned int os_buf_index;
  82. unsigned int len;
  83. unsigned int index;
  84. void *desc;
  85. };
  86. struct vnic_rq {
  87. unsigned int index;
  88. struct vnic_dev *vdev;
  89. struct vnic_rq_ctrl __iomem *ctrl; /* memory-mapped */
  90. struct vnic_dev_ring ring;
  91. struct vnic_rq_buf *bufs[VNIC_RQ_BUF_BLKS_MAX];
  92. struct vnic_rq_buf *to_use;
  93. struct vnic_rq_buf *to_clean;
  94. void *os_buf_head;
  95. unsigned int buf_index;
  96. unsigned int pkts_outstanding;
  97. };
  98. static inline unsigned int vnic_rq_desc_avail(struct vnic_rq *rq)
  99. {
  100. /* how many does SW own? */
  101. return rq->ring.desc_avail;
  102. }
  103. static inline unsigned int vnic_rq_desc_used(struct vnic_rq *rq)
  104. {
  105. /* how many does HW own? */
  106. return rq->ring.desc_count - rq->ring.desc_avail - 1;
  107. }
  108. static inline void *vnic_rq_next_desc(struct vnic_rq *rq)
  109. {
  110. return rq->to_use->desc;
  111. }
  112. static inline unsigned int vnic_rq_next_index(struct vnic_rq *rq)
  113. {
  114. return rq->to_use->index;
  115. }
  116. static inline unsigned int vnic_rq_next_buf_index(struct vnic_rq *rq)
  117. {
  118. return rq->buf_index++;
  119. }
  120. static inline void vnic_rq_post(struct vnic_rq *rq,
  121. void *os_buf, unsigned int os_buf_index,
  122. dma_addr_t dma_addr, unsigned int len)
  123. {
  124. struct vnic_rq_buf *buf = rq->to_use;
  125. buf->os_buf = os_buf;
  126. buf->os_buf_index = os_buf_index;
  127. buf->dma_addr = dma_addr;
  128. buf->len = len;
  129. buf = buf->next;
  130. rq->to_use = buf;
  131. rq->ring.desc_avail--;
  132. /* Move the posted_index every nth descriptor
  133. */
  134. #ifndef VNIC_RQ_RETURN_RATE
  135. #define VNIC_RQ_RETURN_RATE 0xf /* keep 2^n - 1 */
  136. #endif
  137. if ((buf->index & VNIC_RQ_RETURN_RATE) == 0) {
  138. /* Adding write memory barrier prevents compiler and/or CPU
  139. * reordering, thus avoiding descriptor posting before
  140. * descriptor is initialized. Otherwise, hardware can read
  141. * stale descriptor fields.
  142. */
  143. wmb();
  144. iowrite32(buf->index, &rq->ctrl->posted_index);
  145. }
  146. }
  147. static inline int vnic_rq_posting_soon(struct vnic_rq *rq)
  148. {
  149. return (rq->to_use->index & VNIC_RQ_RETURN_RATE) == 0;
  150. }
  151. static inline void vnic_rq_return_descs(struct vnic_rq *rq, unsigned int count)
  152. {
  153. rq->ring.desc_avail += count;
  154. }
  155. enum desc_return_options {
  156. VNIC_RQ_RETURN_DESC,
  157. VNIC_RQ_DEFER_RETURN_DESC,
  158. };
  159. static inline void vnic_rq_service(struct vnic_rq *rq,
  160. struct cq_desc *cq_desc, u16 completed_index,
  161. int desc_return, void (*buf_service)(struct vnic_rq *rq,
  162. struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
  163. int skipped, void *opaque), void *opaque)
  164. {
  165. struct vnic_rq_buf *buf;
  166. int skipped;
  167. buf = rq->to_clean;
  168. while (1) {
  169. skipped = (buf->index != completed_index);
  170. (*buf_service)(rq, cq_desc, buf, skipped, opaque);
  171. if (desc_return == VNIC_RQ_RETURN_DESC)
  172. rq->ring.desc_avail++;
  173. rq->to_clean = buf->next;
  174. if (!skipped)
  175. break;
  176. buf = rq->to_clean;
  177. }
  178. }
  179. static inline int vnic_rq_fill(struct vnic_rq *rq,
  180. int (*buf_fill)(struct vnic_rq *rq))
  181. {
  182. int err;
  183. while (vnic_rq_desc_avail(rq) > 1) {
  184. err = (*buf_fill)(rq);
  185. if (err)
  186. return err;
  187. }
  188. return 0;
  189. }
  190. void vnic_rq_free(struct vnic_rq *rq);
  191. int vnic_rq_alloc(struct vnic_dev *vdev, struct vnic_rq *rq, unsigned int index,
  192. unsigned int desc_count, unsigned int desc_size);
  193. void vnic_rq_init(struct vnic_rq *rq, unsigned int cq_index,
  194. unsigned int error_interrupt_enable,
  195. unsigned int error_interrupt_offset);
  196. unsigned int vnic_rq_error_status(struct vnic_rq *rq);
  197. void vnic_rq_enable(struct vnic_rq *rq);
  198. int vnic_rq_disable(struct vnic_rq *rq);
  199. void vnic_rq_clean(struct vnic_rq *rq,
  200. void (*buf_clean)(struct vnic_rq *rq, struct vnic_rq_buf *buf));
  201. #endif /* _VNIC_RQ_H_ */