pinctrl-spmi-mpp.c 24 KB

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  1. /*
  2. * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/gpio.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/pinctrl/pinconf-generic.h>
  18. #include <linux/pinctrl/pinconf.h>
  19. #include <linux/pinctrl/pinmux.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/regmap.h>
  22. #include <linux/slab.h>
  23. #include <linux/types.h>
  24. #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
  25. #include "../core.h"
  26. #include "../pinctrl-utils.h"
  27. #define PMIC_MPP_ADDRESS_RANGE 0x100
  28. /*
  29. * Pull Up Values - it indicates whether a pull-up should be
  30. * applied for bidirectional mode only. The hardware ignores the
  31. * configuration when operating in other modes.
  32. */
  33. #define PMIC_MPP_PULL_UP_0P6KOHM 0
  34. #define PMIC_MPP_PULL_UP_10KOHM 1
  35. #define PMIC_MPP_PULL_UP_30KOHM 2
  36. #define PMIC_MPP_PULL_UP_OPEN 3
  37. /* type registers base address bases */
  38. #define PMIC_MPP_REG_TYPE 0x4
  39. #define PMIC_MPP_REG_SUBTYPE 0x5
  40. /* mpp peripheral type and subtype values */
  41. #define PMIC_MPP_TYPE 0x11
  42. #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3
  43. #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4
  44. #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5
  45. #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6
  46. #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7
  47. #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf
  48. #define PMIC_MPP_REG_RT_STS 0x10
  49. #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
  50. /* control register base address bases */
  51. #define PMIC_MPP_REG_MODE_CTL 0x40
  52. #define PMIC_MPP_REG_DIG_VIN_CTL 0x41
  53. #define PMIC_MPP_REG_DIG_PULL_CTL 0x42
  54. #define PMIC_MPP_REG_DIG_IN_CTL 0x43
  55. #define PMIC_MPP_REG_EN_CTL 0x46
  56. #define PMIC_MPP_REG_AOUT_CTL 0x48
  57. #define PMIC_MPP_REG_AIN_CTL 0x4a
  58. #define PMIC_MPP_REG_SINK_CTL 0x4c
  59. /* PMIC_MPP_REG_MODE_CTL */
  60. #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1
  61. #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1
  62. #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7
  63. #define PMIC_MPP_REG_MODE_DIR_SHIFT 4
  64. #define PMIC_MPP_REG_MODE_DIR_MASK 0x7
  65. /* PMIC_MPP_REG_DIG_VIN_CTL */
  66. #define PMIC_MPP_REG_VIN_SHIFT 0
  67. #define PMIC_MPP_REG_VIN_MASK 0x7
  68. /* PMIC_MPP_REG_DIG_PULL_CTL */
  69. #define PMIC_MPP_REG_PULL_SHIFT 0
  70. #define PMIC_MPP_REG_PULL_MASK 0x7
  71. /* PMIC_MPP_REG_EN_CTL */
  72. #define PMIC_MPP_REG_MASTER_EN_SHIFT 7
  73. /* PMIC_MPP_REG_AIN_CTL */
  74. #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0
  75. #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7
  76. #define PMIC_MPP_MODE_DIGITAL_INPUT 0
  77. #define PMIC_MPP_MODE_DIGITAL_OUTPUT 1
  78. #define PMIC_MPP_MODE_DIGITAL_BIDIR 2
  79. #define PMIC_MPP_MODE_ANALOG_BIDIR 3
  80. #define PMIC_MPP_MODE_ANALOG_INPUT 4
  81. #define PMIC_MPP_MODE_ANALOG_OUTPUT 5
  82. #define PMIC_MPP_MODE_CURRENT_SINK 6
  83. #define PMIC_MPP_SELECTOR_NORMAL 0
  84. #define PMIC_MPP_SELECTOR_PAIRED 1
  85. #define PMIC_MPP_SELECTOR_DTEST_FIRST 4
  86. #define PMIC_MPP_PHYSICAL_OFFSET 1
  87. /* Qualcomm specific pin configurations */
  88. #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1)
  89. #define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2)
  90. #define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3)
  91. #define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4)
  92. /**
  93. * struct pmic_mpp_pad - keep current MPP settings
  94. * @base: Address base in SPMI device.
  95. * @irq: IRQ number which this MPP generate.
  96. * @is_enabled: Set to false when MPP should be put in high Z state.
  97. * @out_value: Cached pin output value.
  98. * @output_enabled: Set to true if MPP output logic is enabled.
  99. * @input_enabled: Set to true if MPP input buffer logic is enabled.
  100. * @paired: Pin operates in paired mode
  101. * @has_pullup: Pin has support to configure pullup
  102. * @num_sources: Number of power-sources supported by this MPP.
  103. * @power_source: Current power-source used.
  104. * @amux_input: Set the source for analog input.
  105. * @aout_level: Analog output level
  106. * @pullup: Pullup resistor value. Valid in Bidirectional mode only.
  107. * @function: See pmic_mpp_functions[].
  108. * @drive_strength: Amount of current in sink mode
  109. * @dtest: DTEST route selector
  110. */
  111. struct pmic_mpp_pad {
  112. u16 base;
  113. int irq;
  114. bool is_enabled;
  115. bool out_value;
  116. bool output_enabled;
  117. bool input_enabled;
  118. bool paired;
  119. bool has_pullup;
  120. unsigned int num_sources;
  121. unsigned int power_source;
  122. unsigned int amux_input;
  123. unsigned int aout_level;
  124. unsigned int pullup;
  125. unsigned int function;
  126. unsigned int drive_strength;
  127. unsigned int dtest;
  128. };
  129. struct pmic_mpp_state {
  130. struct device *dev;
  131. struct regmap *map;
  132. struct pinctrl_dev *ctrl;
  133. struct gpio_chip chip;
  134. };
  135. static const struct pinconf_generic_params pmic_mpp_bindings[] = {
  136. {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0},
  137. {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0},
  138. {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0},
  139. {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0},
  140. };
  141. #ifdef CONFIG_DEBUG_FS
  142. static const struct pin_config_item pmic_conf_items[] = {
  143. PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true),
  144. PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true),
  145. PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true),
  146. PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false),
  147. };
  148. #endif
  149. static const char *const pmic_mpp_groups[] = {
  150. "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8",
  151. };
  152. #define PMIC_MPP_DIGITAL 0
  153. #define PMIC_MPP_ANALOG 1
  154. #define PMIC_MPP_SINK 2
  155. static const char *const pmic_mpp_functions[] = {
  156. "digital", "analog", "sink"
  157. };
  158. static int pmic_mpp_read(struct pmic_mpp_state *state,
  159. struct pmic_mpp_pad *pad, unsigned int addr)
  160. {
  161. unsigned int val;
  162. int ret;
  163. ret = regmap_read(state->map, pad->base + addr, &val);
  164. if (ret < 0)
  165. dev_err(state->dev, "read 0x%x failed\n", addr);
  166. else
  167. ret = val;
  168. return ret;
  169. }
  170. static int pmic_mpp_write(struct pmic_mpp_state *state,
  171. struct pmic_mpp_pad *pad, unsigned int addr,
  172. unsigned int val)
  173. {
  174. int ret;
  175. ret = regmap_write(state->map, pad->base + addr, val);
  176. if (ret < 0)
  177. dev_err(state->dev, "write 0x%x failed\n", addr);
  178. return ret;
  179. }
  180. static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev)
  181. {
  182. /* Every PIN is a group */
  183. return pctldev->desc->npins;
  184. }
  185. static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev,
  186. unsigned pin)
  187. {
  188. return pctldev->desc->pins[pin].name;
  189. }
  190. static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev,
  191. unsigned pin,
  192. const unsigned **pins, unsigned *num_pins)
  193. {
  194. *pins = &pctldev->desc->pins[pin].number;
  195. *num_pins = 1;
  196. return 0;
  197. }
  198. static const struct pinctrl_ops pmic_mpp_pinctrl_ops = {
  199. .get_groups_count = pmic_mpp_get_groups_count,
  200. .get_group_name = pmic_mpp_get_group_name,
  201. .get_group_pins = pmic_mpp_get_group_pins,
  202. .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
  203. .dt_free_map = pinctrl_utils_free_map,
  204. };
  205. static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev)
  206. {
  207. return ARRAY_SIZE(pmic_mpp_functions);
  208. }
  209. static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev,
  210. unsigned function)
  211. {
  212. return pmic_mpp_functions[function];
  213. }
  214. static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev,
  215. unsigned function,
  216. const char *const **groups,
  217. unsigned *const num_qgroups)
  218. {
  219. *groups = pmic_mpp_groups;
  220. *num_qgroups = pctldev->desc->npins;
  221. return 0;
  222. }
  223. static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state,
  224. struct pmic_mpp_pad *pad)
  225. {
  226. unsigned int mode;
  227. unsigned int sel;
  228. unsigned int val;
  229. unsigned int en;
  230. switch (pad->function) {
  231. case PMIC_MPP_ANALOG:
  232. if (pad->input_enabled && pad->output_enabled)
  233. mode = PMIC_MPP_MODE_ANALOG_BIDIR;
  234. else if (pad->input_enabled)
  235. mode = PMIC_MPP_MODE_ANALOG_INPUT;
  236. else
  237. mode = PMIC_MPP_MODE_ANALOG_OUTPUT;
  238. break;
  239. case PMIC_MPP_DIGITAL:
  240. if (pad->input_enabled && pad->output_enabled)
  241. mode = PMIC_MPP_MODE_DIGITAL_BIDIR;
  242. else if (pad->input_enabled)
  243. mode = PMIC_MPP_MODE_DIGITAL_INPUT;
  244. else
  245. mode = PMIC_MPP_MODE_DIGITAL_OUTPUT;
  246. break;
  247. case PMIC_MPP_SINK:
  248. default:
  249. mode = PMIC_MPP_MODE_CURRENT_SINK;
  250. break;
  251. }
  252. if (pad->dtest)
  253. sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1;
  254. else if (pad->paired)
  255. sel = PMIC_MPP_SELECTOR_PAIRED;
  256. else
  257. sel = PMIC_MPP_SELECTOR_NORMAL;
  258. en = !!pad->out_value;
  259. val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT |
  260. sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT |
  261. en;
  262. return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
  263. }
  264. static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function,
  265. unsigned pin)
  266. {
  267. struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
  268. struct pmic_mpp_pad *pad;
  269. unsigned int val;
  270. int ret;
  271. pad = pctldev->desc->pins[pin].drv_data;
  272. pad->function = function;
  273. ret = pmic_mpp_write_mode_ctl(state, pad);
  274. val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
  275. return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
  276. }
  277. static const struct pinmux_ops pmic_mpp_pinmux_ops = {
  278. .get_functions_count = pmic_mpp_get_functions_count,
  279. .get_function_name = pmic_mpp_get_function_name,
  280. .get_function_groups = pmic_mpp_get_function_groups,
  281. .set_mux = pmic_mpp_set_mux,
  282. };
  283. static int pmic_mpp_config_get(struct pinctrl_dev *pctldev,
  284. unsigned int pin, unsigned long *config)
  285. {
  286. unsigned param = pinconf_to_config_param(*config);
  287. struct pmic_mpp_pad *pad;
  288. unsigned arg = 0;
  289. pad = pctldev->desc->pins[pin].drv_data;
  290. switch (param) {
  291. case PIN_CONFIG_BIAS_DISABLE:
  292. arg = pad->pullup == PMIC_MPP_PULL_UP_OPEN;
  293. break;
  294. case PIN_CONFIG_BIAS_PULL_UP:
  295. switch (pad->pullup) {
  296. case PMIC_MPP_PULL_UP_OPEN:
  297. arg = 0;
  298. break;
  299. case PMIC_MPP_PULL_UP_0P6KOHM:
  300. arg = 600;
  301. break;
  302. case PMIC_MPP_PULL_UP_10KOHM:
  303. arg = 10000;
  304. break;
  305. case PMIC_MPP_PULL_UP_30KOHM:
  306. arg = 30000;
  307. break;
  308. default:
  309. return -EINVAL;
  310. }
  311. break;
  312. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  313. arg = !pad->is_enabled;
  314. break;
  315. case PIN_CONFIG_POWER_SOURCE:
  316. arg = pad->power_source;
  317. break;
  318. case PIN_CONFIG_INPUT_ENABLE:
  319. arg = pad->input_enabled;
  320. break;
  321. case PIN_CONFIG_OUTPUT:
  322. arg = pad->out_value;
  323. break;
  324. case PMIC_MPP_CONF_DTEST_SELECTOR:
  325. arg = pad->dtest;
  326. break;
  327. case PMIC_MPP_CONF_AMUX_ROUTE:
  328. arg = pad->amux_input;
  329. break;
  330. case PMIC_MPP_CONF_PAIRED:
  331. arg = pad->paired;
  332. break;
  333. case PIN_CONFIG_DRIVE_STRENGTH:
  334. arg = pad->drive_strength;
  335. break;
  336. case PMIC_MPP_CONF_ANALOG_LEVEL:
  337. arg = pad->aout_level;
  338. break;
  339. default:
  340. return -EINVAL;
  341. }
  342. /* Convert register value to pinconf value */
  343. *config = pinconf_to_config_packed(param, arg);
  344. return 0;
  345. }
  346. static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
  347. unsigned long *configs, unsigned nconfs)
  348. {
  349. struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
  350. struct pmic_mpp_pad *pad;
  351. unsigned param, arg;
  352. unsigned int val;
  353. int i, ret;
  354. pad = pctldev->desc->pins[pin].drv_data;
  355. /* Make it possible to enable the pin, by not setting high impedance */
  356. pad->is_enabled = true;
  357. for (i = 0; i < nconfs; i++) {
  358. param = pinconf_to_config_param(configs[i]);
  359. arg = pinconf_to_config_argument(configs[i]);
  360. switch (param) {
  361. case PIN_CONFIG_BIAS_DISABLE:
  362. pad->pullup = PMIC_MPP_PULL_UP_OPEN;
  363. break;
  364. case PIN_CONFIG_BIAS_PULL_UP:
  365. switch (arg) {
  366. case 600:
  367. pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM;
  368. break;
  369. case 10000:
  370. pad->pullup = PMIC_MPP_PULL_UP_10KOHM;
  371. break;
  372. case 30000:
  373. pad->pullup = PMIC_MPP_PULL_UP_30KOHM;
  374. break;
  375. default:
  376. return -EINVAL;
  377. }
  378. break;
  379. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  380. pad->is_enabled = false;
  381. break;
  382. case PIN_CONFIG_POWER_SOURCE:
  383. if (arg >= pad->num_sources)
  384. return -EINVAL;
  385. pad->power_source = arg;
  386. break;
  387. case PIN_CONFIG_INPUT_ENABLE:
  388. pad->input_enabled = arg ? true : false;
  389. break;
  390. case PIN_CONFIG_OUTPUT:
  391. pad->output_enabled = true;
  392. pad->out_value = arg;
  393. break;
  394. case PMIC_MPP_CONF_DTEST_SELECTOR:
  395. pad->dtest = arg;
  396. break;
  397. case PIN_CONFIG_DRIVE_STRENGTH:
  398. arg = pad->drive_strength;
  399. break;
  400. case PMIC_MPP_CONF_AMUX_ROUTE:
  401. if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4)
  402. return -EINVAL;
  403. pad->amux_input = arg;
  404. break;
  405. case PMIC_MPP_CONF_ANALOG_LEVEL:
  406. pad->aout_level = arg;
  407. break;
  408. case PMIC_MPP_CONF_PAIRED:
  409. pad->paired = !!arg;
  410. break;
  411. default:
  412. return -EINVAL;
  413. }
  414. }
  415. val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT;
  416. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val);
  417. if (ret < 0)
  418. return ret;
  419. if (pad->has_pullup) {
  420. val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
  421. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL,
  422. val);
  423. if (ret < 0)
  424. return ret;
  425. }
  426. val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK;
  427. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val);
  428. if (ret < 0)
  429. return ret;
  430. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level);
  431. if (ret < 0)
  432. return ret;
  433. ret = pmic_mpp_write_mode_ctl(state, pad);
  434. if (ret < 0)
  435. return ret;
  436. val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
  437. return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
  438. }
  439. static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
  440. struct seq_file *s, unsigned pin)
  441. {
  442. struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
  443. struct pmic_mpp_pad *pad;
  444. int ret;
  445. static const char *const biases[] = {
  446. "0.6kOhm", "10kOhm", "30kOhm", "Disabled"
  447. };
  448. pad = pctldev->desc->pins[pin].drv_data;
  449. seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET);
  450. if (!pad->is_enabled) {
  451. seq_puts(s, " ---");
  452. } else {
  453. if (pad->input_enabled) {
  454. ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
  455. if (ret < 0)
  456. return;
  457. ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
  458. pad->out_value = ret;
  459. }
  460. seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
  461. seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]);
  462. seq_printf(s, " vin-%d", pad->power_source);
  463. seq_printf(s, " %d", pad->aout_level);
  464. if (pad->has_pullup)
  465. seq_printf(s, " %-8s", biases[pad->pullup]);
  466. seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
  467. if (pad->dtest)
  468. seq_printf(s, " dtest%d", pad->dtest);
  469. if (pad->paired)
  470. seq_puts(s, " paired");
  471. }
  472. }
  473. static const struct pinconf_ops pmic_mpp_pinconf_ops = {
  474. .is_generic = true,
  475. .pin_config_group_get = pmic_mpp_config_get,
  476. .pin_config_group_set = pmic_mpp_config_set,
  477. .pin_config_group_dbg_show = pmic_mpp_config_dbg_show,
  478. };
  479. static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin)
  480. {
  481. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  482. unsigned long config;
  483. config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
  484. return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
  485. }
  486. static int pmic_mpp_direction_output(struct gpio_chip *chip,
  487. unsigned pin, int val)
  488. {
  489. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  490. unsigned long config;
  491. config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
  492. return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
  493. }
  494. static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin)
  495. {
  496. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  497. struct pmic_mpp_pad *pad;
  498. int ret;
  499. pad = state->ctrl->desc->pins[pin].drv_data;
  500. if (pad->input_enabled) {
  501. ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
  502. if (ret < 0)
  503. return ret;
  504. pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
  505. }
  506. return !!pad->out_value;
  507. }
  508. static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value)
  509. {
  510. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  511. unsigned long config;
  512. config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
  513. pmic_mpp_config_set(state->ctrl, pin, &config, 1);
  514. }
  515. static int pmic_mpp_of_xlate(struct gpio_chip *chip,
  516. const struct of_phandle_args *gpio_desc,
  517. u32 *flags)
  518. {
  519. if (chip->of_gpio_n_cells < 2)
  520. return -EINVAL;
  521. if (flags)
  522. *flags = gpio_desc->args[1];
  523. return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET;
  524. }
  525. static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin)
  526. {
  527. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  528. struct pmic_mpp_pad *pad;
  529. pad = state->ctrl->desc->pins[pin].drv_data;
  530. return pad->irq;
  531. }
  532. static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  533. {
  534. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  535. unsigned i;
  536. for (i = 0; i < chip->ngpio; i++) {
  537. pmic_mpp_config_dbg_show(state->ctrl, s, i);
  538. seq_puts(s, "\n");
  539. }
  540. }
  541. static const struct gpio_chip pmic_mpp_gpio_template = {
  542. .direction_input = pmic_mpp_direction_input,
  543. .direction_output = pmic_mpp_direction_output,
  544. .get = pmic_mpp_get,
  545. .set = pmic_mpp_set,
  546. .request = gpiochip_generic_request,
  547. .free = gpiochip_generic_free,
  548. .of_xlate = pmic_mpp_of_xlate,
  549. .to_irq = pmic_mpp_to_irq,
  550. .dbg_show = pmic_mpp_dbg_show,
  551. };
  552. static int pmic_mpp_populate(struct pmic_mpp_state *state,
  553. struct pmic_mpp_pad *pad)
  554. {
  555. int type, subtype, val, dir;
  556. unsigned int sel;
  557. type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE);
  558. if (type < 0)
  559. return type;
  560. if (type != PMIC_MPP_TYPE) {
  561. dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
  562. type, pad->base);
  563. return -ENODEV;
  564. }
  565. subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE);
  566. if (subtype < 0)
  567. return subtype;
  568. switch (subtype) {
  569. case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT:
  570. case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT:
  571. case PMIC_MPP_SUBTYPE_4CH_NO_SINK:
  572. case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK:
  573. case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC:
  574. pad->num_sources = 4;
  575. break;
  576. case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC:
  577. pad->num_sources = 8;
  578. break;
  579. default:
  580. dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n",
  581. subtype, pad->base);
  582. return -ENODEV;
  583. }
  584. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL);
  585. if (val < 0)
  586. return val;
  587. pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK;
  588. dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT;
  589. dir &= PMIC_MPP_REG_MODE_DIR_MASK;
  590. switch (dir) {
  591. case PMIC_MPP_MODE_DIGITAL_INPUT:
  592. pad->input_enabled = true;
  593. pad->output_enabled = false;
  594. pad->function = PMIC_MPP_DIGITAL;
  595. break;
  596. case PMIC_MPP_MODE_DIGITAL_OUTPUT:
  597. pad->input_enabled = false;
  598. pad->output_enabled = true;
  599. pad->function = PMIC_MPP_DIGITAL;
  600. break;
  601. case PMIC_MPP_MODE_DIGITAL_BIDIR:
  602. pad->input_enabled = true;
  603. pad->output_enabled = true;
  604. pad->function = PMIC_MPP_DIGITAL;
  605. break;
  606. case PMIC_MPP_MODE_ANALOG_BIDIR:
  607. pad->input_enabled = true;
  608. pad->output_enabled = true;
  609. pad->function = PMIC_MPP_ANALOG;
  610. break;
  611. case PMIC_MPP_MODE_ANALOG_INPUT:
  612. pad->input_enabled = true;
  613. pad->output_enabled = false;
  614. pad->function = PMIC_MPP_ANALOG;
  615. break;
  616. case PMIC_MPP_MODE_ANALOG_OUTPUT:
  617. pad->input_enabled = false;
  618. pad->output_enabled = true;
  619. pad->function = PMIC_MPP_ANALOG;
  620. break;
  621. case PMIC_MPP_MODE_CURRENT_SINK:
  622. pad->input_enabled = false;
  623. pad->output_enabled = true;
  624. pad->function = PMIC_MPP_SINK;
  625. break;
  626. default:
  627. dev_err(state->dev, "unknown MPP direction\n");
  628. return -ENODEV;
  629. }
  630. sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
  631. sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK;
  632. if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST)
  633. pad->dtest = sel + 1;
  634. else if (sel == PMIC_MPP_SELECTOR_PAIRED)
  635. pad->paired = true;
  636. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL);
  637. if (val < 0)
  638. return val;
  639. pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT;
  640. pad->power_source &= PMIC_MPP_REG_VIN_MASK;
  641. if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT &&
  642. subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) {
  643. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
  644. if (val < 0)
  645. return val;
  646. pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
  647. pad->pullup &= PMIC_MPP_REG_PULL_MASK;
  648. pad->has_pullup = true;
  649. }
  650. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL);
  651. if (val < 0)
  652. return val;
  653. pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT;
  654. pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK;
  655. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL);
  656. if (val < 0)
  657. return val;
  658. pad->drive_strength = val;
  659. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL);
  660. if (val < 0)
  661. return val;
  662. pad->aout_level = val;
  663. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL);
  664. if (val < 0)
  665. return val;
  666. pad->is_enabled = !!val;
  667. return 0;
  668. }
  669. static int pmic_mpp_probe(struct platform_device *pdev)
  670. {
  671. struct device *dev = &pdev->dev;
  672. struct pinctrl_pin_desc *pindesc;
  673. struct pinctrl_desc *pctrldesc;
  674. struct pmic_mpp_pad *pad, *pads;
  675. struct pmic_mpp_state *state;
  676. int ret, npins, i;
  677. u32 reg;
  678. ret = of_property_read_u32(dev->of_node, "reg", &reg);
  679. if (ret < 0) {
  680. dev_err(dev, "missing base address");
  681. return ret;
  682. }
  683. npins = platform_irq_count(pdev);
  684. if (!npins)
  685. return -EINVAL;
  686. if (npins < 0)
  687. return npins;
  688. BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups));
  689. state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
  690. if (!state)
  691. return -ENOMEM;
  692. platform_set_drvdata(pdev, state);
  693. state->dev = &pdev->dev;
  694. state->map = dev_get_regmap(dev->parent, NULL);
  695. pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
  696. if (!pindesc)
  697. return -ENOMEM;
  698. pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
  699. if (!pads)
  700. return -ENOMEM;
  701. pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
  702. if (!pctrldesc)
  703. return -ENOMEM;
  704. pctrldesc->pctlops = &pmic_mpp_pinctrl_ops;
  705. pctrldesc->pmxops = &pmic_mpp_pinmux_ops;
  706. pctrldesc->confops = &pmic_mpp_pinconf_ops;
  707. pctrldesc->owner = THIS_MODULE;
  708. pctrldesc->name = dev_name(dev);
  709. pctrldesc->pins = pindesc;
  710. pctrldesc->npins = npins;
  711. pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings);
  712. pctrldesc->custom_params = pmic_mpp_bindings;
  713. #ifdef CONFIG_DEBUG_FS
  714. pctrldesc->custom_conf_items = pmic_conf_items;
  715. #endif
  716. for (i = 0; i < npins; i++, pindesc++) {
  717. pad = &pads[i];
  718. pindesc->drv_data = pad;
  719. pindesc->number = i;
  720. pindesc->name = pmic_mpp_groups[i];
  721. pad->irq = platform_get_irq(pdev, i);
  722. if (pad->irq < 0)
  723. return pad->irq;
  724. pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE;
  725. ret = pmic_mpp_populate(state, pad);
  726. if (ret < 0)
  727. return ret;
  728. }
  729. state->chip = pmic_mpp_gpio_template;
  730. state->chip.parent = dev;
  731. state->chip.base = -1;
  732. state->chip.ngpio = npins;
  733. state->chip.label = dev_name(dev);
  734. state->chip.of_gpio_n_cells = 2;
  735. state->chip.can_sleep = false;
  736. state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
  737. if (IS_ERR(state->ctrl))
  738. return PTR_ERR(state->ctrl);
  739. ret = gpiochip_add_data(&state->chip, state);
  740. if (ret) {
  741. dev_err(state->dev, "can't add gpio chip\n");
  742. return ret;
  743. }
  744. ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
  745. if (ret) {
  746. dev_err(dev, "failed to add pin range\n");
  747. goto err_range;
  748. }
  749. return 0;
  750. err_range:
  751. gpiochip_remove(&state->chip);
  752. return ret;
  753. }
  754. static int pmic_mpp_remove(struct platform_device *pdev)
  755. {
  756. struct pmic_mpp_state *state = platform_get_drvdata(pdev);
  757. gpiochip_remove(&state->chip);
  758. return 0;
  759. }
  760. static const struct of_device_id pmic_mpp_of_match[] = {
  761. { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */
  762. { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */
  763. { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */
  764. { .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */
  765. { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */
  766. { .compatible = "qcom,spmi-mpp" }, /* Generic */
  767. { },
  768. };
  769. MODULE_DEVICE_TABLE(of, pmic_mpp_of_match);
  770. static struct platform_driver pmic_mpp_driver = {
  771. .driver = {
  772. .name = "qcom-spmi-mpp",
  773. .of_match_table = pmic_mpp_of_match,
  774. },
  775. .probe = pmic_mpp_probe,
  776. .remove = pmic_mpp_remove,
  777. };
  778. module_platform_driver(pmic_mpp_driver);
  779. MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
  780. MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver");
  781. MODULE_ALIAS("platform:qcom-spmi-mpp");
  782. MODULE_LICENSE("GPL v2");