pcie-designware-plat.c 2.8 KB

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  1. /*
  2. * PCIe RC driver for Synopsys DesignWare Core
  3. *
  4. * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
  5. *
  6. * Authors: Joao Pinto <Joao.Pinto@synopsys.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/pci.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/resource.h>
  22. #include <linux/signal.h>
  23. #include <linux/types.h>
  24. #include "pcie-designware.h"
  25. struct dw_plat_pcie {
  26. struct pcie_port pp; /* pp.dbi_base is DT 0th resource */
  27. };
  28. static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg)
  29. {
  30. struct pcie_port *pp = arg;
  31. return dw_handle_msi_irq(pp);
  32. }
  33. static void dw_plat_pcie_host_init(struct pcie_port *pp)
  34. {
  35. dw_pcie_setup_rc(pp);
  36. dw_pcie_wait_for_link(pp);
  37. if (IS_ENABLED(CONFIG_PCI_MSI))
  38. dw_pcie_msi_init(pp);
  39. }
  40. static struct pcie_host_ops dw_plat_pcie_host_ops = {
  41. .host_init = dw_plat_pcie_host_init,
  42. };
  43. static int dw_plat_add_pcie_port(struct pcie_port *pp,
  44. struct platform_device *pdev)
  45. {
  46. struct device *dev = pp->dev;
  47. int ret;
  48. pp->irq = platform_get_irq(pdev, 1);
  49. if (pp->irq < 0)
  50. return pp->irq;
  51. if (IS_ENABLED(CONFIG_PCI_MSI)) {
  52. pp->msi_irq = platform_get_irq(pdev, 0);
  53. if (pp->msi_irq < 0)
  54. return pp->msi_irq;
  55. ret = devm_request_irq(dev, pp->msi_irq,
  56. dw_plat_pcie_msi_irq_handler,
  57. IRQF_SHARED, "dw-plat-pcie-msi", pp);
  58. if (ret) {
  59. dev_err(dev, "failed to request MSI IRQ\n");
  60. return ret;
  61. }
  62. }
  63. pp->root_bus_nr = -1;
  64. pp->ops = &dw_plat_pcie_host_ops;
  65. ret = dw_pcie_host_init(pp);
  66. if (ret) {
  67. dev_err(dev, "failed to initialize host\n");
  68. return ret;
  69. }
  70. return 0;
  71. }
  72. static int dw_plat_pcie_probe(struct platform_device *pdev)
  73. {
  74. struct device *dev = &pdev->dev;
  75. struct dw_plat_pcie *dw_plat_pcie;
  76. struct pcie_port *pp;
  77. struct resource *res; /* Resource from DT */
  78. int ret;
  79. dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL);
  80. if (!dw_plat_pcie)
  81. return -ENOMEM;
  82. pp = &dw_plat_pcie->pp;
  83. pp->dev = dev;
  84. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  85. pp->dbi_base = devm_ioremap_resource(dev, res);
  86. if (IS_ERR(pp->dbi_base))
  87. return PTR_ERR(pp->dbi_base);
  88. ret = dw_plat_add_pcie_port(pp, pdev);
  89. if (ret < 0)
  90. return ret;
  91. return 0;
  92. }
  93. static const struct of_device_id dw_plat_pcie_of_match[] = {
  94. { .compatible = "snps,dw-pcie", },
  95. {},
  96. };
  97. static struct platform_driver dw_plat_pcie_driver = {
  98. .driver = {
  99. .name = "dw-pcie",
  100. .of_match_table = dw_plat_pcie_of_match,
  101. },
  102. .probe = dw_plat_pcie_probe,
  103. };
  104. builtin_platform_driver(dw_plat_pcie_driver);