rockchip-efuse.c 6.3 KB

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  1. /*
  2. * Rockchip eFuse Driver
  3. *
  4. * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
  5. * Author: Caesar Wang <wxt@rock-chips.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. */
  16. #include <linux/clk.h>
  17. #include <linux/delay.h>
  18. #include <linux/device.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/nvmem-provider.h>
  22. #include <linux/slab.h>
  23. #include <linux/of.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/platform_device.h>
  26. #define RK3288_A_SHIFT 6
  27. #define RK3288_A_MASK 0x3ff
  28. #define RK3288_PGENB BIT(3)
  29. #define RK3288_LOAD BIT(2)
  30. #define RK3288_STROBE BIT(1)
  31. #define RK3288_CSB BIT(0)
  32. #define RK3399_A_SHIFT 16
  33. #define RK3399_A_MASK 0x3ff
  34. #define RK3399_NBYTES 4
  35. #define RK3399_STROBSFTSEL BIT(9)
  36. #define RK3399_RSB BIT(7)
  37. #define RK3399_PD BIT(5)
  38. #define RK3399_PGENB BIT(3)
  39. #define RK3399_LOAD BIT(2)
  40. #define RK3399_STROBE BIT(1)
  41. #define RK3399_CSB BIT(0)
  42. #define REG_EFUSE_CTRL 0x0000
  43. #define REG_EFUSE_DOUT 0x0004
  44. struct rockchip_efuse_chip {
  45. struct device *dev;
  46. void __iomem *base;
  47. struct clk *clk;
  48. };
  49. static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
  50. void *val, size_t bytes)
  51. {
  52. struct rockchip_efuse_chip *efuse = context;
  53. u8 *buf = val;
  54. int ret;
  55. ret = clk_prepare_enable(efuse->clk);
  56. if (ret < 0) {
  57. dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
  58. return ret;
  59. }
  60. writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
  61. udelay(1);
  62. while (bytes--) {
  63. writel(readl(efuse->base + REG_EFUSE_CTRL) &
  64. (~(RK3288_A_MASK << RK3288_A_SHIFT)),
  65. efuse->base + REG_EFUSE_CTRL);
  66. writel(readl(efuse->base + REG_EFUSE_CTRL) |
  67. ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
  68. efuse->base + REG_EFUSE_CTRL);
  69. udelay(1);
  70. writel(readl(efuse->base + REG_EFUSE_CTRL) |
  71. RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
  72. udelay(1);
  73. *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
  74. writel(readl(efuse->base + REG_EFUSE_CTRL) &
  75. (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
  76. udelay(1);
  77. }
  78. /* Switch to standby mode */
  79. writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
  80. clk_disable_unprepare(efuse->clk);
  81. return 0;
  82. }
  83. static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
  84. void *val, size_t bytes)
  85. {
  86. struct rockchip_efuse_chip *efuse = context;
  87. unsigned int addr_start, addr_end, addr_offset, addr_len;
  88. u32 out_value;
  89. u8 *buf;
  90. int ret, i = 0;
  91. ret = clk_prepare_enable(efuse->clk);
  92. if (ret < 0) {
  93. dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
  94. return ret;
  95. }
  96. addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
  97. addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
  98. addr_offset = offset % RK3399_NBYTES;
  99. addr_len = addr_end - addr_start;
  100. buf = kzalloc(sizeof(*buf) * addr_len * RK3399_NBYTES, GFP_KERNEL);
  101. if (!buf) {
  102. clk_disable_unprepare(efuse->clk);
  103. return -ENOMEM;
  104. }
  105. writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
  106. efuse->base + REG_EFUSE_CTRL);
  107. udelay(1);
  108. while (addr_len--) {
  109. writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE |
  110. ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
  111. efuse->base + REG_EFUSE_CTRL);
  112. udelay(1);
  113. out_value = readl(efuse->base + REG_EFUSE_DOUT);
  114. writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE),
  115. efuse->base + REG_EFUSE_CTRL);
  116. udelay(1);
  117. memcpy(&buf[i], &out_value, RK3399_NBYTES);
  118. i += RK3399_NBYTES;
  119. }
  120. /* Switch to standby mode */
  121. writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);
  122. memcpy(val, buf + addr_offset, bytes);
  123. kfree(buf);
  124. clk_disable_unprepare(efuse->clk);
  125. return 0;
  126. }
  127. static struct nvmem_config econfig = {
  128. .name = "rockchip-efuse",
  129. .owner = THIS_MODULE,
  130. .stride = 1,
  131. .word_size = 1,
  132. .read_only = true,
  133. };
  134. static const struct of_device_id rockchip_efuse_match[] = {
  135. /* deprecated but kept around for dts binding compatibility */
  136. {
  137. .compatible = "rockchip,rockchip-efuse",
  138. .data = (void *)&rockchip_rk3288_efuse_read,
  139. },
  140. {
  141. .compatible = "rockchip,rk3066a-efuse",
  142. .data = (void *)&rockchip_rk3288_efuse_read,
  143. },
  144. {
  145. .compatible = "rockchip,rk3188-efuse",
  146. .data = (void *)&rockchip_rk3288_efuse_read,
  147. },
  148. {
  149. .compatible = "rockchip,rk3288-efuse",
  150. .data = (void *)&rockchip_rk3288_efuse_read,
  151. },
  152. {
  153. .compatible = "rockchip,rk3399-efuse",
  154. .data = (void *)&rockchip_rk3399_efuse_read,
  155. },
  156. { /* sentinel */},
  157. };
  158. MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
  159. static int rockchip_efuse_probe(struct platform_device *pdev)
  160. {
  161. struct resource *res;
  162. struct nvmem_device *nvmem;
  163. struct rockchip_efuse_chip *efuse;
  164. const struct of_device_id *match;
  165. struct device *dev = &pdev->dev;
  166. match = of_match_device(dev->driver->of_match_table, dev);
  167. if (!match || !match->data) {
  168. dev_err(dev, "failed to get match data\n");
  169. return -EINVAL;
  170. }
  171. efuse = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_efuse_chip),
  172. GFP_KERNEL);
  173. if (!efuse)
  174. return -ENOMEM;
  175. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  176. efuse->base = devm_ioremap_resource(&pdev->dev, res);
  177. if (IS_ERR(efuse->base))
  178. return PTR_ERR(efuse->base);
  179. efuse->clk = devm_clk_get(&pdev->dev, "pclk_efuse");
  180. if (IS_ERR(efuse->clk))
  181. return PTR_ERR(efuse->clk);
  182. efuse->dev = &pdev->dev;
  183. econfig.size = resource_size(res);
  184. econfig.reg_read = match->data;
  185. econfig.priv = efuse;
  186. econfig.dev = efuse->dev;
  187. nvmem = nvmem_register(&econfig);
  188. if (IS_ERR(nvmem))
  189. return PTR_ERR(nvmem);
  190. platform_set_drvdata(pdev, nvmem);
  191. return 0;
  192. }
  193. static int rockchip_efuse_remove(struct platform_device *pdev)
  194. {
  195. struct nvmem_device *nvmem = platform_get_drvdata(pdev);
  196. return nvmem_unregister(nvmem);
  197. }
  198. static struct platform_driver rockchip_efuse_driver = {
  199. .probe = rockchip_efuse_probe,
  200. .remove = rockchip_efuse_remove,
  201. .driver = {
  202. .name = "rockchip-efuse",
  203. .of_match_table = rockchip_efuse_match,
  204. },
  205. };
  206. module_platform_driver(rockchip_efuse_driver);
  207. MODULE_DESCRIPTION("rockchip_efuse driver");
  208. MODULE_LICENSE("GPL v2");