ntb_perf.c 19 KB

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  1. /*
  2. * This file is provided under a dual BSD/GPLv2 license. When using or
  3. * redistributing this file, you may do so under either license.
  4. *
  5. * GPL LICENSE SUMMARY
  6. *
  7. * Copyright(c) 2015 Intel Corporation. All rights reserved.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of version 2 of the GNU General Public License as
  11. * published by the Free Software Foundation.
  12. *
  13. * BSD LICENSE
  14. *
  15. * Copyright(c) 2015 Intel Corporation. All rights reserved.
  16. *
  17. * Redistribution and use in source and binary forms, with or without
  18. * modification, are permitted provided that the following conditions
  19. * are met:
  20. *
  21. * * Redistributions of source code must retain the above copyright
  22. * notice, this list of conditions and the following disclaimer.
  23. * * Redistributions in binary form must reproduce the above copy
  24. * notice, this list of conditions and the following disclaimer in
  25. * the documentation and/or other materials provided with the
  26. * distribution.
  27. * * Neither the name of Intel Corporation nor the names of its
  28. * contributors may be used to endorse or promote products derived
  29. * from this software without specific prior written permission.
  30. *
  31. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  32. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  33. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  34. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  35. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  36. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  37. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  38. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  39. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42. *
  43. * PCIe NTB Perf Linux driver
  44. */
  45. #include <linux/init.h>
  46. #include <linux/kernel.h>
  47. #include <linux/module.h>
  48. #include <linux/kthread.h>
  49. #include <linux/time.h>
  50. #include <linux/timer.h>
  51. #include <linux/dma-mapping.h>
  52. #include <linux/pci.h>
  53. #include <linux/slab.h>
  54. #include <linux/spinlock.h>
  55. #include <linux/debugfs.h>
  56. #include <linux/dmaengine.h>
  57. #include <linux/delay.h>
  58. #include <linux/sizes.h>
  59. #include <linux/ntb.h>
  60. #include <linux/mutex.h>
  61. #define DRIVER_NAME "ntb_perf"
  62. #define DRIVER_DESCRIPTION "PCIe NTB Performance Measurement Tool"
  63. #define DRIVER_LICENSE "Dual BSD/GPL"
  64. #define DRIVER_VERSION "1.0"
  65. #define DRIVER_AUTHOR "Dave Jiang <dave.jiang@intel.com>"
  66. #define PERF_LINK_DOWN_TIMEOUT 10
  67. #define PERF_VERSION 0xffff0001
  68. #define MAX_THREADS 32
  69. #define MAX_TEST_SIZE SZ_1M
  70. #define MAX_SRCS 32
  71. #define DMA_OUT_RESOURCE_TO msecs_to_jiffies(50)
  72. #define DMA_RETRIES 20
  73. #define SZ_4G (1ULL << 32)
  74. #define MAX_SEG_ORDER 20 /* no larger than 1M for kmalloc buffer */
  75. MODULE_LICENSE(DRIVER_LICENSE);
  76. MODULE_VERSION(DRIVER_VERSION);
  77. MODULE_AUTHOR(DRIVER_AUTHOR);
  78. MODULE_DESCRIPTION(DRIVER_DESCRIPTION);
  79. static struct dentry *perf_debugfs_dir;
  80. static unsigned long max_mw_size;
  81. module_param(max_mw_size, ulong, 0644);
  82. MODULE_PARM_DESC(max_mw_size, "Limit size of large memory windows");
  83. static unsigned int seg_order = 19; /* 512K */
  84. module_param(seg_order, uint, 0644);
  85. MODULE_PARM_DESC(seg_order, "size order [n^2] of buffer segment for testing");
  86. static unsigned int run_order = 32; /* 4G */
  87. module_param(run_order, uint, 0644);
  88. MODULE_PARM_DESC(run_order, "size order [n^2] of total data to transfer");
  89. static bool use_dma; /* default to 0 */
  90. module_param(use_dma, bool, 0644);
  91. MODULE_PARM_DESC(use_dma, "Using DMA engine to measure performance");
  92. struct perf_mw {
  93. phys_addr_t phys_addr;
  94. resource_size_t phys_size;
  95. resource_size_t xlat_align;
  96. resource_size_t xlat_align_size;
  97. void __iomem *vbase;
  98. size_t xlat_size;
  99. size_t buf_size;
  100. void *virt_addr;
  101. dma_addr_t dma_addr;
  102. };
  103. struct perf_ctx;
  104. struct pthr_ctx {
  105. struct task_struct *thread;
  106. struct perf_ctx *perf;
  107. atomic_t dma_sync;
  108. struct dma_chan *dma_chan;
  109. int dma_prep_err;
  110. int src_idx;
  111. void *srcs[MAX_SRCS];
  112. wait_queue_head_t *wq;
  113. int status;
  114. u64 copied;
  115. u64 diff_us;
  116. };
  117. struct perf_ctx {
  118. struct ntb_dev *ntb;
  119. spinlock_t db_lock;
  120. struct perf_mw mw;
  121. bool link_is_up;
  122. struct delayed_work link_work;
  123. wait_queue_head_t link_wq;
  124. struct dentry *debugfs_node_dir;
  125. struct dentry *debugfs_run;
  126. struct dentry *debugfs_threads;
  127. u8 perf_threads;
  128. /* mutex ensures only one set of threads run at once */
  129. struct mutex run_mutex;
  130. struct pthr_ctx pthr_ctx[MAX_THREADS];
  131. atomic_t tsync;
  132. atomic_t tdone;
  133. };
  134. enum {
  135. VERSION = 0,
  136. MW_SZ_HIGH,
  137. MW_SZ_LOW,
  138. MAX_SPAD
  139. };
  140. static void perf_link_event(void *ctx)
  141. {
  142. struct perf_ctx *perf = ctx;
  143. if (ntb_link_is_up(perf->ntb, NULL, NULL) == 1) {
  144. schedule_delayed_work(&perf->link_work, 2*HZ);
  145. } else {
  146. dev_dbg(&perf->ntb->pdev->dev, "link down\n");
  147. if (!perf->link_is_up)
  148. cancel_delayed_work_sync(&perf->link_work);
  149. perf->link_is_up = false;
  150. }
  151. }
  152. static void perf_db_event(void *ctx, int vec)
  153. {
  154. struct perf_ctx *perf = ctx;
  155. u64 db_bits, db_mask;
  156. db_mask = ntb_db_vector_mask(perf->ntb, vec);
  157. db_bits = ntb_db_read(perf->ntb);
  158. dev_dbg(&perf->ntb->dev, "doorbell vec %d mask %#llx bits %#llx\n",
  159. vec, db_mask, db_bits);
  160. }
  161. static const struct ntb_ctx_ops perf_ops = {
  162. .link_event = perf_link_event,
  163. .db_event = perf_db_event,
  164. };
  165. static void perf_copy_callback(void *data)
  166. {
  167. struct pthr_ctx *pctx = data;
  168. atomic_dec(&pctx->dma_sync);
  169. }
  170. static ssize_t perf_copy(struct pthr_ctx *pctx, char __iomem *dst,
  171. char *src, size_t size)
  172. {
  173. struct perf_ctx *perf = pctx->perf;
  174. struct dma_async_tx_descriptor *txd;
  175. struct dma_chan *chan = pctx->dma_chan;
  176. struct dma_device *device;
  177. struct dmaengine_unmap_data *unmap;
  178. dma_cookie_t cookie;
  179. size_t src_off, dst_off;
  180. struct perf_mw *mw = &perf->mw;
  181. void __iomem *vbase;
  182. void __iomem *dst_vaddr;
  183. dma_addr_t dst_phys;
  184. int retries = 0;
  185. if (!use_dma) {
  186. memcpy_toio(dst, src, size);
  187. return size;
  188. }
  189. if (!chan) {
  190. dev_err(&perf->ntb->dev, "DMA engine does not exist\n");
  191. return -EINVAL;
  192. }
  193. device = chan->device;
  194. src_off = (uintptr_t)src & ~PAGE_MASK;
  195. dst_off = (uintptr_t __force)dst & ~PAGE_MASK;
  196. if (!is_dma_copy_aligned(device, src_off, dst_off, size))
  197. return -ENODEV;
  198. vbase = mw->vbase;
  199. dst_vaddr = dst;
  200. dst_phys = mw->phys_addr + (dst_vaddr - vbase);
  201. unmap = dmaengine_get_unmap_data(device->dev, 1, GFP_NOWAIT);
  202. if (!unmap)
  203. return -ENOMEM;
  204. unmap->len = size;
  205. unmap->addr[0] = dma_map_page(device->dev, virt_to_page(src),
  206. src_off, size, DMA_TO_DEVICE);
  207. if (dma_mapping_error(device->dev, unmap->addr[0]))
  208. goto err_get_unmap;
  209. unmap->to_cnt = 1;
  210. do {
  211. txd = device->device_prep_dma_memcpy(chan, dst_phys,
  212. unmap->addr[0],
  213. size, DMA_PREP_INTERRUPT);
  214. if (!txd) {
  215. set_current_state(TASK_INTERRUPTIBLE);
  216. schedule_timeout(DMA_OUT_RESOURCE_TO);
  217. }
  218. } while (!txd && (++retries < DMA_RETRIES));
  219. if (!txd) {
  220. pctx->dma_prep_err++;
  221. goto err_get_unmap;
  222. }
  223. txd->callback = perf_copy_callback;
  224. txd->callback_param = pctx;
  225. dma_set_unmap(txd, unmap);
  226. cookie = dmaengine_submit(txd);
  227. if (dma_submit_error(cookie))
  228. goto err_set_unmap;
  229. dmaengine_unmap_put(unmap);
  230. atomic_inc(&pctx->dma_sync);
  231. dma_async_issue_pending(chan);
  232. return size;
  233. err_set_unmap:
  234. dmaengine_unmap_put(unmap);
  235. err_get_unmap:
  236. dmaengine_unmap_put(unmap);
  237. return 0;
  238. }
  239. static int perf_move_data(struct pthr_ctx *pctx, char __iomem *dst, char *src,
  240. u64 buf_size, u64 win_size, u64 total)
  241. {
  242. int chunks, total_chunks, i;
  243. int copied_chunks = 0;
  244. u64 copied = 0, result;
  245. char __iomem *tmp = dst;
  246. u64 perf, diff_us;
  247. ktime_t kstart, kstop, kdiff;
  248. unsigned long last_sleep = jiffies;
  249. chunks = div64_u64(win_size, buf_size);
  250. total_chunks = div64_u64(total, buf_size);
  251. kstart = ktime_get();
  252. for (i = 0; i < total_chunks; i++) {
  253. result = perf_copy(pctx, tmp, src, buf_size);
  254. copied += result;
  255. copied_chunks++;
  256. if (copied_chunks == chunks) {
  257. tmp = dst;
  258. copied_chunks = 0;
  259. } else
  260. tmp += buf_size;
  261. /* Probably should schedule every 5s to prevent soft hang. */
  262. if (unlikely((jiffies - last_sleep) > 5 * HZ)) {
  263. last_sleep = jiffies;
  264. set_current_state(TASK_INTERRUPTIBLE);
  265. schedule_timeout(1);
  266. }
  267. if (unlikely(kthread_should_stop()))
  268. break;
  269. }
  270. if (use_dma) {
  271. pr_debug("%s: All DMA descriptors submitted\n", current->comm);
  272. while (atomic_read(&pctx->dma_sync) != 0) {
  273. if (kthread_should_stop())
  274. break;
  275. msleep(20);
  276. }
  277. }
  278. kstop = ktime_get();
  279. kdiff = ktime_sub(kstop, kstart);
  280. diff_us = ktime_to_us(kdiff);
  281. pr_debug("%s: copied %llu bytes\n", current->comm, copied);
  282. pr_debug("%s: lasted %llu usecs\n", current->comm, diff_us);
  283. perf = div64_u64(copied, diff_us);
  284. pr_debug("%s: MBytes/s: %llu\n", current->comm, perf);
  285. pctx->copied = copied;
  286. pctx->diff_us = diff_us;
  287. return 0;
  288. }
  289. static bool perf_dma_filter_fn(struct dma_chan *chan, void *node)
  290. {
  291. return dev_to_node(&chan->dev->device) == (int)(unsigned long)node;
  292. }
  293. static int ntb_perf_thread(void *data)
  294. {
  295. struct pthr_ctx *pctx = data;
  296. struct perf_ctx *perf = pctx->perf;
  297. struct pci_dev *pdev = perf->ntb->pdev;
  298. struct perf_mw *mw = &perf->mw;
  299. char __iomem *dst;
  300. u64 win_size, buf_size, total;
  301. void *src;
  302. int rc, node, i;
  303. struct dma_chan *dma_chan = NULL;
  304. pr_debug("kthread %s starting...\n", current->comm);
  305. node = dev_to_node(&pdev->dev);
  306. if (use_dma && !pctx->dma_chan) {
  307. dma_cap_mask_t dma_mask;
  308. dma_cap_zero(dma_mask);
  309. dma_cap_set(DMA_MEMCPY, dma_mask);
  310. dma_chan = dma_request_channel(dma_mask, perf_dma_filter_fn,
  311. (void *)(unsigned long)node);
  312. if (!dma_chan) {
  313. pr_warn("%s: cannot acquire DMA channel, quitting\n",
  314. current->comm);
  315. return -ENODEV;
  316. }
  317. pctx->dma_chan = dma_chan;
  318. }
  319. for (i = 0; i < MAX_SRCS; i++) {
  320. pctx->srcs[i] = kmalloc_node(MAX_TEST_SIZE, GFP_KERNEL, node);
  321. if (!pctx->srcs[i]) {
  322. rc = -ENOMEM;
  323. goto err;
  324. }
  325. }
  326. win_size = mw->phys_size;
  327. buf_size = 1ULL << seg_order;
  328. total = 1ULL << run_order;
  329. if (buf_size > MAX_TEST_SIZE)
  330. buf_size = MAX_TEST_SIZE;
  331. dst = (char __iomem *)mw->vbase;
  332. atomic_inc(&perf->tsync);
  333. while (atomic_read(&perf->tsync) != perf->perf_threads)
  334. schedule();
  335. src = pctx->srcs[pctx->src_idx];
  336. pctx->src_idx = (pctx->src_idx + 1) & (MAX_SRCS - 1);
  337. rc = perf_move_data(pctx, dst, src, buf_size, win_size, total);
  338. atomic_dec(&perf->tsync);
  339. if (rc < 0) {
  340. pr_err("%s: failed\n", current->comm);
  341. rc = -ENXIO;
  342. goto err;
  343. }
  344. for (i = 0; i < MAX_SRCS; i++) {
  345. kfree(pctx->srcs[i]);
  346. pctx->srcs[i] = NULL;
  347. }
  348. atomic_inc(&perf->tdone);
  349. wake_up(pctx->wq);
  350. rc = 0;
  351. goto done;
  352. err:
  353. for (i = 0; i < MAX_SRCS; i++) {
  354. kfree(pctx->srcs[i]);
  355. pctx->srcs[i] = NULL;
  356. }
  357. if (dma_chan) {
  358. dma_release_channel(dma_chan);
  359. pctx->dma_chan = NULL;
  360. }
  361. done:
  362. /* Wait until we are told to stop */
  363. for (;;) {
  364. set_current_state(TASK_INTERRUPTIBLE);
  365. if (kthread_should_stop())
  366. break;
  367. schedule();
  368. }
  369. __set_current_state(TASK_RUNNING);
  370. return rc;
  371. }
  372. static void perf_free_mw(struct perf_ctx *perf)
  373. {
  374. struct perf_mw *mw = &perf->mw;
  375. struct pci_dev *pdev = perf->ntb->pdev;
  376. if (!mw->virt_addr)
  377. return;
  378. ntb_mw_clear_trans(perf->ntb, 0);
  379. dma_free_coherent(&pdev->dev, mw->buf_size,
  380. mw->virt_addr, mw->dma_addr);
  381. mw->xlat_size = 0;
  382. mw->buf_size = 0;
  383. mw->virt_addr = NULL;
  384. }
  385. static int perf_set_mw(struct perf_ctx *perf, resource_size_t size)
  386. {
  387. struct perf_mw *mw = &perf->mw;
  388. size_t xlat_size, buf_size;
  389. int rc;
  390. if (!size)
  391. return -EINVAL;
  392. xlat_size = round_up(size, mw->xlat_align_size);
  393. buf_size = round_up(size, mw->xlat_align);
  394. if (mw->xlat_size == xlat_size)
  395. return 0;
  396. if (mw->buf_size)
  397. perf_free_mw(perf);
  398. mw->xlat_size = xlat_size;
  399. mw->buf_size = buf_size;
  400. mw->virt_addr = dma_alloc_coherent(&perf->ntb->pdev->dev, buf_size,
  401. &mw->dma_addr, GFP_KERNEL);
  402. if (!mw->virt_addr) {
  403. mw->xlat_size = 0;
  404. mw->buf_size = 0;
  405. }
  406. rc = ntb_mw_set_trans(perf->ntb, 0, mw->dma_addr, mw->xlat_size);
  407. if (rc) {
  408. dev_err(&perf->ntb->dev, "Unable to set mw0 translation\n");
  409. perf_free_mw(perf);
  410. return -EIO;
  411. }
  412. return 0;
  413. }
  414. static void perf_link_work(struct work_struct *work)
  415. {
  416. struct perf_ctx *perf =
  417. container_of(work, struct perf_ctx, link_work.work);
  418. struct ntb_dev *ndev = perf->ntb;
  419. struct pci_dev *pdev = ndev->pdev;
  420. u32 val;
  421. u64 size;
  422. int rc;
  423. dev_dbg(&perf->ntb->pdev->dev, "%s called\n", __func__);
  424. size = perf->mw.phys_size;
  425. if (max_mw_size && size > max_mw_size)
  426. size = max_mw_size;
  427. ntb_peer_spad_write(ndev, MW_SZ_HIGH, upper_32_bits(size));
  428. ntb_peer_spad_write(ndev, MW_SZ_LOW, lower_32_bits(size));
  429. ntb_peer_spad_write(ndev, VERSION, PERF_VERSION);
  430. /* now read what peer wrote */
  431. val = ntb_spad_read(ndev, VERSION);
  432. if (val != PERF_VERSION) {
  433. dev_dbg(&pdev->dev, "Remote version = %#x\n", val);
  434. goto out;
  435. }
  436. val = ntb_spad_read(ndev, MW_SZ_HIGH);
  437. size = (u64)val << 32;
  438. val = ntb_spad_read(ndev, MW_SZ_LOW);
  439. size |= val;
  440. dev_dbg(&pdev->dev, "Remote MW size = %#llx\n", size);
  441. rc = perf_set_mw(perf, size);
  442. if (rc)
  443. goto out1;
  444. perf->link_is_up = true;
  445. wake_up(&perf->link_wq);
  446. return;
  447. out1:
  448. perf_free_mw(perf);
  449. out:
  450. if (ntb_link_is_up(ndev, NULL, NULL) == 1)
  451. schedule_delayed_work(&perf->link_work,
  452. msecs_to_jiffies(PERF_LINK_DOWN_TIMEOUT));
  453. }
  454. static int perf_setup_mw(struct ntb_dev *ntb, struct perf_ctx *perf)
  455. {
  456. struct perf_mw *mw;
  457. int rc;
  458. mw = &perf->mw;
  459. rc = ntb_mw_get_range(ntb, 0, &mw->phys_addr, &mw->phys_size,
  460. &mw->xlat_align, &mw->xlat_align_size);
  461. if (rc)
  462. return rc;
  463. perf->mw.vbase = ioremap_wc(mw->phys_addr, mw->phys_size);
  464. if (!mw->vbase)
  465. return -ENOMEM;
  466. return 0;
  467. }
  468. static ssize_t debugfs_run_read(struct file *filp, char __user *ubuf,
  469. size_t count, loff_t *offp)
  470. {
  471. struct perf_ctx *perf = filp->private_data;
  472. char *buf;
  473. ssize_t ret, out_off = 0;
  474. struct pthr_ctx *pctx;
  475. int i;
  476. u64 rate;
  477. if (!perf)
  478. return 0;
  479. buf = kmalloc(1024, GFP_KERNEL);
  480. if (!buf)
  481. return -ENOMEM;
  482. if (mutex_is_locked(&perf->run_mutex)) {
  483. out_off = scnprintf(buf, 64, "running\n");
  484. goto read_from_buf;
  485. }
  486. for (i = 0; i < MAX_THREADS; i++) {
  487. pctx = &perf->pthr_ctx[i];
  488. if (pctx->status == -ENODATA)
  489. break;
  490. if (pctx->status) {
  491. out_off += scnprintf(buf + out_off, 1024 - out_off,
  492. "%d: error %d\n", i,
  493. pctx->status);
  494. continue;
  495. }
  496. rate = div64_u64(pctx->copied, pctx->diff_us);
  497. out_off += scnprintf(buf + out_off, 1024 - out_off,
  498. "%d: copied %llu bytes in %llu usecs, %llu MBytes/s\n",
  499. i, pctx->copied, pctx->diff_us, rate);
  500. }
  501. read_from_buf:
  502. ret = simple_read_from_buffer(ubuf, count, offp, buf, out_off);
  503. kfree(buf);
  504. return ret;
  505. }
  506. static void threads_cleanup(struct perf_ctx *perf)
  507. {
  508. struct pthr_ctx *pctx;
  509. int i;
  510. for (i = 0; i < MAX_THREADS; i++) {
  511. pctx = &perf->pthr_ctx[i];
  512. if (pctx->thread) {
  513. pctx->status = kthread_stop(pctx->thread);
  514. pctx->thread = NULL;
  515. }
  516. }
  517. }
  518. static void perf_clear_thread_status(struct perf_ctx *perf)
  519. {
  520. int i;
  521. for (i = 0; i < MAX_THREADS; i++)
  522. perf->pthr_ctx[i].status = -ENODATA;
  523. }
  524. static ssize_t debugfs_run_write(struct file *filp, const char __user *ubuf,
  525. size_t count, loff_t *offp)
  526. {
  527. struct perf_ctx *perf = filp->private_data;
  528. int node, i;
  529. DECLARE_WAIT_QUEUE_HEAD(wq);
  530. if (wait_event_interruptible(perf->link_wq, perf->link_is_up))
  531. return -ENOLINK;
  532. if (perf->perf_threads == 0)
  533. return -EINVAL;
  534. if (!mutex_trylock(&perf->run_mutex))
  535. return -EBUSY;
  536. perf_clear_thread_status(perf);
  537. if (perf->perf_threads > MAX_THREADS) {
  538. perf->perf_threads = MAX_THREADS;
  539. pr_info("Reset total threads to: %u\n", MAX_THREADS);
  540. }
  541. /* no greater than 1M */
  542. if (seg_order > MAX_SEG_ORDER) {
  543. seg_order = MAX_SEG_ORDER;
  544. pr_info("Fix seg_order to %u\n", seg_order);
  545. }
  546. if (run_order < seg_order) {
  547. run_order = seg_order;
  548. pr_info("Fix run_order to %u\n", run_order);
  549. }
  550. node = dev_to_node(&perf->ntb->pdev->dev);
  551. atomic_set(&perf->tdone, 0);
  552. /* launch kernel thread */
  553. for (i = 0; i < perf->perf_threads; i++) {
  554. struct pthr_ctx *pctx;
  555. pctx = &perf->pthr_ctx[i];
  556. atomic_set(&pctx->dma_sync, 0);
  557. pctx->perf = perf;
  558. pctx->wq = &wq;
  559. pctx->thread =
  560. kthread_create_on_node(ntb_perf_thread,
  561. (void *)pctx,
  562. node, "ntb_perf %d", i);
  563. if (IS_ERR(pctx->thread)) {
  564. pctx->thread = NULL;
  565. goto err;
  566. } else {
  567. wake_up_process(pctx->thread);
  568. }
  569. }
  570. wait_event_interruptible(wq,
  571. atomic_read(&perf->tdone) == perf->perf_threads);
  572. threads_cleanup(perf);
  573. mutex_unlock(&perf->run_mutex);
  574. return count;
  575. err:
  576. threads_cleanup(perf);
  577. mutex_unlock(&perf->run_mutex);
  578. return -ENXIO;
  579. }
  580. static const struct file_operations ntb_perf_debugfs_run = {
  581. .owner = THIS_MODULE,
  582. .open = simple_open,
  583. .read = debugfs_run_read,
  584. .write = debugfs_run_write,
  585. };
  586. static int perf_debugfs_setup(struct perf_ctx *perf)
  587. {
  588. struct pci_dev *pdev = perf->ntb->pdev;
  589. if (!debugfs_initialized())
  590. return -ENODEV;
  591. if (!perf_debugfs_dir) {
  592. perf_debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
  593. if (!perf_debugfs_dir)
  594. return -ENODEV;
  595. }
  596. perf->debugfs_node_dir = debugfs_create_dir(pci_name(pdev),
  597. perf_debugfs_dir);
  598. if (!perf->debugfs_node_dir)
  599. return -ENODEV;
  600. perf->debugfs_run = debugfs_create_file("run", S_IRUSR | S_IWUSR,
  601. perf->debugfs_node_dir, perf,
  602. &ntb_perf_debugfs_run);
  603. if (!perf->debugfs_run)
  604. return -ENODEV;
  605. perf->debugfs_threads = debugfs_create_u8("threads", S_IRUSR | S_IWUSR,
  606. perf->debugfs_node_dir,
  607. &perf->perf_threads);
  608. if (!perf->debugfs_threads)
  609. return -ENODEV;
  610. return 0;
  611. }
  612. static int perf_probe(struct ntb_client *client, struct ntb_dev *ntb)
  613. {
  614. struct pci_dev *pdev = ntb->pdev;
  615. struct perf_ctx *perf;
  616. int node;
  617. int rc = 0;
  618. if (ntb_spad_count(ntb) < MAX_SPAD) {
  619. dev_err(&ntb->dev, "Not enough scratch pad registers for %s",
  620. DRIVER_NAME);
  621. return -EIO;
  622. }
  623. node = dev_to_node(&pdev->dev);
  624. perf = kzalloc_node(sizeof(*perf), GFP_KERNEL, node);
  625. if (!perf) {
  626. rc = -ENOMEM;
  627. goto err_perf;
  628. }
  629. perf->ntb = ntb;
  630. perf->perf_threads = 1;
  631. atomic_set(&perf->tsync, 0);
  632. mutex_init(&perf->run_mutex);
  633. spin_lock_init(&perf->db_lock);
  634. perf_setup_mw(ntb, perf);
  635. init_waitqueue_head(&perf->link_wq);
  636. INIT_DELAYED_WORK(&perf->link_work, perf_link_work);
  637. rc = ntb_set_ctx(ntb, perf, &perf_ops);
  638. if (rc)
  639. goto err_ctx;
  640. perf->link_is_up = false;
  641. ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO);
  642. ntb_link_event(ntb);
  643. rc = perf_debugfs_setup(perf);
  644. if (rc)
  645. goto err_ctx;
  646. perf_clear_thread_status(perf);
  647. return 0;
  648. err_ctx:
  649. cancel_delayed_work_sync(&perf->link_work);
  650. kfree(perf);
  651. err_perf:
  652. return rc;
  653. }
  654. static void perf_remove(struct ntb_client *client, struct ntb_dev *ntb)
  655. {
  656. struct perf_ctx *perf = ntb->ctx;
  657. int i;
  658. dev_dbg(&perf->ntb->dev, "%s called\n", __func__);
  659. mutex_lock(&perf->run_mutex);
  660. cancel_delayed_work_sync(&perf->link_work);
  661. ntb_clear_ctx(ntb);
  662. ntb_link_disable(ntb);
  663. debugfs_remove_recursive(perf_debugfs_dir);
  664. perf_debugfs_dir = NULL;
  665. if (use_dma) {
  666. for (i = 0; i < MAX_THREADS; i++) {
  667. struct pthr_ctx *pctx = &perf->pthr_ctx[i];
  668. if (pctx->dma_chan)
  669. dma_release_channel(pctx->dma_chan);
  670. }
  671. }
  672. kfree(perf);
  673. }
  674. static struct ntb_client perf_client = {
  675. .ops = {
  676. .probe = perf_probe,
  677. .remove = perf_remove,
  678. },
  679. };
  680. module_ntb_client(perf_client);