lxt.c 6.9 KB

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  1. /*
  2. * drivers/net/phy/lxt.c
  3. *
  4. * Driver for Intel LXT PHYs
  5. *
  6. * Author: Andy Fleming
  7. *
  8. * Copyright (c) 2004 Freescale Semiconductor, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. *
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/string.h>
  18. #include <linux/errno.h>
  19. #include <linux/unistd.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/init.h>
  22. #include <linux/delay.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/skbuff.h>
  26. #include <linux/spinlock.h>
  27. #include <linux/mm.h>
  28. #include <linux/module.h>
  29. #include <linux/mii.h>
  30. #include <linux/ethtool.h>
  31. #include <linux/phy.h>
  32. #include <asm/io.h>
  33. #include <asm/irq.h>
  34. #include <asm/uaccess.h>
  35. /* The Level one LXT970 is used by many boards */
  36. #define MII_LXT970_IER 17 /* Interrupt Enable Register */
  37. #define MII_LXT970_IER_IEN 0x0002
  38. #define MII_LXT970_ISR 18 /* Interrupt Status Register */
  39. #define MII_LXT970_CONFIG 19 /* Configuration Register */
  40. /* ------------------------------------------------------------------------- */
  41. /* The Level one LXT971 is used on some of my custom boards */
  42. /* register definitions for the 971 */
  43. #define MII_LXT971_IER 18 /* Interrupt Enable Register */
  44. #define MII_LXT971_IER_IEN 0x00f2
  45. #define MII_LXT971_ISR 19 /* Interrupt Status Register */
  46. /* register definitions for the 973 */
  47. #define MII_LXT973_PCR 16 /* Port Configuration Register */
  48. #define PCR_FIBER_SELECT 1
  49. MODULE_DESCRIPTION("Intel LXT PHY driver");
  50. MODULE_AUTHOR("Andy Fleming");
  51. MODULE_LICENSE("GPL");
  52. static int lxt970_ack_interrupt(struct phy_device *phydev)
  53. {
  54. int err;
  55. err = phy_read(phydev, MII_BMSR);
  56. if (err < 0)
  57. return err;
  58. err = phy_read(phydev, MII_LXT970_ISR);
  59. if (err < 0)
  60. return err;
  61. return 0;
  62. }
  63. static int lxt970_config_intr(struct phy_device *phydev)
  64. {
  65. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  66. return phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN);
  67. else
  68. return phy_write(phydev, MII_LXT970_IER, 0);
  69. }
  70. static int lxt970_config_init(struct phy_device *phydev)
  71. {
  72. return phy_write(phydev, MII_LXT970_CONFIG, 0);
  73. }
  74. static int lxt971_ack_interrupt(struct phy_device *phydev)
  75. {
  76. int err = phy_read(phydev, MII_LXT971_ISR);
  77. if (err < 0)
  78. return err;
  79. return 0;
  80. }
  81. static int lxt971_config_intr(struct phy_device *phydev)
  82. {
  83. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  84. return phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN);
  85. else
  86. return phy_write(phydev, MII_LXT971_IER, 0);
  87. }
  88. /*
  89. * A2 version of LXT973 chip has an ERRATA: it randomly return the contents
  90. * of the previous even register when you read a odd register regularly
  91. */
  92. static int lxt973a2_update_link(struct phy_device *phydev)
  93. {
  94. int status;
  95. int control;
  96. int retry = 8; /* we try 8 times */
  97. /* Do a fake read */
  98. status = phy_read(phydev, MII_BMSR);
  99. if (status < 0)
  100. return status;
  101. control = phy_read(phydev, MII_BMCR);
  102. if (control < 0)
  103. return control;
  104. do {
  105. /* Read link and autonegotiation status */
  106. status = phy_read(phydev, MII_BMSR);
  107. } while (status >= 0 && retry-- && status == control);
  108. if (status < 0)
  109. return status;
  110. if ((status & BMSR_LSTATUS) == 0)
  111. phydev->link = 0;
  112. else
  113. phydev->link = 1;
  114. return 0;
  115. }
  116. static int lxt973a2_read_status(struct phy_device *phydev)
  117. {
  118. int adv;
  119. int err;
  120. int lpa;
  121. int lpagb = 0;
  122. /* Update the link, but return if there was an error */
  123. err = lxt973a2_update_link(phydev);
  124. if (err)
  125. return err;
  126. if (AUTONEG_ENABLE == phydev->autoneg) {
  127. int retry = 1;
  128. adv = phy_read(phydev, MII_ADVERTISE);
  129. if (adv < 0)
  130. return adv;
  131. do {
  132. lpa = phy_read(phydev, MII_LPA);
  133. if (lpa < 0)
  134. return lpa;
  135. /* If both registers are equal, it is suspect but not
  136. * impossible, hence a new try
  137. */
  138. } while (lpa == adv && retry--);
  139. lpa &= adv;
  140. phydev->speed = SPEED_10;
  141. phydev->duplex = DUPLEX_HALF;
  142. phydev->pause = phydev->asym_pause = 0;
  143. if (lpagb & (LPA_1000FULL | LPA_1000HALF)) {
  144. phydev->speed = SPEED_1000;
  145. if (lpagb & LPA_1000FULL)
  146. phydev->duplex = DUPLEX_FULL;
  147. } else if (lpa & (LPA_100FULL | LPA_100HALF)) {
  148. phydev->speed = SPEED_100;
  149. if (lpa & LPA_100FULL)
  150. phydev->duplex = DUPLEX_FULL;
  151. } else {
  152. if (lpa & LPA_10FULL)
  153. phydev->duplex = DUPLEX_FULL;
  154. }
  155. if (phydev->duplex == DUPLEX_FULL) {
  156. phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
  157. phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
  158. }
  159. } else {
  160. int bmcr = phy_read(phydev, MII_BMCR);
  161. if (bmcr < 0)
  162. return bmcr;
  163. if (bmcr & BMCR_FULLDPLX)
  164. phydev->duplex = DUPLEX_FULL;
  165. else
  166. phydev->duplex = DUPLEX_HALF;
  167. if (bmcr & BMCR_SPEED1000)
  168. phydev->speed = SPEED_1000;
  169. else if (bmcr & BMCR_SPEED100)
  170. phydev->speed = SPEED_100;
  171. else
  172. phydev->speed = SPEED_10;
  173. phydev->pause = phydev->asym_pause = 0;
  174. }
  175. return 0;
  176. }
  177. static int lxt973_probe(struct phy_device *phydev)
  178. {
  179. int val = phy_read(phydev, MII_LXT973_PCR);
  180. if (val & PCR_FIBER_SELECT) {
  181. /*
  182. * If fiber is selected, then the only correct setting
  183. * is 100Mbps, full duplex, and auto negotiation off.
  184. */
  185. val = phy_read(phydev, MII_BMCR);
  186. val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
  187. val &= ~BMCR_ANENABLE;
  188. phy_write(phydev, MII_BMCR, val);
  189. /* Remember that the port is in fiber mode. */
  190. phydev->priv = lxt973_probe;
  191. } else {
  192. phydev->priv = NULL;
  193. }
  194. return 0;
  195. }
  196. static int lxt973_config_aneg(struct phy_device *phydev)
  197. {
  198. /* Do nothing if port is in fiber mode. */
  199. return phydev->priv ? 0 : genphy_config_aneg(phydev);
  200. }
  201. static struct phy_driver lxt97x_driver[] = {
  202. {
  203. .phy_id = 0x78100000,
  204. .name = "LXT970",
  205. .phy_id_mask = 0xfffffff0,
  206. .features = PHY_BASIC_FEATURES,
  207. .flags = PHY_HAS_INTERRUPT,
  208. .config_init = lxt970_config_init,
  209. .config_aneg = genphy_config_aneg,
  210. .read_status = genphy_read_status,
  211. .ack_interrupt = lxt970_ack_interrupt,
  212. .config_intr = lxt970_config_intr,
  213. }, {
  214. .phy_id = 0x001378e0,
  215. .name = "LXT971",
  216. .phy_id_mask = 0xfffffff0,
  217. .features = PHY_BASIC_FEATURES,
  218. .flags = PHY_HAS_INTERRUPT,
  219. .config_aneg = genphy_config_aneg,
  220. .read_status = genphy_read_status,
  221. .ack_interrupt = lxt971_ack_interrupt,
  222. .config_intr = lxt971_config_intr,
  223. }, {
  224. .phy_id = 0x00137a10,
  225. .name = "LXT973-A2",
  226. .phy_id_mask = 0xffffffff,
  227. .features = PHY_BASIC_FEATURES,
  228. .flags = 0,
  229. .probe = lxt973_probe,
  230. .config_aneg = lxt973_config_aneg,
  231. .read_status = lxt973a2_read_status,
  232. }, {
  233. .phy_id = 0x00137a10,
  234. .name = "LXT973",
  235. .phy_id_mask = 0xfffffff0,
  236. .features = PHY_BASIC_FEATURES,
  237. .flags = 0,
  238. .probe = lxt973_probe,
  239. .config_aneg = lxt973_config_aneg,
  240. .read_status = genphy_read_status,
  241. } };
  242. module_phy_driver(lxt97x_driver);
  243. static struct mdio_device_id __maybe_unused lxt_tbl[] = {
  244. { 0x78100000, 0xfffffff0 },
  245. { 0x001378e0, 0xfffffff0 },
  246. { 0x00137a10, 0xfffffff0 },
  247. { }
  248. };
  249. MODULE_DEVICE_TABLE(mdio, lxt_tbl);