qca_7k.h 2.4 KB

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  1. /*
  2. * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
  3. * Copyright (c) 2014, I2SE GmbH
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software
  6. * for any purpose with or without fee is hereby granted, provided
  7. * that the above copyright notice and this permission notice appear
  8. * in all copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL
  13. * THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
  14. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  15. * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
  16. * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  17. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18. *
  19. */
  20. /* Qualcomm Atheros SPI register definition.
  21. *
  22. * This module is designed to define the Qualcomm Atheros SPI
  23. * register placeholders.
  24. */
  25. #ifndef _QCA_7K_H
  26. #define _QCA_7K_H
  27. #include <linux/types.h>
  28. #include "qca_spi.h"
  29. #define QCA7K_SPI_READ (1 << 15)
  30. #define QCA7K_SPI_WRITE (0 << 15)
  31. #define QCA7K_SPI_INTERNAL (1 << 14)
  32. #define QCA7K_SPI_EXTERNAL (0 << 14)
  33. #define QCASPI_CMD_LEN 2
  34. #define QCASPI_HW_PKT_LEN 4
  35. #define QCASPI_HW_BUF_LEN 0xC5B
  36. /* SPI registers; */
  37. #define SPI_REG_BFR_SIZE 0x0100
  38. #define SPI_REG_WRBUF_SPC_AVA 0x0200
  39. #define SPI_REG_RDBUF_BYTE_AVA 0x0300
  40. #define SPI_REG_SPI_CONFIG 0x0400
  41. #define SPI_REG_SPI_STATUS 0x0500
  42. #define SPI_REG_INTR_CAUSE 0x0C00
  43. #define SPI_REG_INTR_ENABLE 0x0D00
  44. #define SPI_REG_RDBUF_WATERMARK 0x1200
  45. #define SPI_REG_WRBUF_WATERMARK 0x1300
  46. #define SPI_REG_SIGNATURE 0x1A00
  47. #define SPI_REG_ACTION_CTRL 0x1B00
  48. /* SPI_CONFIG register definition; */
  49. #define QCASPI_SLAVE_RESET_BIT (1 << 6)
  50. /* INTR_CAUSE/ENABLE register definition. */
  51. #define SPI_INT_WRBUF_BELOW_WM (1 << 10)
  52. #define SPI_INT_CPU_ON (1 << 6)
  53. #define SPI_INT_ADDR_ERR (1 << 3)
  54. #define SPI_INT_WRBUF_ERR (1 << 2)
  55. #define SPI_INT_RDBUF_ERR (1 << 1)
  56. #define SPI_INT_PKT_AVLBL (1 << 0)
  57. void qcaspi_spi_error(struct qcaspi *qca);
  58. int qcaspi_read_register(struct qcaspi *qca, u16 reg, u16 *result);
  59. int qcaspi_write_register(struct qcaspi *qca, u16 reg, u16 value);
  60. int qcaspi_tx_cmd(struct qcaspi *qca, u16 cmd);
  61. #endif /* _QCA_7K_H */