uar.c 6.0 KB

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  1. /*
  2. * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/kernel.h>
  33. #include <linux/module.h>
  34. #include <linux/io-mapping.h>
  35. #include <linux/mlx5/driver.h>
  36. #include <linux/mlx5/cmd.h>
  37. #include "mlx5_core.h"
  38. enum {
  39. NUM_DRIVER_UARS = 4,
  40. NUM_LOW_LAT_UUARS = 4,
  41. };
  42. int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn)
  43. {
  44. u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {0};
  45. u32 in[MLX5_ST_SZ_DW(alloc_uar_in)] = {0};
  46. int err;
  47. MLX5_SET(alloc_uar_in, in, opcode, MLX5_CMD_OP_ALLOC_UAR);
  48. err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
  49. if (!err)
  50. *uarn = MLX5_GET(alloc_uar_out, out, uar);
  51. return err;
  52. }
  53. EXPORT_SYMBOL(mlx5_cmd_alloc_uar);
  54. int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn)
  55. {
  56. u32 out[MLX5_ST_SZ_DW(dealloc_uar_out)] = {0};
  57. u32 in[MLX5_ST_SZ_DW(dealloc_uar_in)] = {0};
  58. MLX5_SET(dealloc_uar_in, in, opcode, MLX5_CMD_OP_DEALLOC_UAR);
  59. MLX5_SET(dealloc_uar_in, in, uar, uarn);
  60. return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
  61. }
  62. EXPORT_SYMBOL(mlx5_cmd_free_uar);
  63. static int need_uuar_lock(int uuarn)
  64. {
  65. int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;
  66. if (uuarn == 0 || tot_uuars - NUM_LOW_LAT_UUARS)
  67. return 0;
  68. return 1;
  69. }
  70. int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari)
  71. {
  72. int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;
  73. struct mlx5_bf *bf;
  74. phys_addr_t addr;
  75. int err;
  76. int i;
  77. uuari->num_uars = NUM_DRIVER_UARS;
  78. uuari->num_low_latency_uuars = NUM_LOW_LAT_UUARS;
  79. mutex_init(&uuari->lock);
  80. uuari->uars = kcalloc(uuari->num_uars, sizeof(*uuari->uars), GFP_KERNEL);
  81. if (!uuari->uars)
  82. return -ENOMEM;
  83. uuari->bfs = kcalloc(tot_uuars, sizeof(*uuari->bfs), GFP_KERNEL);
  84. if (!uuari->bfs) {
  85. err = -ENOMEM;
  86. goto out_uars;
  87. }
  88. uuari->bitmap = kcalloc(BITS_TO_LONGS(tot_uuars), sizeof(*uuari->bitmap),
  89. GFP_KERNEL);
  90. if (!uuari->bitmap) {
  91. err = -ENOMEM;
  92. goto out_bfs;
  93. }
  94. uuari->count = kcalloc(tot_uuars, sizeof(*uuari->count), GFP_KERNEL);
  95. if (!uuari->count) {
  96. err = -ENOMEM;
  97. goto out_bitmap;
  98. }
  99. for (i = 0; i < uuari->num_uars; i++) {
  100. err = mlx5_cmd_alloc_uar(dev, &uuari->uars[i].index);
  101. if (err)
  102. goto out_count;
  103. addr = dev->iseg_base + ((phys_addr_t)(uuari->uars[i].index) << PAGE_SHIFT);
  104. uuari->uars[i].map = ioremap(addr, PAGE_SIZE);
  105. if (!uuari->uars[i].map) {
  106. mlx5_cmd_free_uar(dev, uuari->uars[i].index);
  107. err = -ENOMEM;
  108. goto out_count;
  109. }
  110. mlx5_core_dbg(dev, "allocated uar index 0x%x, mmaped at %p\n",
  111. uuari->uars[i].index, uuari->uars[i].map);
  112. }
  113. for (i = 0; i < tot_uuars; i++) {
  114. bf = &uuari->bfs[i];
  115. bf->buf_size = (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) / 2;
  116. bf->uar = &uuari->uars[i / MLX5_BF_REGS_PER_PAGE];
  117. bf->regreg = uuari->uars[i / MLX5_BF_REGS_PER_PAGE].map;
  118. bf->reg = NULL; /* Add WC support */
  119. bf->offset = (i % MLX5_BF_REGS_PER_PAGE) *
  120. (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) +
  121. MLX5_BF_OFFSET;
  122. bf->need_lock = need_uuar_lock(i);
  123. spin_lock_init(&bf->lock);
  124. spin_lock_init(&bf->lock32);
  125. bf->uuarn = i;
  126. }
  127. return 0;
  128. out_count:
  129. for (i--; i >= 0; i--) {
  130. iounmap(uuari->uars[i].map);
  131. mlx5_cmd_free_uar(dev, uuari->uars[i].index);
  132. }
  133. kfree(uuari->count);
  134. out_bitmap:
  135. kfree(uuari->bitmap);
  136. out_bfs:
  137. kfree(uuari->bfs);
  138. out_uars:
  139. kfree(uuari->uars);
  140. return err;
  141. }
  142. int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari)
  143. {
  144. int i = uuari->num_uars;
  145. for (i--; i >= 0; i--) {
  146. iounmap(uuari->uars[i].map);
  147. mlx5_cmd_free_uar(dev, uuari->uars[i].index);
  148. }
  149. kfree(uuari->count);
  150. kfree(uuari->bitmap);
  151. kfree(uuari->bfs);
  152. kfree(uuari->uars);
  153. return 0;
  154. }
  155. int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar,
  156. bool map_wc)
  157. {
  158. phys_addr_t pfn;
  159. phys_addr_t uar_bar_start;
  160. int err;
  161. err = mlx5_cmd_alloc_uar(mdev, &uar->index);
  162. if (err) {
  163. mlx5_core_warn(mdev, "mlx5_cmd_alloc_uar() failed, %d\n", err);
  164. return err;
  165. }
  166. uar_bar_start = pci_resource_start(mdev->pdev, 0);
  167. pfn = (uar_bar_start >> PAGE_SHIFT) + uar->index;
  168. if (map_wc) {
  169. uar->bf_map = ioremap_wc(pfn << PAGE_SHIFT, PAGE_SIZE);
  170. if (!uar->bf_map) {
  171. mlx5_core_warn(mdev, "ioremap_wc() failed\n");
  172. uar->map = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
  173. if (!uar->map)
  174. goto err_free_uar;
  175. }
  176. } else {
  177. uar->map = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
  178. if (!uar->map)
  179. goto err_free_uar;
  180. }
  181. return 0;
  182. err_free_uar:
  183. mlx5_core_warn(mdev, "ioremap() failed\n");
  184. err = -ENOMEM;
  185. mlx5_cmd_free_uar(mdev, uar->index);
  186. return err;
  187. }
  188. EXPORT_SYMBOL(mlx5_alloc_map_uar);
  189. void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar)
  190. {
  191. if (uar->map)
  192. iounmap(uar->map);
  193. else
  194. iounmap(uar->bf_map);
  195. mlx5_cmd_free_uar(mdev, uar->index);
  196. }
  197. EXPORT_SYMBOL(mlx5_unmap_free_uar);