eswitch.c 55 KB

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  1. /*
  2. * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/etherdevice.h>
  33. #include <linux/mlx5/driver.h>
  34. #include <linux/mlx5/mlx5_ifc.h>
  35. #include <linux/mlx5/vport.h>
  36. #include <linux/mlx5/fs.h>
  37. #include "mlx5_core.h"
  38. #include "eswitch.h"
  39. #define UPLINK_VPORT 0xFFFF
  40. enum {
  41. MLX5_ACTION_NONE = 0,
  42. MLX5_ACTION_ADD = 1,
  43. MLX5_ACTION_DEL = 2,
  44. };
  45. /* E-Switch UC L2 table hash node */
  46. struct esw_uc_addr {
  47. struct l2addr_node node;
  48. u32 table_index;
  49. u32 vport;
  50. };
  51. /* E-Switch MC FDB table hash node */
  52. struct esw_mc_addr { /* SRIOV only */
  53. struct l2addr_node node;
  54. struct mlx5_flow_rule *uplink_rule; /* Forward to uplink rule */
  55. u32 refcnt;
  56. };
  57. /* Vport UC/MC hash node */
  58. struct vport_addr {
  59. struct l2addr_node node;
  60. u8 action;
  61. u32 vport;
  62. struct mlx5_flow_rule *flow_rule; /* SRIOV only */
  63. /* A flag indicating that mac was added due to mc promiscuous vport */
  64. bool mc_promisc;
  65. };
  66. enum {
  67. UC_ADDR_CHANGE = BIT(0),
  68. MC_ADDR_CHANGE = BIT(1),
  69. PROMISC_CHANGE = BIT(3),
  70. };
  71. /* Vport context events */
  72. #define SRIOV_VPORT_EVENTS (UC_ADDR_CHANGE | \
  73. MC_ADDR_CHANGE | \
  74. PROMISC_CHANGE)
  75. static int arm_vport_context_events_cmd(struct mlx5_core_dev *dev, u16 vport,
  76. u32 events_mask)
  77. {
  78. int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {0};
  79. int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0};
  80. void *nic_vport_ctx;
  81. MLX5_SET(modify_nic_vport_context_in, in,
  82. opcode, MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT);
  83. MLX5_SET(modify_nic_vport_context_in, in, field_select.change_event, 1);
  84. MLX5_SET(modify_nic_vport_context_in, in, vport_number, vport);
  85. if (vport)
  86. MLX5_SET(modify_nic_vport_context_in, in, other_vport, 1);
  87. nic_vport_ctx = MLX5_ADDR_OF(modify_nic_vport_context_in,
  88. in, nic_vport_context);
  89. MLX5_SET(nic_vport_context, nic_vport_ctx, arm_change_event, 1);
  90. if (events_mask & UC_ADDR_CHANGE)
  91. MLX5_SET(nic_vport_context, nic_vport_ctx,
  92. event_on_uc_address_change, 1);
  93. if (events_mask & MC_ADDR_CHANGE)
  94. MLX5_SET(nic_vport_context, nic_vport_ctx,
  95. event_on_mc_address_change, 1);
  96. if (events_mask & PROMISC_CHANGE)
  97. MLX5_SET(nic_vport_context, nic_vport_ctx,
  98. event_on_promisc_change, 1);
  99. return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
  100. }
  101. /* E-Switch vport context HW commands */
  102. static int modify_esw_vport_context_cmd(struct mlx5_core_dev *dev, u16 vport,
  103. void *in, int inlen)
  104. {
  105. u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)] = {0};
  106. MLX5_SET(modify_esw_vport_context_in, in, opcode,
  107. MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT);
  108. MLX5_SET(modify_esw_vport_context_in, in, vport_number, vport);
  109. if (vport)
  110. MLX5_SET(modify_esw_vport_context_in, in, other_vport, 1);
  111. return mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
  112. }
  113. static int modify_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport,
  114. u16 vlan, u8 qos, u8 set_flags)
  115. {
  116. u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {0};
  117. if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) ||
  118. !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist))
  119. return -ENOTSUPP;
  120. esw_debug(dev, "Set Vport[%d] VLAN %d qos %d set=%x\n",
  121. vport, vlan, qos, set_flags);
  122. if (set_flags & SET_VLAN_STRIP)
  123. MLX5_SET(modify_esw_vport_context_in, in,
  124. esw_vport_context.vport_cvlan_strip, 1);
  125. if (set_flags & SET_VLAN_INSERT) {
  126. /* insert only if no vlan in packet */
  127. MLX5_SET(modify_esw_vport_context_in, in,
  128. esw_vport_context.vport_cvlan_insert, 1);
  129. MLX5_SET(modify_esw_vport_context_in, in,
  130. esw_vport_context.cvlan_pcp, qos);
  131. MLX5_SET(modify_esw_vport_context_in, in,
  132. esw_vport_context.cvlan_id, vlan);
  133. }
  134. MLX5_SET(modify_esw_vport_context_in, in,
  135. field_select.vport_cvlan_strip, 1);
  136. MLX5_SET(modify_esw_vport_context_in, in,
  137. field_select.vport_cvlan_insert, 1);
  138. return modify_esw_vport_context_cmd(dev, vport, in, sizeof(in));
  139. }
  140. /* HW L2 Table (MPFS) management */
  141. static int set_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index,
  142. u8 *mac, u8 vlan_valid, u16 vlan)
  143. {
  144. u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {0};
  145. u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)] = {0};
  146. u8 *in_mac_addr;
  147. MLX5_SET(set_l2_table_entry_in, in, opcode,
  148. MLX5_CMD_OP_SET_L2_TABLE_ENTRY);
  149. MLX5_SET(set_l2_table_entry_in, in, table_index, index);
  150. MLX5_SET(set_l2_table_entry_in, in, vlan_valid, vlan_valid);
  151. MLX5_SET(set_l2_table_entry_in, in, vlan, vlan);
  152. in_mac_addr = MLX5_ADDR_OF(set_l2_table_entry_in, in, mac_address);
  153. ether_addr_copy(&in_mac_addr[2], mac);
  154. return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
  155. }
  156. static int del_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index)
  157. {
  158. u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)] = {0};
  159. u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)] = {0};
  160. MLX5_SET(delete_l2_table_entry_in, in, opcode,
  161. MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY);
  162. MLX5_SET(delete_l2_table_entry_in, in, table_index, index);
  163. return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
  164. }
  165. static int alloc_l2_table_index(struct mlx5_l2_table *l2_table, u32 *ix)
  166. {
  167. int err = 0;
  168. *ix = find_first_zero_bit(l2_table->bitmap, l2_table->size);
  169. if (*ix >= l2_table->size)
  170. err = -ENOSPC;
  171. else
  172. __set_bit(*ix, l2_table->bitmap);
  173. return err;
  174. }
  175. static void free_l2_table_index(struct mlx5_l2_table *l2_table, u32 ix)
  176. {
  177. __clear_bit(ix, l2_table->bitmap);
  178. }
  179. static int set_l2_table_entry(struct mlx5_core_dev *dev, u8 *mac,
  180. u8 vlan_valid, u16 vlan,
  181. u32 *index)
  182. {
  183. struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
  184. int err;
  185. err = alloc_l2_table_index(l2_table, index);
  186. if (err)
  187. return err;
  188. err = set_l2_table_entry_cmd(dev, *index, mac, vlan_valid, vlan);
  189. if (err)
  190. free_l2_table_index(l2_table, *index);
  191. return err;
  192. }
  193. static void del_l2_table_entry(struct mlx5_core_dev *dev, u32 index)
  194. {
  195. struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
  196. del_l2_table_entry_cmd(dev, index);
  197. free_l2_table_index(l2_table, index);
  198. }
  199. /* E-Switch FDB */
  200. static struct mlx5_flow_rule *
  201. __esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u32 vport, bool rx_rule,
  202. u8 mac_c[ETH_ALEN], u8 mac_v[ETH_ALEN])
  203. {
  204. int match_header = (is_zero_ether_addr(mac_c) ? 0 :
  205. MLX5_MATCH_OUTER_HEADERS);
  206. struct mlx5_flow_rule *flow_rule = NULL;
  207. struct mlx5_flow_destination dest;
  208. struct mlx5_flow_spec *spec;
  209. void *mv_misc = NULL;
  210. void *mc_misc = NULL;
  211. u8 *dmac_v = NULL;
  212. u8 *dmac_c = NULL;
  213. if (rx_rule)
  214. match_header |= MLX5_MATCH_MISC_PARAMETERS;
  215. spec = mlx5_vzalloc(sizeof(*spec));
  216. if (!spec) {
  217. esw_warn(esw->dev, "FDB: Failed to alloc match parameters\n");
  218. return NULL;
  219. }
  220. dmac_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
  221. outer_headers.dmac_47_16);
  222. dmac_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
  223. outer_headers.dmac_47_16);
  224. if (match_header & MLX5_MATCH_OUTER_HEADERS) {
  225. ether_addr_copy(dmac_v, mac_v);
  226. ether_addr_copy(dmac_c, mac_c);
  227. }
  228. if (match_header & MLX5_MATCH_MISC_PARAMETERS) {
  229. mv_misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
  230. misc_parameters);
  231. mc_misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
  232. misc_parameters);
  233. MLX5_SET(fte_match_set_misc, mv_misc, source_port, UPLINK_VPORT);
  234. MLX5_SET_TO_ONES(fte_match_set_misc, mc_misc, source_port);
  235. }
  236. dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
  237. dest.vport_num = vport;
  238. esw_debug(esw->dev,
  239. "\tFDB add rule dmac_v(%pM) dmac_c(%pM) -> vport(%d)\n",
  240. dmac_v, dmac_c, vport);
  241. spec->match_criteria_enable = match_header;
  242. flow_rule =
  243. mlx5_add_flow_rule(esw->fdb_table.fdb, spec,
  244. MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
  245. 0, &dest);
  246. if (IS_ERR(flow_rule)) {
  247. esw_warn(esw->dev,
  248. "FDB: Failed to add flow rule: dmac_v(%pM) dmac_c(%pM) -> vport(%d), err(%ld)\n",
  249. dmac_v, dmac_c, vport, PTR_ERR(flow_rule));
  250. flow_rule = NULL;
  251. }
  252. kvfree(spec);
  253. return flow_rule;
  254. }
  255. static struct mlx5_flow_rule *
  256. esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u8 mac[ETH_ALEN], u32 vport)
  257. {
  258. u8 mac_c[ETH_ALEN];
  259. eth_broadcast_addr(mac_c);
  260. return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac);
  261. }
  262. static struct mlx5_flow_rule *
  263. esw_fdb_set_vport_allmulti_rule(struct mlx5_eswitch *esw, u32 vport)
  264. {
  265. u8 mac_c[ETH_ALEN];
  266. u8 mac_v[ETH_ALEN];
  267. eth_zero_addr(mac_c);
  268. eth_zero_addr(mac_v);
  269. mac_c[0] = 0x01;
  270. mac_v[0] = 0x01;
  271. return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac_v);
  272. }
  273. static struct mlx5_flow_rule *
  274. esw_fdb_set_vport_promisc_rule(struct mlx5_eswitch *esw, u32 vport)
  275. {
  276. u8 mac_c[ETH_ALEN];
  277. u8 mac_v[ETH_ALEN];
  278. eth_zero_addr(mac_c);
  279. eth_zero_addr(mac_v);
  280. return __esw_fdb_set_vport_rule(esw, vport, true, mac_c, mac_v);
  281. }
  282. static int esw_create_legacy_fdb_table(struct mlx5_eswitch *esw, int nvports)
  283. {
  284. int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
  285. struct mlx5_core_dev *dev = esw->dev;
  286. struct mlx5_flow_namespace *root_ns;
  287. struct mlx5_flow_table *fdb;
  288. struct mlx5_flow_group *g;
  289. void *match_criteria;
  290. int table_size;
  291. u32 *flow_group_in;
  292. u8 *dmac;
  293. int err = 0;
  294. esw_debug(dev, "Create FDB log_max_size(%d)\n",
  295. MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
  296. root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
  297. if (!root_ns) {
  298. esw_warn(dev, "Failed to get FDB flow namespace\n");
  299. return -EOPNOTSUPP;
  300. }
  301. flow_group_in = mlx5_vzalloc(inlen);
  302. if (!flow_group_in)
  303. return -ENOMEM;
  304. memset(flow_group_in, 0, inlen);
  305. table_size = BIT(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
  306. fdb = mlx5_create_flow_table(root_ns, 0, table_size, 0);
  307. if (IS_ERR(fdb)) {
  308. err = PTR_ERR(fdb);
  309. esw_warn(dev, "Failed to create FDB Table err %d\n", err);
  310. goto out;
  311. }
  312. esw->fdb_table.fdb = fdb;
  313. /* Addresses group : Full match unicast/multicast addresses */
  314. MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
  315. MLX5_MATCH_OUTER_HEADERS);
  316. match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
  317. dmac = MLX5_ADDR_OF(fte_match_param, match_criteria, outer_headers.dmac_47_16);
  318. MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
  319. /* Preserve 2 entries for allmulti and promisc rules*/
  320. MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 3);
  321. eth_broadcast_addr(dmac);
  322. g = mlx5_create_flow_group(fdb, flow_group_in);
  323. if (IS_ERR(g)) {
  324. err = PTR_ERR(g);
  325. esw_warn(dev, "Failed to create flow group err(%d)\n", err);
  326. goto out;
  327. }
  328. esw->fdb_table.legacy.addr_grp = g;
  329. /* Allmulti group : One rule that forwards any mcast traffic */
  330. MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
  331. MLX5_MATCH_OUTER_HEADERS);
  332. MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 2);
  333. MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 2);
  334. eth_zero_addr(dmac);
  335. dmac[0] = 0x01;
  336. g = mlx5_create_flow_group(fdb, flow_group_in);
  337. if (IS_ERR(g)) {
  338. err = PTR_ERR(g);
  339. esw_warn(dev, "Failed to create allmulti flow group err(%d)\n", err);
  340. goto out;
  341. }
  342. esw->fdb_table.legacy.allmulti_grp = g;
  343. /* Promiscuous group :
  344. * One rule that forward all unmatched traffic from previous groups
  345. */
  346. eth_zero_addr(dmac);
  347. MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
  348. MLX5_MATCH_MISC_PARAMETERS);
  349. MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
  350. MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 1);
  351. MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 1);
  352. g = mlx5_create_flow_group(fdb, flow_group_in);
  353. if (IS_ERR(g)) {
  354. err = PTR_ERR(g);
  355. esw_warn(dev, "Failed to create promisc flow group err(%d)\n", err);
  356. goto out;
  357. }
  358. esw->fdb_table.legacy.promisc_grp = g;
  359. out:
  360. if (err) {
  361. if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.allmulti_grp)) {
  362. mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
  363. esw->fdb_table.legacy.allmulti_grp = NULL;
  364. }
  365. if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.addr_grp)) {
  366. mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
  367. esw->fdb_table.legacy.addr_grp = NULL;
  368. }
  369. if (!IS_ERR_OR_NULL(esw->fdb_table.fdb)) {
  370. mlx5_destroy_flow_table(esw->fdb_table.fdb);
  371. esw->fdb_table.fdb = NULL;
  372. }
  373. }
  374. kvfree(flow_group_in);
  375. return err;
  376. }
  377. static void esw_destroy_legacy_fdb_table(struct mlx5_eswitch *esw)
  378. {
  379. if (!esw->fdb_table.fdb)
  380. return;
  381. esw_debug(esw->dev, "Destroy FDB Table\n");
  382. mlx5_destroy_flow_group(esw->fdb_table.legacy.promisc_grp);
  383. mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
  384. mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
  385. mlx5_destroy_flow_table(esw->fdb_table.fdb);
  386. esw->fdb_table.fdb = NULL;
  387. esw->fdb_table.legacy.addr_grp = NULL;
  388. esw->fdb_table.legacy.allmulti_grp = NULL;
  389. esw->fdb_table.legacy.promisc_grp = NULL;
  390. }
  391. /* E-Switch vport UC/MC lists management */
  392. typedef int (*vport_addr_action)(struct mlx5_eswitch *esw,
  393. struct vport_addr *vaddr);
  394. static int esw_add_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
  395. {
  396. struct hlist_head *hash = esw->l2_table.l2_hash;
  397. struct esw_uc_addr *esw_uc;
  398. u8 *mac = vaddr->node.addr;
  399. u32 vport = vaddr->vport;
  400. int err;
  401. esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
  402. if (esw_uc) {
  403. esw_warn(esw->dev,
  404. "Failed to set L2 mac(%pM) for vport(%d), mac is already in use by vport(%d)\n",
  405. mac, vport, esw_uc->vport);
  406. return -EEXIST;
  407. }
  408. esw_uc = l2addr_hash_add(hash, mac, struct esw_uc_addr, GFP_KERNEL);
  409. if (!esw_uc)
  410. return -ENOMEM;
  411. esw_uc->vport = vport;
  412. err = set_l2_table_entry(esw->dev, mac, 0, 0, &esw_uc->table_index);
  413. if (err)
  414. goto abort;
  415. /* SRIOV is enabled: Forward UC MAC to vport */
  416. if (esw->fdb_table.fdb && esw->mode == SRIOV_LEGACY)
  417. vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
  418. esw_debug(esw->dev, "\tADDED UC MAC: vport[%d] %pM index:%d fr(%p)\n",
  419. vport, mac, esw_uc->table_index, vaddr->flow_rule);
  420. return err;
  421. abort:
  422. l2addr_hash_del(esw_uc);
  423. return err;
  424. }
  425. static int esw_del_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
  426. {
  427. struct hlist_head *hash = esw->l2_table.l2_hash;
  428. struct esw_uc_addr *esw_uc;
  429. u8 *mac = vaddr->node.addr;
  430. u32 vport = vaddr->vport;
  431. esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
  432. if (!esw_uc || esw_uc->vport != vport) {
  433. esw_debug(esw->dev,
  434. "MAC(%pM) doesn't belong to vport (%d)\n",
  435. mac, vport);
  436. return -EINVAL;
  437. }
  438. esw_debug(esw->dev, "\tDELETE UC MAC: vport[%d] %pM index:%d fr(%p)\n",
  439. vport, mac, esw_uc->table_index, vaddr->flow_rule);
  440. del_l2_table_entry(esw->dev, esw_uc->table_index);
  441. if (vaddr->flow_rule)
  442. mlx5_del_flow_rule(vaddr->flow_rule);
  443. vaddr->flow_rule = NULL;
  444. l2addr_hash_del(esw_uc);
  445. return 0;
  446. }
  447. static void update_allmulti_vports(struct mlx5_eswitch *esw,
  448. struct vport_addr *vaddr,
  449. struct esw_mc_addr *esw_mc)
  450. {
  451. u8 *mac = vaddr->node.addr;
  452. u32 vport_idx = 0;
  453. for (vport_idx = 0; vport_idx < esw->total_vports; vport_idx++) {
  454. struct mlx5_vport *vport = &esw->vports[vport_idx];
  455. struct hlist_head *vport_hash = vport->mc_list;
  456. struct vport_addr *iter_vaddr =
  457. l2addr_hash_find(vport_hash,
  458. mac,
  459. struct vport_addr);
  460. if (IS_ERR_OR_NULL(vport->allmulti_rule) ||
  461. vaddr->vport == vport_idx)
  462. continue;
  463. switch (vaddr->action) {
  464. case MLX5_ACTION_ADD:
  465. if (iter_vaddr)
  466. continue;
  467. iter_vaddr = l2addr_hash_add(vport_hash, mac,
  468. struct vport_addr,
  469. GFP_KERNEL);
  470. if (!iter_vaddr) {
  471. esw_warn(esw->dev,
  472. "ALL-MULTI: Failed to add MAC(%pM) to vport[%d] DB\n",
  473. mac, vport_idx);
  474. continue;
  475. }
  476. iter_vaddr->vport = vport_idx;
  477. iter_vaddr->flow_rule =
  478. esw_fdb_set_vport_rule(esw,
  479. mac,
  480. vport_idx);
  481. iter_vaddr->mc_promisc = true;
  482. break;
  483. case MLX5_ACTION_DEL:
  484. if (!iter_vaddr)
  485. continue;
  486. mlx5_del_flow_rule(iter_vaddr->flow_rule);
  487. l2addr_hash_del(iter_vaddr);
  488. break;
  489. }
  490. }
  491. }
  492. static int esw_add_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
  493. {
  494. struct hlist_head *hash = esw->mc_table;
  495. struct esw_mc_addr *esw_mc;
  496. u8 *mac = vaddr->node.addr;
  497. u32 vport = vaddr->vport;
  498. if (!esw->fdb_table.fdb)
  499. return 0;
  500. esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
  501. if (esw_mc)
  502. goto add;
  503. esw_mc = l2addr_hash_add(hash, mac, struct esw_mc_addr, GFP_KERNEL);
  504. if (!esw_mc)
  505. return -ENOMEM;
  506. esw_mc->uplink_rule = /* Forward MC MAC to Uplink */
  507. esw_fdb_set_vport_rule(esw, mac, UPLINK_VPORT);
  508. /* Add this multicast mac to all the mc promiscuous vports */
  509. update_allmulti_vports(esw, vaddr, esw_mc);
  510. add:
  511. /* If the multicast mac is added as a result of mc promiscuous vport,
  512. * don't increment the multicast ref count
  513. */
  514. if (!vaddr->mc_promisc)
  515. esw_mc->refcnt++;
  516. /* Forward MC MAC to vport */
  517. vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
  518. esw_debug(esw->dev,
  519. "\tADDED MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
  520. vport, mac, vaddr->flow_rule,
  521. esw_mc->refcnt, esw_mc->uplink_rule);
  522. return 0;
  523. }
  524. static int esw_del_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
  525. {
  526. struct hlist_head *hash = esw->mc_table;
  527. struct esw_mc_addr *esw_mc;
  528. u8 *mac = vaddr->node.addr;
  529. u32 vport = vaddr->vport;
  530. if (!esw->fdb_table.fdb)
  531. return 0;
  532. esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
  533. if (!esw_mc) {
  534. esw_warn(esw->dev,
  535. "Failed to find eswitch MC addr for MAC(%pM) vport(%d)",
  536. mac, vport);
  537. return -EINVAL;
  538. }
  539. esw_debug(esw->dev,
  540. "\tDELETE MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
  541. vport, mac, vaddr->flow_rule, esw_mc->refcnt,
  542. esw_mc->uplink_rule);
  543. if (vaddr->flow_rule)
  544. mlx5_del_flow_rule(vaddr->flow_rule);
  545. vaddr->flow_rule = NULL;
  546. /* If the multicast mac is added as a result of mc promiscuous vport,
  547. * don't decrement the multicast ref count.
  548. */
  549. if (vaddr->mc_promisc || (--esw_mc->refcnt > 0))
  550. return 0;
  551. /* Remove this multicast mac from all the mc promiscuous vports */
  552. update_allmulti_vports(esw, vaddr, esw_mc);
  553. if (esw_mc->uplink_rule)
  554. mlx5_del_flow_rule(esw_mc->uplink_rule);
  555. l2addr_hash_del(esw_mc);
  556. return 0;
  557. }
  558. /* Apply vport UC/MC list to HW l2 table and FDB table */
  559. static void esw_apply_vport_addr_list(struct mlx5_eswitch *esw,
  560. u32 vport_num, int list_type)
  561. {
  562. struct mlx5_vport *vport = &esw->vports[vport_num];
  563. bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
  564. vport_addr_action vport_addr_add;
  565. vport_addr_action vport_addr_del;
  566. struct vport_addr *addr;
  567. struct l2addr_node *node;
  568. struct hlist_head *hash;
  569. struct hlist_node *tmp;
  570. int hi;
  571. vport_addr_add = is_uc ? esw_add_uc_addr :
  572. esw_add_mc_addr;
  573. vport_addr_del = is_uc ? esw_del_uc_addr :
  574. esw_del_mc_addr;
  575. hash = is_uc ? vport->uc_list : vport->mc_list;
  576. for_each_l2hash_node(node, tmp, hash, hi) {
  577. addr = container_of(node, struct vport_addr, node);
  578. switch (addr->action) {
  579. case MLX5_ACTION_ADD:
  580. vport_addr_add(esw, addr);
  581. addr->action = MLX5_ACTION_NONE;
  582. break;
  583. case MLX5_ACTION_DEL:
  584. vport_addr_del(esw, addr);
  585. l2addr_hash_del(addr);
  586. break;
  587. }
  588. }
  589. }
  590. /* Sync vport UC/MC list from vport context */
  591. static void esw_update_vport_addr_list(struct mlx5_eswitch *esw,
  592. u32 vport_num, int list_type)
  593. {
  594. struct mlx5_vport *vport = &esw->vports[vport_num];
  595. bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
  596. u8 (*mac_list)[ETH_ALEN];
  597. struct l2addr_node *node;
  598. struct vport_addr *addr;
  599. struct hlist_head *hash;
  600. struct hlist_node *tmp;
  601. int size;
  602. int err;
  603. int hi;
  604. int i;
  605. size = is_uc ? MLX5_MAX_UC_PER_VPORT(esw->dev) :
  606. MLX5_MAX_MC_PER_VPORT(esw->dev);
  607. mac_list = kcalloc(size, ETH_ALEN, GFP_KERNEL);
  608. if (!mac_list)
  609. return;
  610. hash = is_uc ? vport->uc_list : vport->mc_list;
  611. for_each_l2hash_node(node, tmp, hash, hi) {
  612. addr = container_of(node, struct vport_addr, node);
  613. addr->action = MLX5_ACTION_DEL;
  614. }
  615. if (!vport->enabled)
  616. goto out;
  617. err = mlx5_query_nic_vport_mac_list(esw->dev, vport_num, list_type,
  618. mac_list, &size);
  619. if (err)
  620. goto out;
  621. esw_debug(esw->dev, "vport[%d] context update %s list size (%d)\n",
  622. vport_num, is_uc ? "UC" : "MC", size);
  623. for (i = 0; i < size; i++) {
  624. if (is_uc && !is_valid_ether_addr(mac_list[i]))
  625. continue;
  626. if (!is_uc && !is_multicast_ether_addr(mac_list[i]))
  627. continue;
  628. addr = l2addr_hash_find(hash, mac_list[i], struct vport_addr);
  629. if (addr) {
  630. addr->action = MLX5_ACTION_NONE;
  631. /* If this mac was previously added because of allmulti
  632. * promiscuous rx mode, its now converted to be original
  633. * vport mac.
  634. */
  635. if (addr->mc_promisc) {
  636. struct esw_mc_addr *esw_mc =
  637. l2addr_hash_find(esw->mc_table,
  638. mac_list[i],
  639. struct esw_mc_addr);
  640. if (!esw_mc) {
  641. esw_warn(esw->dev,
  642. "Failed to MAC(%pM) in mcast DB\n",
  643. mac_list[i]);
  644. continue;
  645. }
  646. esw_mc->refcnt++;
  647. addr->mc_promisc = false;
  648. }
  649. continue;
  650. }
  651. addr = l2addr_hash_add(hash, mac_list[i], struct vport_addr,
  652. GFP_KERNEL);
  653. if (!addr) {
  654. esw_warn(esw->dev,
  655. "Failed to add MAC(%pM) to vport[%d] DB\n",
  656. mac_list[i], vport_num);
  657. continue;
  658. }
  659. addr->vport = vport_num;
  660. addr->action = MLX5_ACTION_ADD;
  661. }
  662. out:
  663. kfree(mac_list);
  664. }
  665. /* Sync vport UC/MC list from vport context
  666. * Must be called after esw_update_vport_addr_list
  667. */
  668. static void esw_update_vport_mc_promisc(struct mlx5_eswitch *esw, u32 vport_num)
  669. {
  670. struct mlx5_vport *vport = &esw->vports[vport_num];
  671. struct l2addr_node *node;
  672. struct vport_addr *addr;
  673. struct hlist_head *hash;
  674. struct hlist_node *tmp;
  675. int hi;
  676. hash = vport->mc_list;
  677. for_each_l2hash_node(node, tmp, esw->mc_table, hi) {
  678. u8 *mac = node->addr;
  679. addr = l2addr_hash_find(hash, mac, struct vport_addr);
  680. if (addr) {
  681. if (addr->action == MLX5_ACTION_DEL)
  682. addr->action = MLX5_ACTION_NONE;
  683. continue;
  684. }
  685. addr = l2addr_hash_add(hash, mac, struct vport_addr,
  686. GFP_KERNEL);
  687. if (!addr) {
  688. esw_warn(esw->dev,
  689. "Failed to add allmulti MAC(%pM) to vport[%d] DB\n",
  690. mac, vport_num);
  691. continue;
  692. }
  693. addr->vport = vport_num;
  694. addr->action = MLX5_ACTION_ADD;
  695. addr->mc_promisc = true;
  696. }
  697. }
  698. /* Apply vport rx mode to HW FDB table */
  699. static void esw_apply_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num,
  700. bool promisc, bool mc_promisc)
  701. {
  702. struct esw_mc_addr *allmulti_addr = esw->mc_promisc;
  703. struct mlx5_vport *vport = &esw->vports[vport_num];
  704. if (IS_ERR_OR_NULL(vport->allmulti_rule) != mc_promisc)
  705. goto promisc;
  706. if (mc_promisc) {
  707. vport->allmulti_rule =
  708. esw_fdb_set_vport_allmulti_rule(esw, vport_num);
  709. if (!allmulti_addr->uplink_rule)
  710. allmulti_addr->uplink_rule =
  711. esw_fdb_set_vport_allmulti_rule(esw,
  712. UPLINK_VPORT);
  713. allmulti_addr->refcnt++;
  714. } else if (vport->allmulti_rule) {
  715. mlx5_del_flow_rule(vport->allmulti_rule);
  716. vport->allmulti_rule = NULL;
  717. if (--allmulti_addr->refcnt > 0)
  718. goto promisc;
  719. if (allmulti_addr->uplink_rule)
  720. mlx5_del_flow_rule(allmulti_addr->uplink_rule);
  721. allmulti_addr->uplink_rule = NULL;
  722. }
  723. promisc:
  724. if (IS_ERR_OR_NULL(vport->promisc_rule) != promisc)
  725. return;
  726. if (promisc) {
  727. vport->promisc_rule = esw_fdb_set_vport_promisc_rule(esw,
  728. vport_num);
  729. } else if (vport->promisc_rule) {
  730. mlx5_del_flow_rule(vport->promisc_rule);
  731. vport->promisc_rule = NULL;
  732. }
  733. }
  734. /* Sync vport rx mode from vport context */
  735. static void esw_update_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num)
  736. {
  737. struct mlx5_vport *vport = &esw->vports[vport_num];
  738. int promisc_all = 0;
  739. int promisc_uc = 0;
  740. int promisc_mc = 0;
  741. int err;
  742. err = mlx5_query_nic_vport_promisc(esw->dev,
  743. vport_num,
  744. &promisc_uc,
  745. &promisc_mc,
  746. &promisc_all);
  747. if (err)
  748. return;
  749. esw_debug(esw->dev, "vport[%d] context update rx mode promisc_all=%d, all_multi=%d\n",
  750. vport_num, promisc_all, promisc_mc);
  751. if (!vport->info.trusted || !vport->enabled) {
  752. promisc_uc = 0;
  753. promisc_mc = 0;
  754. promisc_all = 0;
  755. }
  756. esw_apply_vport_rx_mode(esw, vport_num, promisc_all,
  757. (promisc_all || promisc_mc));
  758. }
  759. static void esw_vport_change_handle_locked(struct mlx5_vport *vport)
  760. {
  761. struct mlx5_core_dev *dev = vport->dev;
  762. struct mlx5_eswitch *esw = dev->priv.eswitch;
  763. u8 mac[ETH_ALEN];
  764. mlx5_query_nic_vport_mac_address(dev, vport->vport, mac);
  765. esw_debug(dev, "vport[%d] Context Changed: perm mac: %pM\n",
  766. vport->vport, mac);
  767. if (vport->enabled_events & UC_ADDR_CHANGE) {
  768. esw_update_vport_addr_list(esw, vport->vport,
  769. MLX5_NVPRT_LIST_TYPE_UC);
  770. esw_apply_vport_addr_list(esw, vport->vport,
  771. MLX5_NVPRT_LIST_TYPE_UC);
  772. }
  773. if (vport->enabled_events & MC_ADDR_CHANGE) {
  774. esw_update_vport_addr_list(esw, vport->vport,
  775. MLX5_NVPRT_LIST_TYPE_MC);
  776. }
  777. if (vport->enabled_events & PROMISC_CHANGE) {
  778. esw_update_vport_rx_mode(esw, vport->vport);
  779. if (!IS_ERR_OR_NULL(vport->allmulti_rule))
  780. esw_update_vport_mc_promisc(esw, vport->vport);
  781. }
  782. if (vport->enabled_events & (PROMISC_CHANGE | MC_ADDR_CHANGE)) {
  783. esw_apply_vport_addr_list(esw, vport->vport,
  784. MLX5_NVPRT_LIST_TYPE_MC);
  785. }
  786. esw_debug(esw->dev, "vport[%d] Context Changed: Done\n", vport->vport);
  787. if (vport->enabled)
  788. arm_vport_context_events_cmd(dev, vport->vport,
  789. vport->enabled_events);
  790. }
  791. static void esw_vport_change_handler(struct work_struct *work)
  792. {
  793. struct mlx5_vport *vport =
  794. container_of(work, struct mlx5_vport, vport_change_handler);
  795. struct mlx5_eswitch *esw = vport->dev->priv.eswitch;
  796. mutex_lock(&esw->state_lock);
  797. esw_vport_change_handle_locked(vport);
  798. mutex_unlock(&esw->state_lock);
  799. }
  800. static int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
  801. struct mlx5_vport *vport)
  802. {
  803. int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
  804. struct mlx5_flow_group *vlan_grp = NULL;
  805. struct mlx5_flow_group *drop_grp = NULL;
  806. struct mlx5_core_dev *dev = esw->dev;
  807. struct mlx5_flow_namespace *root_ns;
  808. struct mlx5_flow_table *acl;
  809. void *match_criteria;
  810. u32 *flow_group_in;
  811. /* The egress acl table contains 2 rules:
  812. * 1)Allow traffic with vlan_tag=vst_vlan_id
  813. * 2)Drop all other traffic.
  814. */
  815. int table_size = 2;
  816. int err = 0;
  817. if (!MLX5_CAP_ESW_EGRESS_ACL(dev, ft_support))
  818. return -EOPNOTSUPP;
  819. if (!IS_ERR_OR_NULL(vport->egress.acl))
  820. return 0;
  821. esw_debug(dev, "Create vport[%d] egress ACL log_max_size(%d)\n",
  822. vport->vport, MLX5_CAP_ESW_EGRESS_ACL(dev, log_max_ft_size));
  823. root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_EGRESS);
  824. if (!root_ns) {
  825. esw_warn(dev, "Failed to get E-Switch egress flow namespace\n");
  826. return -EOPNOTSUPP;
  827. }
  828. flow_group_in = mlx5_vzalloc(inlen);
  829. if (!flow_group_in)
  830. return -ENOMEM;
  831. acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
  832. if (IS_ERR(acl)) {
  833. err = PTR_ERR(acl);
  834. esw_warn(dev, "Failed to create E-Switch vport[%d] egress flow Table, err(%d)\n",
  835. vport->vport, err);
  836. goto out;
  837. }
  838. MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
  839. match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
  840. MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
  841. MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.first_vid);
  842. MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
  843. MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
  844. vlan_grp = mlx5_create_flow_group(acl, flow_group_in);
  845. if (IS_ERR(vlan_grp)) {
  846. err = PTR_ERR(vlan_grp);
  847. esw_warn(dev, "Failed to create E-Switch vport[%d] egress allowed vlans flow group, err(%d)\n",
  848. vport->vport, err);
  849. goto out;
  850. }
  851. memset(flow_group_in, 0, inlen);
  852. MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
  853. MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
  854. drop_grp = mlx5_create_flow_group(acl, flow_group_in);
  855. if (IS_ERR(drop_grp)) {
  856. err = PTR_ERR(drop_grp);
  857. esw_warn(dev, "Failed to create E-Switch vport[%d] egress drop flow group, err(%d)\n",
  858. vport->vport, err);
  859. goto out;
  860. }
  861. vport->egress.acl = acl;
  862. vport->egress.drop_grp = drop_grp;
  863. vport->egress.allowed_vlans_grp = vlan_grp;
  864. out:
  865. kvfree(flow_group_in);
  866. if (err && !IS_ERR_OR_NULL(vlan_grp))
  867. mlx5_destroy_flow_group(vlan_grp);
  868. if (err && !IS_ERR_OR_NULL(acl))
  869. mlx5_destroy_flow_table(acl);
  870. return err;
  871. }
  872. static void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
  873. struct mlx5_vport *vport)
  874. {
  875. if (!IS_ERR_OR_NULL(vport->egress.allowed_vlan))
  876. mlx5_del_flow_rule(vport->egress.allowed_vlan);
  877. if (!IS_ERR_OR_NULL(vport->egress.drop_rule))
  878. mlx5_del_flow_rule(vport->egress.drop_rule);
  879. vport->egress.allowed_vlan = NULL;
  880. vport->egress.drop_rule = NULL;
  881. }
  882. static void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
  883. struct mlx5_vport *vport)
  884. {
  885. if (IS_ERR_OR_NULL(vport->egress.acl))
  886. return;
  887. esw_debug(esw->dev, "Destroy vport[%d] E-Switch egress ACL\n", vport->vport);
  888. esw_vport_cleanup_egress_rules(esw, vport);
  889. mlx5_destroy_flow_group(vport->egress.allowed_vlans_grp);
  890. mlx5_destroy_flow_group(vport->egress.drop_grp);
  891. mlx5_destroy_flow_table(vport->egress.acl);
  892. vport->egress.allowed_vlans_grp = NULL;
  893. vport->egress.drop_grp = NULL;
  894. vport->egress.acl = NULL;
  895. }
  896. static int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
  897. struct mlx5_vport *vport)
  898. {
  899. int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
  900. struct mlx5_core_dev *dev = esw->dev;
  901. struct mlx5_flow_namespace *root_ns;
  902. struct mlx5_flow_table *acl;
  903. struct mlx5_flow_group *g;
  904. void *match_criteria;
  905. u32 *flow_group_in;
  906. /* The ingress acl table contains 4 groups
  907. * (2 active rules at the same time -
  908. * 1 allow rule from one of the first 3 groups.
  909. * 1 drop rule from the last group):
  910. * 1)Allow untagged traffic with smac=original mac.
  911. * 2)Allow untagged traffic.
  912. * 3)Allow traffic with smac=original mac.
  913. * 4)Drop all other traffic.
  914. */
  915. int table_size = 4;
  916. int err = 0;
  917. if (!MLX5_CAP_ESW_INGRESS_ACL(dev, ft_support))
  918. return -EOPNOTSUPP;
  919. if (!IS_ERR_OR_NULL(vport->ingress.acl))
  920. return 0;
  921. esw_debug(dev, "Create vport[%d] ingress ACL log_max_size(%d)\n",
  922. vport->vport, MLX5_CAP_ESW_INGRESS_ACL(dev, log_max_ft_size));
  923. root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS);
  924. if (!root_ns) {
  925. esw_warn(dev, "Failed to get E-Switch ingress flow namespace\n");
  926. return -EOPNOTSUPP;
  927. }
  928. flow_group_in = mlx5_vzalloc(inlen);
  929. if (!flow_group_in)
  930. return -ENOMEM;
  931. acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
  932. if (IS_ERR(acl)) {
  933. err = PTR_ERR(acl);
  934. esw_warn(dev, "Failed to create E-Switch vport[%d] ingress flow Table, err(%d)\n",
  935. vport->vport, err);
  936. goto out;
  937. }
  938. vport->ingress.acl = acl;
  939. match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
  940. MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
  941. MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
  942. MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
  943. MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
  944. MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
  945. MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
  946. g = mlx5_create_flow_group(acl, flow_group_in);
  947. if (IS_ERR(g)) {
  948. err = PTR_ERR(g);
  949. esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged spoofchk flow group, err(%d)\n",
  950. vport->vport, err);
  951. goto out;
  952. }
  953. vport->ingress.allow_untagged_spoofchk_grp = g;
  954. memset(flow_group_in, 0, inlen);
  955. MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
  956. MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
  957. MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
  958. MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
  959. g = mlx5_create_flow_group(acl, flow_group_in);
  960. if (IS_ERR(g)) {
  961. err = PTR_ERR(g);
  962. esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged flow group, err(%d)\n",
  963. vport->vport, err);
  964. goto out;
  965. }
  966. vport->ingress.allow_untagged_only_grp = g;
  967. memset(flow_group_in, 0, inlen);
  968. MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
  969. MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
  970. MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
  971. MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 2);
  972. MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 2);
  973. g = mlx5_create_flow_group(acl, flow_group_in);
  974. if (IS_ERR(g)) {
  975. err = PTR_ERR(g);
  976. esw_warn(dev, "Failed to create E-Switch vport[%d] ingress spoofchk flow group, err(%d)\n",
  977. vport->vport, err);
  978. goto out;
  979. }
  980. vport->ingress.allow_spoofchk_only_grp = g;
  981. memset(flow_group_in, 0, inlen);
  982. MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 3);
  983. MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 3);
  984. g = mlx5_create_flow_group(acl, flow_group_in);
  985. if (IS_ERR(g)) {
  986. err = PTR_ERR(g);
  987. esw_warn(dev, "Failed to create E-Switch vport[%d] ingress drop flow group, err(%d)\n",
  988. vport->vport, err);
  989. goto out;
  990. }
  991. vport->ingress.drop_grp = g;
  992. out:
  993. if (err) {
  994. if (!IS_ERR_OR_NULL(vport->ingress.allow_spoofchk_only_grp))
  995. mlx5_destroy_flow_group(
  996. vport->ingress.allow_spoofchk_only_grp);
  997. if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_only_grp))
  998. mlx5_destroy_flow_group(
  999. vport->ingress.allow_untagged_only_grp);
  1000. if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_spoofchk_grp))
  1001. mlx5_destroy_flow_group(
  1002. vport->ingress.allow_untagged_spoofchk_grp);
  1003. if (!IS_ERR_OR_NULL(vport->ingress.acl))
  1004. mlx5_destroy_flow_table(vport->ingress.acl);
  1005. }
  1006. kvfree(flow_group_in);
  1007. return err;
  1008. }
  1009. static void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
  1010. struct mlx5_vport *vport)
  1011. {
  1012. if (!IS_ERR_OR_NULL(vport->ingress.drop_rule))
  1013. mlx5_del_flow_rule(vport->ingress.drop_rule);
  1014. if (!IS_ERR_OR_NULL(vport->ingress.allow_rule))
  1015. mlx5_del_flow_rule(vport->ingress.allow_rule);
  1016. vport->ingress.drop_rule = NULL;
  1017. vport->ingress.allow_rule = NULL;
  1018. }
  1019. static void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
  1020. struct mlx5_vport *vport)
  1021. {
  1022. if (IS_ERR_OR_NULL(vport->ingress.acl))
  1023. return;
  1024. esw_debug(esw->dev, "Destroy vport[%d] E-Switch ingress ACL\n", vport->vport);
  1025. esw_vport_cleanup_ingress_rules(esw, vport);
  1026. mlx5_destroy_flow_group(vport->ingress.allow_spoofchk_only_grp);
  1027. mlx5_destroy_flow_group(vport->ingress.allow_untagged_only_grp);
  1028. mlx5_destroy_flow_group(vport->ingress.allow_untagged_spoofchk_grp);
  1029. mlx5_destroy_flow_group(vport->ingress.drop_grp);
  1030. mlx5_destroy_flow_table(vport->ingress.acl);
  1031. vport->ingress.acl = NULL;
  1032. vport->ingress.drop_grp = NULL;
  1033. vport->ingress.allow_spoofchk_only_grp = NULL;
  1034. vport->ingress.allow_untagged_only_grp = NULL;
  1035. vport->ingress.allow_untagged_spoofchk_grp = NULL;
  1036. }
  1037. static int esw_vport_ingress_config(struct mlx5_eswitch *esw,
  1038. struct mlx5_vport *vport)
  1039. {
  1040. struct mlx5_flow_spec *spec;
  1041. int err = 0;
  1042. u8 *smac_v;
  1043. if (vport->info.spoofchk && !is_valid_ether_addr(vport->info.mac)) {
  1044. mlx5_core_warn(esw->dev,
  1045. "vport[%d] configure ingress rules failed, illegal mac with spoofchk\n",
  1046. vport->vport);
  1047. return -EPERM;
  1048. }
  1049. esw_vport_cleanup_ingress_rules(esw, vport);
  1050. if (!vport->info.vlan && !vport->info.qos && !vport->info.spoofchk) {
  1051. esw_vport_disable_ingress_acl(esw, vport);
  1052. return 0;
  1053. }
  1054. err = esw_vport_enable_ingress_acl(esw, vport);
  1055. if (err) {
  1056. mlx5_core_warn(esw->dev,
  1057. "failed to enable ingress acl (%d) on vport[%d]\n",
  1058. err, vport->vport);
  1059. return err;
  1060. }
  1061. esw_debug(esw->dev,
  1062. "vport[%d] configure ingress rules, vlan(%d) qos(%d)\n",
  1063. vport->vport, vport->info.vlan, vport->info.qos);
  1064. spec = mlx5_vzalloc(sizeof(*spec));
  1065. if (!spec) {
  1066. err = -ENOMEM;
  1067. esw_warn(esw->dev, "vport[%d] configure ingress rules failed, err(%d)\n",
  1068. vport->vport, err);
  1069. goto out;
  1070. }
  1071. if (vport->info.vlan || vport->info.qos)
  1072. MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag);
  1073. if (vport->info.spoofchk) {
  1074. MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_47_16);
  1075. MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_15_0);
  1076. smac_v = MLX5_ADDR_OF(fte_match_param,
  1077. spec->match_value,
  1078. outer_headers.smac_47_16);
  1079. ether_addr_copy(smac_v, vport->info.mac);
  1080. }
  1081. spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
  1082. vport->ingress.allow_rule =
  1083. mlx5_add_flow_rule(vport->ingress.acl, spec,
  1084. MLX5_FLOW_CONTEXT_ACTION_ALLOW,
  1085. 0, NULL);
  1086. if (IS_ERR(vport->ingress.allow_rule)) {
  1087. err = PTR_ERR(vport->ingress.allow_rule);
  1088. esw_warn(esw->dev,
  1089. "vport[%d] configure ingress allow rule, err(%d)\n",
  1090. vport->vport, err);
  1091. vport->ingress.allow_rule = NULL;
  1092. goto out;
  1093. }
  1094. memset(spec, 0, sizeof(*spec));
  1095. vport->ingress.drop_rule =
  1096. mlx5_add_flow_rule(vport->ingress.acl, spec,
  1097. MLX5_FLOW_CONTEXT_ACTION_DROP,
  1098. 0, NULL);
  1099. if (IS_ERR(vport->ingress.drop_rule)) {
  1100. err = PTR_ERR(vport->ingress.drop_rule);
  1101. esw_warn(esw->dev,
  1102. "vport[%d] configure ingress drop rule, err(%d)\n",
  1103. vport->vport, err);
  1104. vport->ingress.drop_rule = NULL;
  1105. goto out;
  1106. }
  1107. out:
  1108. if (err)
  1109. esw_vport_cleanup_ingress_rules(esw, vport);
  1110. kvfree(spec);
  1111. return err;
  1112. }
  1113. static int esw_vport_egress_config(struct mlx5_eswitch *esw,
  1114. struct mlx5_vport *vport)
  1115. {
  1116. struct mlx5_flow_spec *spec;
  1117. int err = 0;
  1118. esw_vport_cleanup_egress_rules(esw, vport);
  1119. if (!vport->info.vlan && !vport->info.qos) {
  1120. esw_vport_disable_egress_acl(esw, vport);
  1121. return 0;
  1122. }
  1123. err = esw_vport_enable_egress_acl(esw, vport);
  1124. if (err) {
  1125. mlx5_core_warn(esw->dev,
  1126. "failed to enable egress acl (%d) on vport[%d]\n",
  1127. err, vport->vport);
  1128. return err;
  1129. }
  1130. esw_debug(esw->dev,
  1131. "vport[%d] configure egress rules, vlan(%d) qos(%d)\n",
  1132. vport->vport, vport->info.vlan, vport->info.qos);
  1133. spec = mlx5_vzalloc(sizeof(*spec));
  1134. if (!spec) {
  1135. err = -ENOMEM;
  1136. esw_warn(esw->dev, "vport[%d] configure egress rules failed, err(%d)\n",
  1137. vport->vport, err);
  1138. goto out;
  1139. }
  1140. /* Allowed vlan rule */
  1141. MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag);
  1142. MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.vlan_tag);
  1143. MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);
  1144. MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, vport->info.vlan);
  1145. spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
  1146. vport->egress.allowed_vlan =
  1147. mlx5_add_flow_rule(vport->egress.acl, spec,
  1148. MLX5_FLOW_CONTEXT_ACTION_ALLOW,
  1149. 0, NULL);
  1150. if (IS_ERR(vport->egress.allowed_vlan)) {
  1151. err = PTR_ERR(vport->egress.allowed_vlan);
  1152. esw_warn(esw->dev,
  1153. "vport[%d] configure egress allowed vlan rule failed, err(%d)\n",
  1154. vport->vport, err);
  1155. vport->egress.allowed_vlan = NULL;
  1156. goto out;
  1157. }
  1158. /* Drop others rule (star rule) */
  1159. memset(spec, 0, sizeof(*spec));
  1160. vport->egress.drop_rule =
  1161. mlx5_add_flow_rule(vport->egress.acl, spec,
  1162. MLX5_FLOW_CONTEXT_ACTION_DROP,
  1163. 0, NULL);
  1164. if (IS_ERR(vport->egress.drop_rule)) {
  1165. err = PTR_ERR(vport->egress.drop_rule);
  1166. esw_warn(esw->dev,
  1167. "vport[%d] configure egress drop rule failed, err(%d)\n",
  1168. vport->vport, err);
  1169. vport->egress.drop_rule = NULL;
  1170. }
  1171. out:
  1172. kvfree(spec);
  1173. return err;
  1174. }
  1175. static void node_guid_gen_from_mac(u64 *node_guid, u8 mac[ETH_ALEN])
  1176. {
  1177. ((u8 *)node_guid)[7] = mac[0];
  1178. ((u8 *)node_guid)[6] = mac[1];
  1179. ((u8 *)node_guid)[5] = mac[2];
  1180. ((u8 *)node_guid)[4] = 0xff;
  1181. ((u8 *)node_guid)[3] = 0xfe;
  1182. ((u8 *)node_guid)[2] = mac[3];
  1183. ((u8 *)node_guid)[1] = mac[4];
  1184. ((u8 *)node_guid)[0] = mac[5];
  1185. }
  1186. static void esw_apply_vport_conf(struct mlx5_eswitch *esw,
  1187. struct mlx5_vport *vport)
  1188. {
  1189. int vport_num = vport->vport;
  1190. if (!vport_num)
  1191. return;
  1192. mlx5_modify_vport_admin_state(esw->dev,
  1193. MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
  1194. vport_num,
  1195. vport->info.link_state);
  1196. mlx5_modify_nic_vport_mac_address(esw->dev, vport_num, vport->info.mac);
  1197. mlx5_modify_nic_vport_node_guid(esw->dev, vport_num, vport->info.node_guid);
  1198. modify_esw_vport_cvlan(esw->dev, vport_num, vport->info.vlan, vport->info.qos,
  1199. (vport->info.vlan || vport->info.qos));
  1200. /* Only legacy mode needs ACLs */
  1201. if (esw->mode == SRIOV_LEGACY) {
  1202. esw_vport_ingress_config(esw, vport);
  1203. esw_vport_egress_config(esw, vport);
  1204. }
  1205. }
  1206. static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num,
  1207. int enable_events)
  1208. {
  1209. struct mlx5_vport *vport = &esw->vports[vport_num];
  1210. mutex_lock(&esw->state_lock);
  1211. WARN_ON(vport->enabled);
  1212. esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num);
  1213. /* Restore old vport configuration */
  1214. esw_apply_vport_conf(esw, vport);
  1215. /* Sync with current vport context */
  1216. vport->enabled_events = enable_events;
  1217. vport->enabled = true;
  1218. /* only PF is trusted by default */
  1219. if (!vport_num)
  1220. vport->info.trusted = true;
  1221. esw_vport_change_handle_locked(vport);
  1222. esw->enabled_vports++;
  1223. esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num);
  1224. mutex_unlock(&esw->state_lock);
  1225. }
  1226. static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num)
  1227. {
  1228. struct mlx5_vport *vport = &esw->vports[vport_num];
  1229. if (!vport->enabled)
  1230. return;
  1231. esw_debug(esw->dev, "Disabling vport(%d)\n", vport_num);
  1232. /* Mark this vport as disabled to discard new events */
  1233. vport->enabled = false;
  1234. synchronize_irq(mlx5_get_msix_vec(esw->dev, MLX5_EQ_VEC_ASYNC));
  1235. /* Wait for current already scheduled events to complete */
  1236. flush_workqueue(esw->work_queue);
  1237. /* Disable events from this vport */
  1238. arm_vport_context_events_cmd(esw->dev, vport->vport, 0);
  1239. mutex_lock(&esw->state_lock);
  1240. /* We don't assume VFs will cleanup after themselves.
  1241. * Calling vport change handler while vport is disabled will cleanup
  1242. * the vport resources.
  1243. */
  1244. esw_vport_change_handle_locked(vport);
  1245. vport->enabled_events = 0;
  1246. if (vport_num && esw->mode == SRIOV_LEGACY) {
  1247. mlx5_modify_vport_admin_state(esw->dev,
  1248. MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
  1249. vport_num,
  1250. MLX5_ESW_VPORT_ADMIN_STATE_DOWN);
  1251. esw_vport_disable_egress_acl(esw, vport);
  1252. esw_vport_disable_ingress_acl(esw, vport);
  1253. }
  1254. esw->enabled_vports--;
  1255. mutex_unlock(&esw->state_lock);
  1256. }
  1257. /* Public E-Switch API */
  1258. int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode)
  1259. {
  1260. int err;
  1261. int i, enabled_events;
  1262. if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
  1263. MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
  1264. return 0;
  1265. if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) ||
  1266. !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ft_support)) {
  1267. esw_warn(esw->dev, "E-Switch FDB is not supported, aborting ...\n");
  1268. return -ENOTSUPP;
  1269. }
  1270. if (!MLX5_CAP_ESW_INGRESS_ACL(esw->dev, ft_support))
  1271. esw_warn(esw->dev, "E-Switch ingress ACL is not supported by FW\n");
  1272. if (!MLX5_CAP_ESW_EGRESS_ACL(esw->dev, ft_support))
  1273. esw_warn(esw->dev, "E-Switch engress ACL is not supported by FW\n");
  1274. esw_info(esw->dev, "E-Switch enable SRIOV: nvfs(%d) mode (%d)\n", nvfs, mode);
  1275. esw->mode = mode;
  1276. esw_disable_vport(esw, 0);
  1277. if (mode == SRIOV_LEGACY)
  1278. err = esw_create_legacy_fdb_table(esw, nvfs + 1);
  1279. else
  1280. err = esw_offloads_init(esw, nvfs + 1);
  1281. if (err)
  1282. goto abort;
  1283. enabled_events = (mode == SRIOV_LEGACY) ? SRIOV_VPORT_EVENTS : UC_ADDR_CHANGE;
  1284. for (i = 0; i <= nvfs; i++)
  1285. esw_enable_vport(esw, i, enabled_events);
  1286. esw_info(esw->dev, "SRIOV enabled: active vports(%d)\n",
  1287. esw->enabled_vports);
  1288. return 0;
  1289. abort:
  1290. esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
  1291. esw->mode = SRIOV_NONE;
  1292. return err;
  1293. }
  1294. void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw)
  1295. {
  1296. struct esw_mc_addr *mc_promisc;
  1297. int nvports;
  1298. int i;
  1299. if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
  1300. MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
  1301. return;
  1302. esw_info(esw->dev, "disable SRIOV: active vports(%d) mode(%d)\n",
  1303. esw->enabled_vports, esw->mode);
  1304. mc_promisc = esw->mc_promisc;
  1305. nvports = esw->enabled_vports;
  1306. for (i = 0; i < esw->total_vports; i++)
  1307. esw_disable_vport(esw, i);
  1308. if (mc_promisc && mc_promisc->uplink_rule)
  1309. mlx5_del_flow_rule(mc_promisc->uplink_rule);
  1310. if (esw->mode == SRIOV_LEGACY)
  1311. esw_destroy_legacy_fdb_table(esw);
  1312. else if (esw->mode == SRIOV_OFFLOADS)
  1313. esw_offloads_cleanup(esw, nvports);
  1314. esw->mode = SRIOV_NONE;
  1315. /* VPORT 0 (PF) must be enabled back with non-sriov configuration */
  1316. esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
  1317. }
  1318. void mlx5_eswitch_attach(struct mlx5_eswitch *esw)
  1319. {
  1320. if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
  1321. MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
  1322. return;
  1323. esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
  1324. /* VF Vports will be enabled when SRIOV is enabled */
  1325. }
  1326. void mlx5_eswitch_detach(struct mlx5_eswitch *esw)
  1327. {
  1328. if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
  1329. MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
  1330. return;
  1331. esw_disable_vport(esw, 0);
  1332. }
  1333. int mlx5_eswitch_init(struct mlx5_core_dev *dev)
  1334. {
  1335. int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table);
  1336. int total_vports = MLX5_TOTAL_VPORTS(dev);
  1337. struct esw_mc_addr *mc_promisc;
  1338. struct mlx5_eswitch *esw;
  1339. int vport_num;
  1340. int err;
  1341. if (!MLX5_CAP_GEN(dev, vport_group_manager) ||
  1342. MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
  1343. return 0;
  1344. esw_info(dev,
  1345. "Total vports %d, l2 table size(%d), per vport: max uc(%d) max mc(%d)\n",
  1346. total_vports, l2_table_size,
  1347. MLX5_MAX_UC_PER_VPORT(dev),
  1348. MLX5_MAX_MC_PER_VPORT(dev));
  1349. esw = kzalloc(sizeof(*esw), GFP_KERNEL);
  1350. if (!esw)
  1351. return -ENOMEM;
  1352. esw->dev = dev;
  1353. esw->l2_table.bitmap = kcalloc(BITS_TO_LONGS(l2_table_size),
  1354. sizeof(uintptr_t), GFP_KERNEL);
  1355. if (!esw->l2_table.bitmap) {
  1356. err = -ENOMEM;
  1357. goto abort;
  1358. }
  1359. esw->l2_table.size = l2_table_size;
  1360. mc_promisc = kzalloc(sizeof(*mc_promisc), GFP_KERNEL);
  1361. if (!mc_promisc) {
  1362. err = -ENOMEM;
  1363. goto abort;
  1364. }
  1365. esw->mc_promisc = mc_promisc;
  1366. esw->work_queue = create_singlethread_workqueue("mlx5_esw_wq");
  1367. if (!esw->work_queue) {
  1368. err = -ENOMEM;
  1369. goto abort;
  1370. }
  1371. esw->vports = kcalloc(total_vports, sizeof(struct mlx5_vport),
  1372. GFP_KERNEL);
  1373. if (!esw->vports) {
  1374. err = -ENOMEM;
  1375. goto abort;
  1376. }
  1377. esw->offloads.vport_reps =
  1378. kzalloc(total_vports * sizeof(struct mlx5_eswitch_rep),
  1379. GFP_KERNEL);
  1380. if (!esw->offloads.vport_reps) {
  1381. err = -ENOMEM;
  1382. goto abort;
  1383. }
  1384. mutex_init(&esw->state_lock);
  1385. for (vport_num = 0; vport_num < total_vports; vport_num++) {
  1386. struct mlx5_vport *vport = &esw->vports[vport_num];
  1387. vport->vport = vport_num;
  1388. vport->info.link_state = MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
  1389. vport->dev = dev;
  1390. INIT_WORK(&vport->vport_change_handler,
  1391. esw_vport_change_handler);
  1392. }
  1393. esw->total_vports = total_vports;
  1394. esw->enabled_vports = 0;
  1395. esw->mode = SRIOV_NONE;
  1396. dev->priv.eswitch = esw;
  1397. return 0;
  1398. abort:
  1399. if (esw->work_queue)
  1400. destroy_workqueue(esw->work_queue);
  1401. kfree(esw->l2_table.bitmap);
  1402. kfree(esw->vports);
  1403. kfree(esw->offloads.vport_reps);
  1404. kfree(esw);
  1405. return err;
  1406. }
  1407. void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw)
  1408. {
  1409. if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
  1410. MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
  1411. return;
  1412. esw_info(esw->dev, "cleanup\n");
  1413. esw->dev->priv.eswitch = NULL;
  1414. destroy_workqueue(esw->work_queue);
  1415. kfree(esw->l2_table.bitmap);
  1416. kfree(esw->mc_promisc);
  1417. kfree(esw->offloads.vport_reps);
  1418. kfree(esw->vports);
  1419. kfree(esw);
  1420. }
  1421. void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe)
  1422. {
  1423. struct mlx5_eqe_vport_change *vc_eqe = &eqe->data.vport_change;
  1424. u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
  1425. struct mlx5_vport *vport;
  1426. if (!esw) {
  1427. pr_warn("MLX5 E-Switch: vport %d got an event while eswitch is not initialized\n",
  1428. vport_num);
  1429. return;
  1430. }
  1431. vport = &esw->vports[vport_num];
  1432. if (vport->enabled)
  1433. queue_work(esw->work_queue, &vport->vport_change_handler);
  1434. }
  1435. /* Vport Administration */
  1436. #define ESW_ALLOWED(esw) \
  1437. (esw && MLX5_CAP_GEN(esw->dev, vport_group_manager) && mlx5_core_is_pf(esw->dev))
  1438. #define LEGAL_VPORT(esw, vport) (vport >= 0 && vport < esw->total_vports)
  1439. int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
  1440. int vport, u8 mac[ETH_ALEN])
  1441. {
  1442. struct mlx5_vport *evport;
  1443. u64 node_guid;
  1444. int err = 0;
  1445. if (!ESW_ALLOWED(esw))
  1446. return -EPERM;
  1447. if (!LEGAL_VPORT(esw, vport) || is_multicast_ether_addr(mac))
  1448. return -EINVAL;
  1449. mutex_lock(&esw->state_lock);
  1450. evport = &esw->vports[vport];
  1451. if (evport->info.spoofchk && !is_valid_ether_addr(mac)) {
  1452. mlx5_core_warn(esw->dev,
  1453. "MAC invalidation is not allowed when spoofchk is on, vport(%d)\n",
  1454. vport);
  1455. err = -EPERM;
  1456. goto unlock;
  1457. }
  1458. err = mlx5_modify_nic_vport_mac_address(esw->dev, vport, mac);
  1459. if (err) {
  1460. mlx5_core_warn(esw->dev,
  1461. "Failed to mlx5_modify_nic_vport_mac vport(%d) err=(%d)\n",
  1462. vport, err);
  1463. goto unlock;
  1464. }
  1465. node_guid_gen_from_mac(&node_guid, mac);
  1466. err = mlx5_modify_nic_vport_node_guid(esw->dev, vport, node_guid);
  1467. if (err)
  1468. mlx5_core_warn(esw->dev,
  1469. "Failed to set vport %d node guid, err = %d. RDMA_CM will not function properly for this VF.\n",
  1470. vport, err);
  1471. ether_addr_copy(evport->info.mac, mac);
  1472. evport->info.node_guid = node_guid;
  1473. if (evport->enabled && esw->mode == SRIOV_LEGACY)
  1474. err = esw_vport_ingress_config(esw, evport);
  1475. unlock:
  1476. mutex_unlock(&esw->state_lock);
  1477. return err;
  1478. }
  1479. int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
  1480. int vport, int link_state)
  1481. {
  1482. struct mlx5_vport *evport;
  1483. int err = 0;
  1484. if (!ESW_ALLOWED(esw))
  1485. return -EPERM;
  1486. if (!LEGAL_VPORT(esw, vport))
  1487. return -EINVAL;
  1488. mutex_lock(&esw->state_lock);
  1489. evport = &esw->vports[vport];
  1490. err = mlx5_modify_vport_admin_state(esw->dev,
  1491. MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
  1492. vport, link_state);
  1493. if (err) {
  1494. mlx5_core_warn(esw->dev,
  1495. "Failed to set vport %d link state, err = %d",
  1496. vport, err);
  1497. goto unlock;
  1498. }
  1499. evport->info.link_state = link_state;
  1500. unlock:
  1501. mutex_unlock(&esw->state_lock);
  1502. return 0;
  1503. }
  1504. int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
  1505. int vport, struct ifla_vf_info *ivi)
  1506. {
  1507. struct mlx5_vport *evport;
  1508. if (!ESW_ALLOWED(esw))
  1509. return -EPERM;
  1510. if (!LEGAL_VPORT(esw, vport))
  1511. return -EINVAL;
  1512. evport = &esw->vports[vport];
  1513. memset(ivi, 0, sizeof(*ivi));
  1514. ivi->vf = vport - 1;
  1515. mutex_lock(&esw->state_lock);
  1516. ether_addr_copy(ivi->mac, evport->info.mac);
  1517. ivi->linkstate = evport->info.link_state;
  1518. ivi->vlan = evport->info.vlan;
  1519. ivi->qos = evport->info.qos;
  1520. ivi->spoofchk = evport->info.spoofchk;
  1521. ivi->trusted = evport->info.trusted;
  1522. mutex_unlock(&esw->state_lock);
  1523. return 0;
  1524. }
  1525. int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
  1526. int vport, u16 vlan, u8 qos, u8 set_flags)
  1527. {
  1528. struct mlx5_vport *evport;
  1529. int err = 0;
  1530. if (!ESW_ALLOWED(esw))
  1531. return -EPERM;
  1532. if (!LEGAL_VPORT(esw, vport) || (vlan > 4095) || (qos > 7))
  1533. return -EINVAL;
  1534. mutex_lock(&esw->state_lock);
  1535. evport = &esw->vports[vport];
  1536. err = modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set_flags);
  1537. if (err)
  1538. goto unlock;
  1539. evport->info.vlan = vlan;
  1540. evport->info.qos = qos;
  1541. if (evport->enabled && esw->mode == SRIOV_LEGACY) {
  1542. err = esw_vport_ingress_config(esw, evport);
  1543. if (err)
  1544. goto unlock;
  1545. err = esw_vport_egress_config(esw, evport);
  1546. }
  1547. unlock:
  1548. mutex_unlock(&esw->state_lock);
  1549. return err;
  1550. }
  1551. int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
  1552. int vport, u16 vlan, u8 qos)
  1553. {
  1554. u8 set_flags = 0;
  1555. if (vlan || qos)
  1556. set_flags = SET_VLAN_STRIP | SET_VLAN_INSERT;
  1557. return __mlx5_eswitch_set_vport_vlan(esw, vport, vlan, qos, set_flags);
  1558. }
  1559. int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
  1560. int vport, bool spoofchk)
  1561. {
  1562. struct mlx5_vport *evport;
  1563. bool pschk;
  1564. int err = 0;
  1565. if (!ESW_ALLOWED(esw))
  1566. return -EPERM;
  1567. if (!LEGAL_VPORT(esw, vport))
  1568. return -EINVAL;
  1569. mutex_lock(&esw->state_lock);
  1570. evport = &esw->vports[vport];
  1571. pschk = evport->info.spoofchk;
  1572. evport->info.spoofchk = spoofchk;
  1573. if (evport->enabled && esw->mode == SRIOV_LEGACY)
  1574. err = esw_vport_ingress_config(esw, evport);
  1575. if (err)
  1576. evport->info.spoofchk = pschk;
  1577. mutex_unlock(&esw->state_lock);
  1578. return err;
  1579. }
  1580. int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
  1581. int vport, bool setting)
  1582. {
  1583. struct mlx5_vport *evport;
  1584. if (!ESW_ALLOWED(esw))
  1585. return -EPERM;
  1586. if (!LEGAL_VPORT(esw, vport))
  1587. return -EINVAL;
  1588. mutex_lock(&esw->state_lock);
  1589. evport = &esw->vports[vport];
  1590. evport->info.trusted = setting;
  1591. if (evport->enabled)
  1592. esw_vport_change_handle_locked(evport);
  1593. mutex_unlock(&esw->state_lock);
  1594. return 0;
  1595. }
  1596. int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
  1597. int vport,
  1598. struct ifla_vf_stats *vf_stats)
  1599. {
  1600. int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
  1601. u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
  1602. int err = 0;
  1603. u32 *out;
  1604. if (!ESW_ALLOWED(esw))
  1605. return -EPERM;
  1606. if (!LEGAL_VPORT(esw, vport))
  1607. return -EINVAL;
  1608. out = mlx5_vzalloc(outlen);
  1609. if (!out)
  1610. return -ENOMEM;
  1611. MLX5_SET(query_vport_counter_in, in, opcode,
  1612. MLX5_CMD_OP_QUERY_VPORT_COUNTER);
  1613. MLX5_SET(query_vport_counter_in, in, op_mod, 0);
  1614. MLX5_SET(query_vport_counter_in, in, vport_number, vport);
  1615. if (vport)
  1616. MLX5_SET(query_vport_counter_in, in, other_vport, 1);
  1617. memset(out, 0, outlen);
  1618. err = mlx5_cmd_exec(esw->dev, in, sizeof(in), out, outlen);
  1619. if (err)
  1620. goto free_out;
  1621. #define MLX5_GET_CTR(p, x) \
  1622. MLX5_GET64(query_vport_counter_out, p, x)
  1623. memset(vf_stats, 0, sizeof(*vf_stats));
  1624. vf_stats->rx_packets =
  1625. MLX5_GET_CTR(out, received_eth_unicast.packets) +
  1626. MLX5_GET_CTR(out, received_ib_unicast.packets) +
  1627. MLX5_GET_CTR(out, received_eth_multicast.packets) +
  1628. MLX5_GET_CTR(out, received_ib_multicast.packets) +
  1629. MLX5_GET_CTR(out, received_eth_broadcast.packets);
  1630. vf_stats->rx_bytes =
  1631. MLX5_GET_CTR(out, received_eth_unicast.octets) +
  1632. MLX5_GET_CTR(out, received_ib_unicast.octets) +
  1633. MLX5_GET_CTR(out, received_eth_multicast.octets) +
  1634. MLX5_GET_CTR(out, received_ib_multicast.octets) +
  1635. MLX5_GET_CTR(out, received_eth_broadcast.octets);
  1636. vf_stats->tx_packets =
  1637. MLX5_GET_CTR(out, transmitted_eth_unicast.packets) +
  1638. MLX5_GET_CTR(out, transmitted_ib_unicast.packets) +
  1639. MLX5_GET_CTR(out, transmitted_eth_multicast.packets) +
  1640. MLX5_GET_CTR(out, transmitted_ib_multicast.packets) +
  1641. MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
  1642. vf_stats->tx_bytes =
  1643. MLX5_GET_CTR(out, transmitted_eth_unicast.octets) +
  1644. MLX5_GET_CTR(out, transmitted_ib_unicast.octets) +
  1645. MLX5_GET_CTR(out, transmitted_eth_multicast.octets) +
  1646. MLX5_GET_CTR(out, transmitted_ib_multicast.octets) +
  1647. MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
  1648. vf_stats->multicast =
  1649. MLX5_GET_CTR(out, received_eth_multicast.packets) +
  1650. MLX5_GET_CTR(out, received_ib_multicast.packets);
  1651. vf_stats->broadcast =
  1652. MLX5_GET_CTR(out, received_eth_broadcast.packets);
  1653. free_out:
  1654. kvfree(out);
  1655. return err;
  1656. }