fw.h 6.6 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
  4. * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #ifndef MLX4_FW_H
  35. #define MLX4_FW_H
  36. #include "mlx4.h"
  37. #include "icm.h"
  38. struct mlx4_mod_stat_cfg {
  39. u8 log_pg_sz;
  40. u8 log_pg_sz_m;
  41. };
  42. struct mlx4_port_cap {
  43. u8 link_state;
  44. u8 supported_port_types;
  45. u8 suggested_type;
  46. u8 default_sense;
  47. u8 log_max_macs;
  48. u8 log_max_vlans;
  49. int ib_mtu;
  50. int max_port_width;
  51. int max_vl;
  52. int max_tc_eth;
  53. int max_gids;
  54. int max_pkeys;
  55. u64 def_mac;
  56. u16 eth_mtu;
  57. int trans_type;
  58. int vendor_oui;
  59. u16 wavelength;
  60. u64 trans_code;
  61. u8 dmfs_optimized_state;
  62. };
  63. struct mlx4_dev_cap {
  64. int max_srq_sz;
  65. int max_qp_sz;
  66. int reserved_qps;
  67. int max_qps;
  68. int reserved_srqs;
  69. int max_srqs;
  70. int max_cq_sz;
  71. int reserved_cqs;
  72. int max_cqs;
  73. int max_mpts;
  74. int reserved_eqs;
  75. int max_eqs;
  76. int num_sys_eqs;
  77. int reserved_mtts;
  78. int reserved_mrws;
  79. int max_requester_per_qp;
  80. int max_responder_per_qp;
  81. int max_rdma_global;
  82. int local_ca_ack_delay;
  83. int num_ports;
  84. u32 max_msg_sz;
  85. u16 stat_rate_support;
  86. int fs_log_max_ucast_qp_range_size;
  87. int fs_max_num_qp_per_entry;
  88. u64 flags;
  89. u64 flags2;
  90. int reserved_uars;
  91. int uar_size;
  92. int min_page_sz;
  93. int bf_reg_size;
  94. int bf_regs_per_page;
  95. int max_sq_sg;
  96. int max_sq_desc_sz;
  97. int max_rq_sg;
  98. int max_rq_desc_sz;
  99. int max_qp_per_mcg;
  100. int reserved_mgms;
  101. int max_mcgs;
  102. int reserved_pds;
  103. int max_pds;
  104. int reserved_xrcds;
  105. int max_xrcds;
  106. int qpc_entry_sz;
  107. int rdmarc_entry_sz;
  108. int altc_entry_sz;
  109. int aux_entry_sz;
  110. int srq_entry_sz;
  111. int cqc_entry_sz;
  112. int eqc_entry_sz;
  113. int dmpt_entry_sz;
  114. int cmpt_entry_sz;
  115. int mtt_entry_sz;
  116. int resize_srq;
  117. u32 bmme_flags;
  118. u32 reserved_lkey;
  119. u64 max_icm_sz;
  120. int max_gso_sz;
  121. int max_rss_tbl_sz;
  122. u32 max_counters;
  123. u32 dmfs_high_rate_qpn_base;
  124. u32 dmfs_high_rate_qpn_range;
  125. struct mlx4_rate_limit_caps rl_caps;
  126. struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1];
  127. };
  128. struct mlx4_func_cap {
  129. u8 num_ports;
  130. u8 flags;
  131. u32 pf_context_behaviour;
  132. int qp_quota;
  133. int cq_quota;
  134. int srq_quota;
  135. int mpt_quota;
  136. int mtt_quota;
  137. int max_eq;
  138. int reserved_eq;
  139. int mcg_quota;
  140. u32 qp0_qkey;
  141. u32 qp0_tunnel_qpn;
  142. u32 qp0_proxy_qpn;
  143. u32 qp1_tunnel_qpn;
  144. u32 qp1_proxy_qpn;
  145. u32 reserved_lkey;
  146. u8 physical_port;
  147. u8 flags0;
  148. u8 flags1;
  149. u64 phys_port_id;
  150. u32 extra_flags;
  151. };
  152. struct mlx4_func {
  153. int bus;
  154. int device;
  155. int function;
  156. int physical_function;
  157. int rsvd_eqs;
  158. int max_eq;
  159. int rsvd_uars;
  160. };
  161. struct mlx4_adapter {
  162. char board_id[MLX4_BOARD_ID_LEN];
  163. u8 inta_pin;
  164. };
  165. struct mlx4_init_hca_param {
  166. u64 qpc_base;
  167. u64 rdmarc_base;
  168. u64 auxc_base;
  169. u64 altc_base;
  170. u64 srqc_base;
  171. u64 cqc_base;
  172. u64 eqc_base;
  173. u64 mc_base;
  174. u64 dmpt_base;
  175. u64 cmpt_base;
  176. u64 mtt_base;
  177. u64 global_caps;
  178. u16 log_mc_entry_sz;
  179. u16 log_mc_hash_sz;
  180. u16 hca_core_clock; /* Internal Clock Frequency (in MHz) */
  181. u8 log_num_qps;
  182. u8 log_num_srqs;
  183. u8 log_num_cqs;
  184. u8 log_num_eqs;
  185. u16 num_sys_eqs;
  186. u8 log_rd_per_qp;
  187. u8 log_mc_table_sz;
  188. u8 log_mpt_sz;
  189. u8 log_uar_sz;
  190. u8 mw_enabled; /* Enable memory windows */
  191. u8 uar_page_sz; /* log pg sz in 4k chunks */
  192. u8 steering_mode; /* for QUERY_HCA */
  193. u8 dmfs_high_steer_mode; /* for QUERY_HCA */
  194. u64 dev_cap_enabled;
  195. u16 cqe_size; /* For use only when CQE stride feature enabled */
  196. u16 eqe_size; /* For use only when EQE stride feature enabled */
  197. u8 rss_ip_frags;
  198. u8 phv_check_en; /* for QUERY_HCA */
  199. };
  200. struct mlx4_init_ib_param {
  201. int port_width;
  202. int vl_cap;
  203. int mtu_cap;
  204. u16 gid_cap;
  205. u16 pkey_cap;
  206. int set_guid0;
  207. u64 guid0;
  208. int set_node_guid;
  209. u64 node_guid;
  210. int set_si_guid;
  211. u64 si_guid;
  212. };
  213. struct mlx4_set_ib_param {
  214. int set_si_guid;
  215. int reset_qkey_viol;
  216. u64 si_guid;
  217. u32 cap_mask;
  218. };
  219. void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
  220. int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
  221. int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap);
  222. int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
  223. struct mlx4_func_cap *func_cap);
  224. int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
  225. struct mlx4_vhcr *vhcr,
  226. struct mlx4_cmd_mailbox *inbox,
  227. struct mlx4_cmd_mailbox *outbox,
  228. struct mlx4_cmd_info *cmd);
  229. int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave);
  230. int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm);
  231. int mlx4_UNMAP_FA(struct mlx4_dev *dev);
  232. int mlx4_RUN_FW(struct mlx4_dev *dev);
  233. int mlx4_QUERY_FW(struct mlx4_dev *dev);
  234. int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter);
  235. int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
  236. int mlx4_QUERY_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
  237. int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic);
  238. int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt);
  239. int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages);
  240. int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm);
  241. int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev);
  242. int mlx4_NOP(struct mlx4_dev *dev);
  243. int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg);
  244. void mlx4_opreq_action(struct work_struct *work);
  245. #endif /* MLX4_FW_H */