en_port.c 14 KB

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  1. /*
  2. * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/if_vlan.h>
  34. #include <linux/mlx4/device.h>
  35. #include <linux/mlx4/cmd.h>
  36. #include "en_port.h"
  37. #include "mlx4_en.h"
  38. int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv)
  39. {
  40. struct mlx4_cmd_mailbox *mailbox;
  41. struct mlx4_set_vlan_fltr_mbox *filter;
  42. int i;
  43. int j;
  44. int index = 0;
  45. u32 entry;
  46. int err = 0;
  47. mailbox = mlx4_alloc_cmd_mailbox(dev);
  48. if (IS_ERR(mailbox))
  49. return PTR_ERR(mailbox);
  50. filter = mailbox->buf;
  51. for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
  52. entry = 0;
  53. for (j = 0; j < 32; j++)
  54. if (test_bit(index++, priv->active_vlans))
  55. entry |= 1 << j;
  56. filter->entry[i] = cpu_to_be32(entry);
  57. }
  58. err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
  59. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
  60. mlx4_free_cmd_mailbox(dev, mailbox);
  61. return err;
  62. }
  63. int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
  64. {
  65. struct mlx4_en_query_port_context *qport_context;
  66. struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
  67. struct mlx4_en_port_state *state = &priv->port_state;
  68. struct mlx4_cmd_mailbox *mailbox;
  69. int err;
  70. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  71. if (IS_ERR(mailbox))
  72. return PTR_ERR(mailbox);
  73. err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
  74. MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
  75. MLX4_CMD_WRAPPED);
  76. if (err)
  77. goto out;
  78. qport_context = mailbox->buf;
  79. /* This command is always accessed from Ethtool context
  80. * already synchronized, no need in locking */
  81. state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
  82. switch (qport_context->link_speed & MLX4_EN_SPEED_MASK) {
  83. case MLX4_EN_100M_SPEED:
  84. state->link_speed = SPEED_100;
  85. break;
  86. case MLX4_EN_1G_SPEED:
  87. state->link_speed = SPEED_1000;
  88. break;
  89. case MLX4_EN_10G_SPEED_XAUI:
  90. case MLX4_EN_10G_SPEED_XFI:
  91. state->link_speed = SPEED_10000;
  92. break;
  93. case MLX4_EN_20G_SPEED:
  94. state->link_speed = SPEED_20000;
  95. break;
  96. case MLX4_EN_40G_SPEED:
  97. state->link_speed = SPEED_40000;
  98. break;
  99. case MLX4_EN_56G_SPEED:
  100. state->link_speed = SPEED_56000;
  101. break;
  102. default:
  103. state->link_speed = -1;
  104. break;
  105. }
  106. state->transceiver = qport_context->transceiver;
  107. state->flags = 0; /* Reset and recalculate the port flags */
  108. state->flags |= (qport_context->link_up & MLX4_EN_ANC_MASK) ?
  109. MLX4_EN_PORT_ANC : 0;
  110. state->flags |= (qport_context->autoneg & MLX4_EN_AUTONEG_MASK) ?
  111. MLX4_EN_PORT_ANE : 0;
  112. out:
  113. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  114. return err;
  115. }
  116. /* Each counter set is located in struct mlx4_en_stat_out_mbox
  117. * with a const offset between its prio components.
  118. * This function runs over a counter set and sum all of it's prio components.
  119. */
  120. static unsigned long en_stats_adder(__be64 *start, __be64 *next, int num)
  121. {
  122. __be64 *curr = start;
  123. unsigned long ret = 0;
  124. int i;
  125. int offset = next - start;
  126. for (i = 0; i < num; i++) {
  127. ret += be64_to_cpu(*curr);
  128. curr += offset;
  129. }
  130. return ret;
  131. }
  132. int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
  133. {
  134. struct mlx4_counter tmp_counter_stats;
  135. struct mlx4_en_stat_out_mbox *mlx4_en_stats;
  136. struct mlx4_en_stat_out_flow_control_mbox *flowstats;
  137. struct net_device *dev = mdev->pndev[port];
  138. struct mlx4_en_priv *priv = netdev_priv(dev);
  139. struct net_device_stats *stats = &dev->stats;
  140. struct mlx4_cmd_mailbox *mailbox;
  141. u64 in_mod = reset << 8 | port;
  142. int err;
  143. int i, counter_index;
  144. unsigned long sw_rx_dropped = 0;
  145. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  146. if (IS_ERR(mailbox))
  147. return PTR_ERR(mailbox);
  148. err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
  149. MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
  150. MLX4_CMD_NATIVE);
  151. if (err)
  152. goto out;
  153. mlx4_en_stats = mailbox->buf;
  154. spin_lock_bh(&priv->stats_lock);
  155. stats->rx_packets = 0;
  156. stats->rx_bytes = 0;
  157. priv->port_stats.rx_chksum_good = 0;
  158. priv->port_stats.rx_chksum_none = 0;
  159. priv->port_stats.rx_chksum_complete = 0;
  160. for (i = 0; i < priv->rx_ring_num; i++) {
  161. stats->rx_packets += priv->rx_ring[i]->packets;
  162. stats->rx_bytes += priv->rx_ring[i]->bytes;
  163. sw_rx_dropped += priv->rx_ring[i]->dropped;
  164. priv->port_stats.rx_chksum_good += priv->rx_ring[i]->csum_ok;
  165. priv->port_stats.rx_chksum_none += priv->rx_ring[i]->csum_none;
  166. priv->port_stats.rx_chksum_complete += priv->rx_ring[i]->csum_complete;
  167. }
  168. stats->tx_packets = 0;
  169. stats->tx_bytes = 0;
  170. stats->tx_dropped = 0;
  171. priv->port_stats.tx_chksum_offload = 0;
  172. priv->port_stats.queue_stopped = 0;
  173. priv->port_stats.wake_queue = 0;
  174. priv->port_stats.tso_packets = 0;
  175. priv->port_stats.xmit_more = 0;
  176. for (i = 0; i < priv->tx_ring_num; i++) {
  177. const struct mlx4_en_tx_ring *ring = priv->tx_ring[i];
  178. stats->tx_packets += ring->packets;
  179. stats->tx_bytes += ring->bytes;
  180. stats->tx_dropped += ring->tx_dropped;
  181. priv->port_stats.tx_chksum_offload += ring->tx_csum;
  182. priv->port_stats.queue_stopped += ring->queue_stopped;
  183. priv->port_stats.wake_queue += ring->wake_queue;
  184. priv->port_stats.tso_packets += ring->tso_packets;
  185. priv->port_stats.xmit_more += ring->xmit_more;
  186. }
  187. if (mlx4_is_master(mdev->dev)) {
  188. stats->rx_packets = en_stats_adder(&mlx4_en_stats->RTOT_prio_0,
  189. &mlx4_en_stats->RTOT_prio_1,
  190. NUM_PRIORITIES);
  191. stats->tx_packets = en_stats_adder(&mlx4_en_stats->TTOT_prio_0,
  192. &mlx4_en_stats->TTOT_prio_1,
  193. NUM_PRIORITIES);
  194. stats->rx_bytes = en_stats_adder(&mlx4_en_stats->ROCT_prio_0,
  195. &mlx4_en_stats->ROCT_prio_1,
  196. NUM_PRIORITIES);
  197. stats->tx_bytes = en_stats_adder(&mlx4_en_stats->TOCT_prio_0,
  198. &mlx4_en_stats->TOCT_prio_1,
  199. NUM_PRIORITIES);
  200. }
  201. /* net device stats */
  202. stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
  203. be32_to_cpu(mlx4_en_stats->RJBBR) +
  204. be32_to_cpu(mlx4_en_stats->RCRC) +
  205. be32_to_cpu(mlx4_en_stats->RRUNT) +
  206. be64_to_cpu(mlx4_en_stats->RInRangeLengthErr) +
  207. be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr) +
  208. be32_to_cpu(mlx4_en_stats->RSHORT) +
  209. en_stats_adder(&mlx4_en_stats->RGIANT_prio_0,
  210. &mlx4_en_stats->RGIANT_prio_1,
  211. NUM_PRIORITIES);
  212. stats->tx_errors = en_stats_adder(&mlx4_en_stats->TGIANT_prio_0,
  213. &mlx4_en_stats->TGIANT_prio_1,
  214. NUM_PRIORITIES);
  215. stats->multicast = en_stats_adder(&mlx4_en_stats->MCAST_prio_0,
  216. &mlx4_en_stats->MCAST_prio_1,
  217. NUM_PRIORITIES);
  218. stats->rx_dropped = be32_to_cpu(mlx4_en_stats->RDROP) +
  219. sw_rx_dropped;
  220. stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
  221. stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
  222. stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
  223. stats->tx_dropped += be32_to_cpu(mlx4_en_stats->TDROP);
  224. /* RX stats */
  225. priv->pkstats.rx_multicast_packets = stats->multicast;
  226. priv->pkstats.rx_broadcast_packets =
  227. en_stats_adder(&mlx4_en_stats->RBCAST_prio_0,
  228. &mlx4_en_stats->RBCAST_prio_1,
  229. NUM_PRIORITIES);
  230. priv->pkstats.rx_jabbers = be32_to_cpu(mlx4_en_stats->RJBBR);
  231. priv->pkstats.rx_in_range_length_error =
  232. be64_to_cpu(mlx4_en_stats->RInRangeLengthErr);
  233. priv->pkstats.rx_out_range_length_error =
  234. be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr);
  235. /* Tx stats */
  236. priv->pkstats.tx_multicast_packets =
  237. en_stats_adder(&mlx4_en_stats->TMCAST_prio_0,
  238. &mlx4_en_stats->TMCAST_prio_1,
  239. NUM_PRIORITIES);
  240. priv->pkstats.tx_broadcast_packets =
  241. en_stats_adder(&mlx4_en_stats->TBCAST_prio_0,
  242. &mlx4_en_stats->TBCAST_prio_1,
  243. NUM_PRIORITIES);
  244. priv->pkstats.rx_prio[0][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
  245. priv->pkstats.rx_prio[0][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_0);
  246. priv->pkstats.rx_prio[1][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
  247. priv->pkstats.rx_prio[1][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_1);
  248. priv->pkstats.rx_prio[2][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
  249. priv->pkstats.rx_prio[2][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_2);
  250. priv->pkstats.rx_prio[3][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
  251. priv->pkstats.rx_prio[3][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_3);
  252. priv->pkstats.rx_prio[4][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
  253. priv->pkstats.rx_prio[4][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_4);
  254. priv->pkstats.rx_prio[5][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
  255. priv->pkstats.rx_prio[5][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_5);
  256. priv->pkstats.rx_prio[6][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
  257. priv->pkstats.rx_prio[6][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_6);
  258. priv->pkstats.rx_prio[7][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
  259. priv->pkstats.rx_prio[7][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_7);
  260. priv->pkstats.rx_prio[8][0] = be64_to_cpu(mlx4_en_stats->RTOT_novlan);
  261. priv->pkstats.rx_prio[8][1] = be64_to_cpu(mlx4_en_stats->ROCT_novlan);
  262. priv->pkstats.tx_prio[0][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
  263. priv->pkstats.tx_prio[0][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_0);
  264. priv->pkstats.tx_prio[1][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
  265. priv->pkstats.tx_prio[1][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_1);
  266. priv->pkstats.tx_prio[2][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
  267. priv->pkstats.tx_prio[2][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_2);
  268. priv->pkstats.tx_prio[3][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
  269. priv->pkstats.tx_prio[3][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_3);
  270. priv->pkstats.tx_prio[4][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
  271. priv->pkstats.tx_prio[4][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_4);
  272. priv->pkstats.tx_prio[5][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
  273. priv->pkstats.tx_prio[5][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_5);
  274. priv->pkstats.tx_prio[6][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
  275. priv->pkstats.tx_prio[6][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_6);
  276. priv->pkstats.tx_prio[7][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
  277. priv->pkstats.tx_prio[7][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_7);
  278. priv->pkstats.tx_prio[8][0] = be64_to_cpu(mlx4_en_stats->TTOT_novlan);
  279. priv->pkstats.tx_prio[8][1] = be64_to_cpu(mlx4_en_stats->TOCT_novlan);
  280. spin_unlock_bh(&priv->stats_lock);
  281. memset(&tmp_counter_stats, 0, sizeof(tmp_counter_stats));
  282. counter_index = mlx4_get_default_counter_index(mdev->dev, port);
  283. err = mlx4_get_counter_stats(mdev->dev, counter_index,
  284. &tmp_counter_stats, reset);
  285. /* 0xffs indicates invalid value */
  286. memset(mailbox->buf, 0xff, sizeof(*flowstats) * MLX4_NUM_PRIORITIES);
  287. if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN) {
  288. memset(mailbox->buf, 0,
  289. sizeof(*flowstats) * MLX4_NUM_PRIORITIES);
  290. err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma,
  291. in_mod | MLX4_DUMP_ETH_STATS_FLOW_CONTROL,
  292. 0, MLX4_CMD_DUMP_ETH_STATS,
  293. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
  294. if (err)
  295. goto out;
  296. }
  297. flowstats = mailbox->buf;
  298. spin_lock_bh(&priv->stats_lock);
  299. if (tmp_counter_stats.counter_mode == 0) {
  300. priv->pf_stats.rx_bytes = be64_to_cpu(tmp_counter_stats.rx_bytes);
  301. priv->pf_stats.tx_bytes = be64_to_cpu(tmp_counter_stats.tx_bytes);
  302. priv->pf_stats.rx_packets = be64_to_cpu(tmp_counter_stats.rx_frames);
  303. priv->pf_stats.tx_packets = be64_to_cpu(tmp_counter_stats.tx_frames);
  304. }
  305. for (i = 0; i < MLX4_NUM_PRIORITIES; i++) {
  306. priv->rx_priority_flowstats[i].rx_pause =
  307. be64_to_cpu(flowstats[i].rx_pause);
  308. priv->rx_priority_flowstats[i].rx_pause_duration =
  309. be64_to_cpu(flowstats[i].rx_pause_duration);
  310. priv->rx_priority_flowstats[i].rx_pause_transition =
  311. be64_to_cpu(flowstats[i].rx_pause_transition);
  312. priv->tx_priority_flowstats[i].tx_pause =
  313. be64_to_cpu(flowstats[i].tx_pause);
  314. priv->tx_priority_flowstats[i].tx_pause_duration =
  315. be64_to_cpu(flowstats[i].tx_pause_duration);
  316. priv->tx_priority_flowstats[i].tx_pause_transition =
  317. be64_to_cpu(flowstats[i].tx_pause_transition);
  318. }
  319. /* if pfc is not in use, all priorities counters have the same value */
  320. priv->rx_flowstats.rx_pause =
  321. be64_to_cpu(flowstats[0].rx_pause);
  322. priv->rx_flowstats.rx_pause_duration =
  323. be64_to_cpu(flowstats[0].rx_pause_duration);
  324. priv->rx_flowstats.rx_pause_transition =
  325. be64_to_cpu(flowstats[0].rx_pause_transition);
  326. priv->tx_flowstats.tx_pause =
  327. be64_to_cpu(flowstats[0].tx_pause);
  328. priv->tx_flowstats.tx_pause_duration =
  329. be64_to_cpu(flowstats[0].tx_pause_duration);
  330. priv->tx_flowstats.tx_pause_transition =
  331. be64_to_cpu(flowstats[0].tx_pause_transition);
  332. spin_unlock_bh(&priv->stats_lock);
  333. out:
  334. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  335. return err;
  336. }