en_ethtool.c 58 KB

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  1. /*
  2. * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/kernel.h>
  34. #include <linux/ethtool.h>
  35. #include <linux/netdevice.h>
  36. #include <linux/mlx4/driver.h>
  37. #include <linux/mlx4/device.h>
  38. #include <linux/in.h>
  39. #include <net/ip.h>
  40. #include <linux/bitmap.h>
  41. #include "mlx4_en.h"
  42. #include "en_port.h"
  43. #define EN_ETHTOOL_QP_ATTACH (1ull << 63)
  44. #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
  45. #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
  46. static int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
  47. {
  48. int i;
  49. int err = 0;
  50. for (i = 0; i < priv->tx_ring_num; i++) {
  51. priv->tx_cq[i]->moder_cnt = priv->tx_frames;
  52. priv->tx_cq[i]->moder_time = priv->tx_usecs;
  53. if (priv->port_up) {
  54. err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]);
  55. if (err)
  56. return err;
  57. }
  58. }
  59. if (priv->adaptive_rx_coal)
  60. return 0;
  61. for (i = 0; i < priv->rx_ring_num; i++) {
  62. priv->rx_cq[i]->moder_cnt = priv->rx_frames;
  63. priv->rx_cq[i]->moder_time = priv->rx_usecs;
  64. priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
  65. if (priv->port_up) {
  66. err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
  67. if (err)
  68. return err;
  69. }
  70. }
  71. return err;
  72. }
  73. static void
  74. mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
  75. {
  76. struct mlx4_en_priv *priv = netdev_priv(dev);
  77. struct mlx4_en_dev *mdev = priv->mdev;
  78. strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
  79. strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")",
  80. sizeof(drvinfo->version));
  81. snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
  82. "%d.%d.%d",
  83. (u16) (mdev->dev->caps.fw_ver >> 32),
  84. (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
  85. (u16) (mdev->dev->caps.fw_ver & 0xffff));
  86. strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev),
  87. sizeof(drvinfo->bus_info));
  88. }
  89. static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
  90. "blueflame",
  91. "phv-bit"
  92. };
  93. static const char main_strings[][ETH_GSTRING_LEN] = {
  94. /* main statistics */
  95. "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
  96. "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
  97. "rx_length_errors", "rx_over_errors", "rx_crc_errors",
  98. "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
  99. "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
  100. "tx_heartbeat_errors", "tx_window_errors",
  101. /* port statistics */
  102. "tso_packets",
  103. "xmit_more",
  104. "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed",
  105. "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload",
  106. /* pf statistics */
  107. "pf_rx_packets",
  108. "pf_rx_bytes",
  109. "pf_tx_packets",
  110. "pf_tx_bytes",
  111. /* priority flow control statistics rx */
  112. "rx_pause_prio_0", "rx_pause_duration_prio_0",
  113. "rx_pause_transition_prio_0",
  114. "rx_pause_prio_1", "rx_pause_duration_prio_1",
  115. "rx_pause_transition_prio_1",
  116. "rx_pause_prio_2", "rx_pause_duration_prio_2",
  117. "rx_pause_transition_prio_2",
  118. "rx_pause_prio_3", "rx_pause_duration_prio_3",
  119. "rx_pause_transition_prio_3",
  120. "rx_pause_prio_4", "rx_pause_duration_prio_4",
  121. "rx_pause_transition_prio_4",
  122. "rx_pause_prio_5", "rx_pause_duration_prio_5",
  123. "rx_pause_transition_prio_5",
  124. "rx_pause_prio_6", "rx_pause_duration_prio_6",
  125. "rx_pause_transition_prio_6",
  126. "rx_pause_prio_7", "rx_pause_duration_prio_7",
  127. "rx_pause_transition_prio_7",
  128. /* flow control statistics rx */
  129. "rx_pause", "rx_pause_duration", "rx_pause_transition",
  130. /* priority flow control statistics tx */
  131. "tx_pause_prio_0", "tx_pause_duration_prio_0",
  132. "tx_pause_transition_prio_0",
  133. "tx_pause_prio_1", "tx_pause_duration_prio_1",
  134. "tx_pause_transition_prio_1",
  135. "tx_pause_prio_2", "tx_pause_duration_prio_2",
  136. "tx_pause_transition_prio_2",
  137. "tx_pause_prio_3", "tx_pause_duration_prio_3",
  138. "tx_pause_transition_prio_3",
  139. "tx_pause_prio_4", "tx_pause_duration_prio_4",
  140. "tx_pause_transition_prio_4",
  141. "tx_pause_prio_5", "tx_pause_duration_prio_5",
  142. "tx_pause_transition_prio_5",
  143. "tx_pause_prio_6", "tx_pause_duration_prio_6",
  144. "tx_pause_transition_prio_6",
  145. "tx_pause_prio_7", "tx_pause_duration_prio_7",
  146. "tx_pause_transition_prio_7",
  147. /* flow control statistics tx */
  148. "tx_pause", "tx_pause_duration", "tx_pause_transition",
  149. /* packet statistics */
  150. "rx_multicast_packets",
  151. "rx_broadcast_packets",
  152. "rx_jabbers",
  153. "rx_in_range_length_error",
  154. "rx_out_range_length_error",
  155. "tx_multicast_packets",
  156. "tx_broadcast_packets",
  157. "rx_prio_0_packets", "rx_prio_0_bytes",
  158. "rx_prio_1_packets", "rx_prio_1_bytes",
  159. "rx_prio_2_packets", "rx_prio_2_bytes",
  160. "rx_prio_3_packets", "rx_prio_3_bytes",
  161. "rx_prio_4_packets", "rx_prio_4_bytes",
  162. "rx_prio_5_packets", "rx_prio_5_bytes",
  163. "rx_prio_6_packets", "rx_prio_6_bytes",
  164. "rx_prio_7_packets", "rx_prio_7_bytes",
  165. "rx_novlan_packets", "rx_novlan_bytes",
  166. "tx_prio_0_packets", "tx_prio_0_bytes",
  167. "tx_prio_1_packets", "tx_prio_1_bytes",
  168. "tx_prio_2_packets", "tx_prio_2_bytes",
  169. "tx_prio_3_packets", "tx_prio_3_bytes",
  170. "tx_prio_4_packets", "tx_prio_4_bytes",
  171. "tx_prio_5_packets", "tx_prio_5_bytes",
  172. "tx_prio_6_packets", "tx_prio_6_bytes",
  173. "tx_prio_7_packets", "tx_prio_7_bytes",
  174. "tx_novlan_packets", "tx_novlan_bytes",
  175. };
  176. static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
  177. "Interrupt Test",
  178. "Link Test",
  179. "Speed Test",
  180. "Register Test",
  181. "Loopback Test",
  182. };
  183. static u32 mlx4_en_get_msglevel(struct net_device *dev)
  184. {
  185. return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
  186. }
  187. static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
  188. {
  189. ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
  190. }
  191. static void mlx4_en_get_wol(struct net_device *netdev,
  192. struct ethtool_wolinfo *wol)
  193. {
  194. struct mlx4_en_priv *priv = netdev_priv(netdev);
  195. int err = 0;
  196. u64 config = 0;
  197. u64 mask;
  198. if ((priv->port < 1) || (priv->port > 2)) {
  199. en_err(priv, "Failed to get WoL information\n");
  200. return;
  201. }
  202. mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
  203. MLX4_DEV_CAP_FLAG_WOL_PORT2;
  204. if (!(priv->mdev->dev->caps.flags & mask)) {
  205. wol->supported = 0;
  206. wol->wolopts = 0;
  207. return;
  208. }
  209. err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
  210. if (err) {
  211. en_err(priv, "Failed to get WoL information\n");
  212. return;
  213. }
  214. if (config & MLX4_EN_WOL_MAGIC)
  215. wol->supported = WAKE_MAGIC;
  216. else
  217. wol->supported = 0;
  218. if (config & MLX4_EN_WOL_ENABLED)
  219. wol->wolopts = WAKE_MAGIC;
  220. else
  221. wol->wolopts = 0;
  222. }
  223. static int mlx4_en_set_wol(struct net_device *netdev,
  224. struct ethtool_wolinfo *wol)
  225. {
  226. struct mlx4_en_priv *priv = netdev_priv(netdev);
  227. u64 config = 0;
  228. int err = 0;
  229. u64 mask;
  230. if ((priv->port < 1) || (priv->port > 2))
  231. return -EOPNOTSUPP;
  232. mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
  233. MLX4_DEV_CAP_FLAG_WOL_PORT2;
  234. if (!(priv->mdev->dev->caps.flags & mask))
  235. return -EOPNOTSUPP;
  236. if (wol->supported & ~WAKE_MAGIC)
  237. return -EINVAL;
  238. err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
  239. if (err) {
  240. en_err(priv, "Failed to get WoL info, unable to modify\n");
  241. return err;
  242. }
  243. if (wol->wolopts & WAKE_MAGIC) {
  244. config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
  245. MLX4_EN_WOL_MAGIC;
  246. } else {
  247. config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
  248. config |= MLX4_EN_WOL_DO_MODIFY;
  249. }
  250. err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
  251. if (err)
  252. en_err(priv, "Failed to set WoL information\n");
  253. return err;
  254. }
  255. struct bitmap_iterator {
  256. unsigned long *stats_bitmap;
  257. unsigned int count;
  258. unsigned int iterator;
  259. bool advance_array; /* if set, force no increments */
  260. };
  261. static inline void bitmap_iterator_init(struct bitmap_iterator *h,
  262. unsigned long *stats_bitmap,
  263. int count)
  264. {
  265. h->iterator = 0;
  266. h->advance_array = !bitmap_empty(stats_bitmap, count);
  267. h->count = h->advance_array ? bitmap_weight(stats_bitmap, count)
  268. : count;
  269. h->stats_bitmap = stats_bitmap;
  270. }
  271. static inline int bitmap_iterator_test(struct bitmap_iterator *h)
  272. {
  273. return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap);
  274. }
  275. static inline int bitmap_iterator_inc(struct bitmap_iterator *h)
  276. {
  277. return h->iterator++;
  278. }
  279. static inline unsigned int
  280. bitmap_iterator_count(struct bitmap_iterator *h)
  281. {
  282. return h->count;
  283. }
  284. static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
  285. {
  286. struct mlx4_en_priv *priv = netdev_priv(dev);
  287. struct bitmap_iterator it;
  288. bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
  289. switch (sset) {
  290. case ETH_SS_STATS:
  291. return bitmap_iterator_count(&it) +
  292. (priv->tx_ring_num * 2) +
  293. (priv->rx_ring_num * 3);
  294. case ETH_SS_TEST:
  295. return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
  296. & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
  297. case ETH_SS_PRIV_FLAGS:
  298. return ARRAY_SIZE(mlx4_en_priv_flags);
  299. default:
  300. return -EOPNOTSUPP;
  301. }
  302. }
  303. static void mlx4_en_get_ethtool_stats(struct net_device *dev,
  304. struct ethtool_stats *stats, uint64_t *data)
  305. {
  306. struct mlx4_en_priv *priv = netdev_priv(dev);
  307. int index = 0;
  308. int i;
  309. struct bitmap_iterator it;
  310. bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
  311. spin_lock_bh(&priv->stats_lock);
  312. for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it))
  313. if (bitmap_iterator_test(&it))
  314. data[index++] = ((unsigned long *)&dev->stats)[i];
  315. for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it))
  316. if (bitmap_iterator_test(&it))
  317. data[index++] = ((unsigned long *)&priv->port_stats)[i];
  318. for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it))
  319. if (bitmap_iterator_test(&it))
  320. data[index++] =
  321. ((unsigned long *)&priv->pf_stats)[i];
  322. for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX;
  323. i++, bitmap_iterator_inc(&it))
  324. if (bitmap_iterator_test(&it))
  325. data[index++] =
  326. ((u64 *)&priv->rx_priority_flowstats)[i];
  327. for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it))
  328. if (bitmap_iterator_test(&it))
  329. data[index++] = ((u64 *)&priv->rx_flowstats)[i];
  330. for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX;
  331. i++, bitmap_iterator_inc(&it))
  332. if (bitmap_iterator_test(&it))
  333. data[index++] =
  334. ((u64 *)&priv->tx_priority_flowstats)[i];
  335. for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it))
  336. if (bitmap_iterator_test(&it))
  337. data[index++] = ((u64 *)&priv->tx_flowstats)[i];
  338. for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it))
  339. if (bitmap_iterator_test(&it))
  340. data[index++] = ((unsigned long *)&priv->pkstats)[i];
  341. for (i = 0; i < priv->tx_ring_num; i++) {
  342. data[index++] = priv->tx_ring[i]->packets;
  343. data[index++] = priv->tx_ring[i]->bytes;
  344. }
  345. for (i = 0; i < priv->rx_ring_num; i++) {
  346. data[index++] = priv->rx_ring[i]->packets;
  347. data[index++] = priv->rx_ring[i]->bytes;
  348. data[index++] = priv->rx_ring[i]->dropped;
  349. }
  350. spin_unlock_bh(&priv->stats_lock);
  351. }
  352. static void mlx4_en_self_test(struct net_device *dev,
  353. struct ethtool_test *etest, u64 *buf)
  354. {
  355. mlx4_en_ex_selftest(dev, &etest->flags, buf);
  356. }
  357. static void mlx4_en_get_strings(struct net_device *dev,
  358. uint32_t stringset, uint8_t *data)
  359. {
  360. struct mlx4_en_priv *priv = netdev_priv(dev);
  361. int index = 0;
  362. int i, strings = 0;
  363. struct bitmap_iterator it;
  364. bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
  365. switch (stringset) {
  366. case ETH_SS_TEST:
  367. for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
  368. strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
  369. if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
  370. for (; i < MLX4_EN_NUM_SELF_TEST; i++)
  371. strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
  372. break;
  373. case ETH_SS_STATS:
  374. /* Add main counters */
  375. for (i = 0; i < NUM_MAIN_STATS; i++, strings++,
  376. bitmap_iterator_inc(&it))
  377. if (bitmap_iterator_test(&it))
  378. strcpy(data + (index++) * ETH_GSTRING_LEN,
  379. main_strings[strings]);
  380. for (i = 0; i < NUM_PORT_STATS; i++, strings++,
  381. bitmap_iterator_inc(&it))
  382. if (bitmap_iterator_test(&it))
  383. strcpy(data + (index++) * ETH_GSTRING_LEN,
  384. main_strings[strings]);
  385. for (i = 0; i < NUM_PF_STATS; i++, strings++,
  386. bitmap_iterator_inc(&it))
  387. if (bitmap_iterator_test(&it))
  388. strcpy(data + (index++) * ETH_GSTRING_LEN,
  389. main_strings[strings]);
  390. for (i = 0; i < NUM_FLOW_STATS; i++, strings++,
  391. bitmap_iterator_inc(&it))
  392. if (bitmap_iterator_test(&it))
  393. strcpy(data + (index++) * ETH_GSTRING_LEN,
  394. main_strings[strings]);
  395. for (i = 0; i < NUM_PKT_STATS; i++, strings++,
  396. bitmap_iterator_inc(&it))
  397. if (bitmap_iterator_test(&it))
  398. strcpy(data + (index++) * ETH_GSTRING_LEN,
  399. main_strings[strings]);
  400. for (i = 0; i < priv->tx_ring_num; i++) {
  401. sprintf(data + (index++) * ETH_GSTRING_LEN,
  402. "tx%d_packets", i);
  403. sprintf(data + (index++) * ETH_GSTRING_LEN,
  404. "tx%d_bytes", i);
  405. }
  406. for (i = 0; i < priv->rx_ring_num; i++) {
  407. sprintf(data + (index++) * ETH_GSTRING_LEN,
  408. "rx%d_packets", i);
  409. sprintf(data + (index++) * ETH_GSTRING_LEN,
  410. "rx%d_bytes", i);
  411. sprintf(data + (index++) * ETH_GSTRING_LEN,
  412. "rx%d_dropped", i);
  413. }
  414. break;
  415. case ETH_SS_PRIV_FLAGS:
  416. for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
  417. strcpy(data + i * ETH_GSTRING_LEN,
  418. mlx4_en_priv_flags[i]);
  419. break;
  420. }
  421. }
  422. static u32 mlx4_en_autoneg_get(struct net_device *dev)
  423. {
  424. struct mlx4_en_priv *priv = netdev_priv(dev);
  425. struct mlx4_en_dev *mdev = priv->mdev;
  426. u32 autoneg = AUTONEG_DISABLE;
  427. if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
  428. (priv->port_state.flags & MLX4_EN_PORT_ANE))
  429. autoneg = AUTONEG_ENABLE;
  430. return autoneg;
  431. }
  432. static void ptys2ethtool_update_supported_port(unsigned long *mask,
  433. struct mlx4_ptys_reg *ptys_reg)
  434. {
  435. u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
  436. if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
  437. | MLX4_PROT_MASK(MLX4_1000BASE_T)
  438. | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
  439. __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask);
  440. } else if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
  441. | MLX4_PROT_MASK(MLX4_10GBASE_SR)
  442. | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
  443. | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
  444. | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
  445. | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
  446. __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask);
  447. } else if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
  448. | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
  449. | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
  450. | MLX4_PROT_MASK(MLX4_10GBASE_KR)
  451. | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
  452. | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
  453. __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask);
  454. }
  455. }
  456. static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
  457. {
  458. u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
  459. if (!eth_proto) /* link down */
  460. eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
  461. if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
  462. | MLX4_PROT_MASK(MLX4_1000BASE_T)
  463. | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
  464. return PORT_TP;
  465. }
  466. if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
  467. | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
  468. | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
  469. | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
  470. return PORT_FIBRE;
  471. }
  472. if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
  473. | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
  474. | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
  475. return PORT_DA;
  476. }
  477. if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
  478. | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
  479. | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
  480. | MLX4_PROT_MASK(MLX4_10GBASE_KR)
  481. | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
  482. | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
  483. return PORT_NONE;
  484. }
  485. return PORT_OTHER;
  486. }
  487. #define MLX4_LINK_MODES_SZ \
  488. (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
  489. enum ethtool_report {
  490. SUPPORTED = 0,
  491. ADVERTISED = 1,
  492. };
  493. struct ptys2ethtool_config {
  494. __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
  495. __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
  496. u32 speed;
  497. };
  498. static unsigned long *ptys2ethtool_link_mode(struct ptys2ethtool_config *cfg,
  499. enum ethtool_report report)
  500. {
  501. switch (report) {
  502. case SUPPORTED:
  503. return cfg->supported;
  504. case ADVERTISED:
  505. return cfg->advertised;
  506. }
  507. return NULL;
  508. }
  509. #define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
  510. ({ \
  511. struct ptys2ethtool_config *cfg; \
  512. const unsigned int modes[] = { __VA_ARGS__ }; \
  513. unsigned int i; \
  514. cfg = &ptys2ethtool_map[reg_]; \
  515. cfg->speed = speed_; \
  516. bitmap_zero(cfg->supported, \
  517. __ETHTOOL_LINK_MODE_MASK_NBITS); \
  518. bitmap_zero(cfg->advertised, \
  519. __ETHTOOL_LINK_MODE_MASK_NBITS); \
  520. for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
  521. __set_bit(modes[i], cfg->supported); \
  522. __set_bit(modes[i], cfg->advertised); \
  523. } \
  524. })
  525. /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
  526. static struct ptys2ethtool_config ptys2ethtool_map[MLX4_LINK_MODES_SZ];
  527. void __init mlx4_en_init_ptys2ethtool_map(void)
  528. {
  529. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_100BASE_TX, SPEED_100,
  530. ETHTOOL_LINK_MODE_100baseT_Full_BIT);
  531. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_T, SPEED_1000,
  532. ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
  533. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_CX_SGMII, SPEED_1000,
  534. ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
  535. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_KX, SPEED_1000,
  536. ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
  537. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_T, SPEED_10000,
  538. ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
  539. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CX4, SPEED_10000,
  540. ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
  541. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KX4, SPEED_10000,
  542. ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
  543. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KR, SPEED_10000,
  544. ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
  545. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CR, SPEED_10000,
  546. ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
  547. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_SR, SPEED_10000,
  548. ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
  549. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_20GBASE_KR2, SPEED_20000,
  550. ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT,
  551. ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
  552. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_CR4, SPEED_40000,
  553. ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
  554. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_KR4, SPEED_40000,
  555. ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
  556. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_SR4, SPEED_40000,
  557. ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
  558. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_KR4, SPEED_56000,
  559. ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
  560. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_CR4, SPEED_56000,
  561. ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT);
  562. MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_SR4, SPEED_56000,
  563. ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT);
  564. };
  565. static void ptys2ethtool_update_link_modes(unsigned long *link_modes,
  566. u32 eth_proto,
  567. enum ethtool_report report)
  568. {
  569. int i;
  570. for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
  571. if (eth_proto & MLX4_PROT_MASK(i))
  572. bitmap_or(link_modes, link_modes,
  573. ptys2ethtool_link_mode(&ptys2ethtool_map[i],
  574. report),
  575. __ETHTOOL_LINK_MODE_MASK_NBITS);
  576. }
  577. }
  578. static u32 ethtool2ptys_link_modes(const unsigned long *link_modes,
  579. enum ethtool_report report)
  580. {
  581. int i;
  582. u32 ptys_modes = 0;
  583. for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
  584. if (bitmap_intersects(
  585. ptys2ethtool_link_mode(&ptys2ethtool_map[i],
  586. report),
  587. link_modes,
  588. __ETHTOOL_LINK_MODE_MASK_NBITS))
  589. ptys_modes |= 1 << i;
  590. }
  591. return ptys_modes;
  592. }
  593. /* Convert actual speed (SPEED_XXX) to ptys link modes */
  594. static u32 speed2ptys_link_modes(u32 speed)
  595. {
  596. int i;
  597. u32 ptys_modes = 0;
  598. for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
  599. if (ptys2ethtool_map[i].speed == speed)
  600. ptys_modes |= 1 << i;
  601. }
  602. return ptys_modes;
  603. }
  604. static int
  605. ethtool_get_ptys_link_ksettings(struct net_device *dev,
  606. struct ethtool_link_ksettings *link_ksettings)
  607. {
  608. struct mlx4_en_priv *priv = netdev_priv(dev);
  609. struct mlx4_ptys_reg ptys_reg;
  610. u32 eth_proto;
  611. int ret;
  612. memset(&ptys_reg, 0, sizeof(ptys_reg));
  613. ptys_reg.local_port = priv->port;
  614. ptys_reg.proto_mask = MLX4_PTYS_EN;
  615. ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
  616. MLX4_ACCESS_REG_QUERY, &ptys_reg);
  617. if (ret) {
  618. en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
  619. ret);
  620. return ret;
  621. }
  622. en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
  623. ptys_reg.proto_mask);
  624. en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
  625. be32_to_cpu(ptys_reg.eth_proto_cap));
  626. en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
  627. be32_to_cpu(ptys_reg.eth_proto_admin));
  628. en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
  629. be32_to_cpu(ptys_reg.eth_proto_oper));
  630. en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
  631. be32_to_cpu(ptys_reg.eth_proto_lp_adv));
  632. /* reset supported/advertising masks */
  633. ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
  634. ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
  635. ptys2ethtool_update_supported_port(link_ksettings->link_modes.supported,
  636. &ptys_reg);
  637. eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
  638. ptys2ethtool_update_link_modes(link_ksettings->link_modes.supported,
  639. eth_proto, SUPPORTED);
  640. eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
  641. ptys2ethtool_update_link_modes(link_ksettings->link_modes.advertising,
  642. eth_proto, ADVERTISED);
  643. ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
  644. Pause);
  645. ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
  646. Asym_Pause);
  647. if (priv->prof->tx_pause)
  648. ethtool_link_ksettings_add_link_mode(link_ksettings,
  649. advertising, Pause);
  650. if (priv->prof->tx_pause ^ priv->prof->rx_pause)
  651. ethtool_link_ksettings_add_link_mode(link_ksettings,
  652. advertising, Asym_Pause);
  653. link_ksettings->base.port = ptys_get_active_port(&ptys_reg);
  654. if (mlx4_en_autoneg_get(dev)) {
  655. ethtool_link_ksettings_add_link_mode(link_ksettings,
  656. supported, Autoneg);
  657. ethtool_link_ksettings_add_link_mode(link_ksettings,
  658. advertising, Autoneg);
  659. }
  660. link_ksettings->base.autoneg
  661. = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
  662. AUTONEG_ENABLE : AUTONEG_DISABLE;
  663. eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
  664. ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);
  665. ptys2ethtool_update_link_modes(
  666. link_ksettings->link_modes.lp_advertising,
  667. eth_proto, ADVERTISED);
  668. if (priv->port_state.flags & MLX4_EN_PORT_ANC)
  669. ethtool_link_ksettings_add_link_mode(link_ksettings,
  670. lp_advertising, Autoneg);
  671. link_ksettings->base.phy_address = 0;
  672. link_ksettings->base.mdio_support = 0;
  673. link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
  674. link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
  675. return ret;
  676. }
  677. static void
  678. ethtool_get_default_link_ksettings(
  679. struct net_device *dev, struct ethtool_link_ksettings *link_ksettings)
  680. {
  681. struct mlx4_en_priv *priv = netdev_priv(dev);
  682. int trans_type;
  683. link_ksettings->base.autoneg = AUTONEG_DISABLE;
  684. ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
  685. ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
  686. 10000baseT_Full);
  687. ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
  688. ethtool_link_ksettings_add_link_mode(link_ksettings, advertising,
  689. 10000baseT_Full);
  690. trans_type = priv->port_state.transceiver;
  691. if (trans_type > 0 && trans_type <= 0xC) {
  692. link_ksettings->base.port = PORT_FIBRE;
  693. ethtool_link_ksettings_add_link_mode(link_ksettings,
  694. supported, FIBRE);
  695. ethtool_link_ksettings_add_link_mode(link_ksettings,
  696. advertising, FIBRE);
  697. } else if (trans_type == 0x80 || trans_type == 0) {
  698. link_ksettings->base.port = PORT_TP;
  699. ethtool_link_ksettings_add_link_mode(link_ksettings,
  700. supported, TP);
  701. ethtool_link_ksettings_add_link_mode(link_ksettings,
  702. advertising, TP);
  703. } else {
  704. link_ksettings->base.port = -1;
  705. }
  706. }
  707. static int
  708. mlx4_en_get_link_ksettings(struct net_device *dev,
  709. struct ethtool_link_ksettings *link_ksettings)
  710. {
  711. struct mlx4_en_priv *priv = netdev_priv(dev);
  712. int ret = -EINVAL;
  713. if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
  714. return -ENOMEM;
  715. en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
  716. priv->port_state.flags & MLX4_EN_PORT_ANC,
  717. priv->port_state.flags & MLX4_EN_PORT_ANE);
  718. if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
  719. ret = ethtool_get_ptys_link_ksettings(dev, link_ksettings);
  720. if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
  721. ethtool_get_default_link_ksettings(dev, link_ksettings);
  722. if (netif_carrier_ok(dev)) {
  723. link_ksettings->base.speed = priv->port_state.link_speed;
  724. link_ksettings->base.duplex = DUPLEX_FULL;
  725. } else {
  726. link_ksettings->base.speed = SPEED_UNKNOWN;
  727. link_ksettings->base.duplex = DUPLEX_UNKNOWN;
  728. }
  729. return 0;
  730. }
  731. /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */
  732. static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed,
  733. __be32 proto_cap)
  734. {
  735. __be32 proto_admin = 0;
  736. if (!speed) { /* Speed = 0 ==> Reset Link modes */
  737. proto_admin = proto_cap;
  738. en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n",
  739. be32_to_cpu(proto_cap));
  740. } else {
  741. u32 ptys_link_modes = speed2ptys_link_modes(speed);
  742. proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap;
  743. en_info(priv, "Setting Speed to %d\n", speed);
  744. }
  745. return proto_admin;
  746. }
  747. static int
  748. mlx4_en_set_link_ksettings(struct net_device *dev,
  749. const struct ethtool_link_ksettings *link_ksettings)
  750. {
  751. struct mlx4_en_priv *priv = netdev_priv(dev);
  752. struct mlx4_ptys_reg ptys_reg;
  753. __be32 proto_admin;
  754. int ret;
  755. u32 ptys_adv = ethtool2ptys_link_modes(
  756. link_ksettings->link_modes.advertising, ADVERTISED);
  757. const int speed = link_ksettings->base.speed;
  758. en_dbg(DRV, priv,
  759. "Set Speed=%d adv={%*pbl} autoneg=%d duplex=%d\n",
  760. speed, __ETHTOOL_LINK_MODE_MASK_NBITS,
  761. link_ksettings->link_modes.advertising,
  762. link_ksettings->base.autoneg,
  763. link_ksettings->base.duplex);
  764. if (!(priv->mdev->dev->caps.flags2 &
  765. MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) ||
  766. (link_ksettings->base.duplex == DUPLEX_HALF))
  767. return -EINVAL;
  768. memset(&ptys_reg, 0, sizeof(ptys_reg));
  769. ptys_reg.local_port = priv->port;
  770. ptys_reg.proto_mask = MLX4_PTYS_EN;
  771. ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
  772. MLX4_ACCESS_REG_QUERY, &ptys_reg);
  773. if (ret) {
  774. en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n",
  775. ret);
  776. return 0;
  777. }
  778. proto_admin = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
  779. cpu_to_be32(ptys_adv) :
  780. speed_set_ptys_admin(priv, speed,
  781. ptys_reg.eth_proto_cap);
  782. proto_admin &= ptys_reg.eth_proto_cap;
  783. if (!proto_admin) {
  784. en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n");
  785. return -EINVAL; /* nothing to change due to bad input */
  786. }
  787. if (proto_admin == ptys_reg.eth_proto_admin)
  788. return 0; /* Nothing to change */
  789. en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n",
  790. be32_to_cpu(proto_admin));
  791. ptys_reg.eth_proto_admin = proto_admin;
  792. ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE,
  793. &ptys_reg);
  794. if (ret) {
  795. en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)",
  796. be32_to_cpu(ptys_reg.eth_proto_admin), ret);
  797. return ret;
  798. }
  799. mutex_lock(&priv->mdev->state_lock);
  800. if (priv->port_up) {
  801. en_warn(priv, "Port link mode changed, restarting port...\n");
  802. mlx4_en_stop_port(dev, 1);
  803. if (mlx4_en_start_port(dev))
  804. en_err(priv, "Failed restarting port %d\n", priv->port);
  805. }
  806. mutex_unlock(&priv->mdev->state_lock);
  807. return 0;
  808. }
  809. static int mlx4_en_get_coalesce(struct net_device *dev,
  810. struct ethtool_coalesce *coal)
  811. {
  812. struct mlx4_en_priv *priv = netdev_priv(dev);
  813. coal->tx_coalesce_usecs = priv->tx_usecs;
  814. coal->tx_max_coalesced_frames = priv->tx_frames;
  815. coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
  816. coal->rx_coalesce_usecs = priv->rx_usecs;
  817. coal->rx_max_coalesced_frames = priv->rx_frames;
  818. coal->pkt_rate_low = priv->pkt_rate_low;
  819. coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
  820. coal->pkt_rate_high = priv->pkt_rate_high;
  821. coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
  822. coal->rate_sample_interval = priv->sample_interval;
  823. coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
  824. return 0;
  825. }
  826. static int mlx4_en_set_coalesce(struct net_device *dev,
  827. struct ethtool_coalesce *coal)
  828. {
  829. struct mlx4_en_priv *priv = netdev_priv(dev);
  830. if (!coal->tx_max_coalesced_frames_irq)
  831. return -EINVAL;
  832. if (coal->tx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME ||
  833. coal->rx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME ||
  834. coal->rx_coalesce_usecs_low > MLX4_EN_MAX_COAL_TIME ||
  835. coal->rx_coalesce_usecs_high > MLX4_EN_MAX_COAL_TIME) {
  836. netdev_info(dev, "%s: maximum coalesce time supported is %d usecs\n",
  837. __func__, MLX4_EN_MAX_COAL_TIME);
  838. return -ERANGE;
  839. }
  840. if (coal->tx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS ||
  841. coal->rx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS) {
  842. netdev_info(dev, "%s: maximum coalesced frames supported is %d\n",
  843. __func__, MLX4_EN_MAX_COAL_PKTS);
  844. return -ERANGE;
  845. }
  846. priv->rx_frames = (coal->rx_max_coalesced_frames ==
  847. MLX4_EN_AUTO_CONF) ?
  848. MLX4_EN_RX_COAL_TARGET :
  849. coal->rx_max_coalesced_frames;
  850. priv->rx_usecs = (coal->rx_coalesce_usecs ==
  851. MLX4_EN_AUTO_CONF) ?
  852. MLX4_EN_RX_COAL_TIME :
  853. coal->rx_coalesce_usecs;
  854. /* Setting TX coalescing parameters */
  855. if (coal->tx_coalesce_usecs != priv->tx_usecs ||
  856. coal->tx_max_coalesced_frames != priv->tx_frames) {
  857. priv->tx_usecs = coal->tx_coalesce_usecs;
  858. priv->tx_frames = coal->tx_max_coalesced_frames;
  859. }
  860. /* Set adaptive coalescing params */
  861. priv->pkt_rate_low = coal->pkt_rate_low;
  862. priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
  863. priv->pkt_rate_high = coal->pkt_rate_high;
  864. priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
  865. priv->sample_interval = coal->rate_sample_interval;
  866. priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
  867. priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
  868. return mlx4_en_moderation_update(priv);
  869. }
  870. static int mlx4_en_set_pauseparam(struct net_device *dev,
  871. struct ethtool_pauseparam *pause)
  872. {
  873. struct mlx4_en_priv *priv = netdev_priv(dev);
  874. struct mlx4_en_dev *mdev = priv->mdev;
  875. u8 tx_pause, tx_ppp, rx_pause, rx_ppp;
  876. int err;
  877. if (pause->autoneg)
  878. return -EINVAL;
  879. tx_pause = !!(pause->tx_pause);
  880. rx_pause = !!(pause->rx_pause);
  881. rx_ppp = priv->prof->rx_ppp && !(tx_pause || rx_pause);
  882. tx_ppp = priv->prof->tx_ppp && !(tx_pause || rx_pause);
  883. err = mlx4_SET_PORT_general(mdev->dev, priv->port,
  884. priv->rx_skb_size + ETH_FCS_LEN,
  885. tx_pause, tx_ppp, rx_pause, rx_ppp);
  886. if (err) {
  887. en_err(priv, "Failed setting pause params, err = %d\n", err);
  888. return err;
  889. }
  890. mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap,
  891. rx_ppp, rx_pause, tx_ppp, tx_pause);
  892. priv->prof->tx_pause = tx_pause;
  893. priv->prof->rx_pause = rx_pause;
  894. priv->prof->tx_ppp = tx_ppp;
  895. priv->prof->rx_ppp = rx_ppp;
  896. return err;
  897. }
  898. static void mlx4_en_get_pauseparam(struct net_device *dev,
  899. struct ethtool_pauseparam *pause)
  900. {
  901. struct mlx4_en_priv *priv = netdev_priv(dev);
  902. pause->tx_pause = priv->prof->tx_pause;
  903. pause->rx_pause = priv->prof->rx_pause;
  904. }
  905. static int mlx4_en_set_ringparam(struct net_device *dev,
  906. struct ethtool_ringparam *param)
  907. {
  908. struct mlx4_en_priv *priv = netdev_priv(dev);
  909. struct mlx4_en_dev *mdev = priv->mdev;
  910. struct mlx4_en_port_profile new_prof;
  911. struct mlx4_en_priv *tmp;
  912. u32 rx_size, tx_size;
  913. int port_up = 0;
  914. int err = 0;
  915. if (param->rx_jumbo_pending || param->rx_mini_pending)
  916. return -EINVAL;
  917. rx_size = roundup_pow_of_two(param->rx_pending);
  918. rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE);
  919. rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE);
  920. tx_size = roundup_pow_of_two(param->tx_pending);
  921. tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE);
  922. tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE);
  923. if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
  924. priv->rx_ring[0]->size) &&
  925. tx_size == priv->tx_ring[0]->size)
  926. return 0;
  927. tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
  928. if (!tmp)
  929. return -ENOMEM;
  930. mutex_lock(&mdev->state_lock);
  931. memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
  932. new_prof.tx_ring_size = tx_size;
  933. new_prof.rx_ring_size = rx_size;
  934. err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof);
  935. if (err)
  936. goto out;
  937. if (priv->port_up) {
  938. port_up = 1;
  939. mlx4_en_stop_port(dev, 1);
  940. }
  941. mlx4_en_safe_replace_resources(priv, tmp);
  942. if (port_up) {
  943. err = mlx4_en_start_port(dev);
  944. if (err)
  945. en_err(priv, "Failed starting port\n");
  946. }
  947. err = mlx4_en_moderation_update(priv);
  948. out:
  949. kfree(tmp);
  950. mutex_unlock(&mdev->state_lock);
  951. return err;
  952. }
  953. static void mlx4_en_get_ringparam(struct net_device *dev,
  954. struct ethtool_ringparam *param)
  955. {
  956. struct mlx4_en_priv *priv = netdev_priv(dev);
  957. memset(param, 0, sizeof(*param));
  958. param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
  959. param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
  960. param->rx_pending = priv->port_up ?
  961. priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
  962. param->tx_pending = priv->tx_ring[0]->size;
  963. }
  964. static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
  965. {
  966. struct mlx4_en_priv *priv = netdev_priv(dev);
  967. return rounddown_pow_of_two(priv->rx_ring_num);
  968. }
  969. static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev)
  970. {
  971. return MLX4_EN_RSS_KEY_SIZE;
  972. }
  973. static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)
  974. {
  975. struct mlx4_en_priv *priv = netdev_priv(dev);
  976. /* check if requested function is supported by the device */
  977. if (hfunc == ETH_RSS_HASH_TOP) {
  978. if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP))
  979. return -EINVAL;
  980. if (!(dev->features & NETIF_F_RXHASH))
  981. en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n");
  982. return 0;
  983. } else if (hfunc == ETH_RSS_HASH_XOR) {
  984. if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR))
  985. return -EINVAL;
  986. if (dev->features & NETIF_F_RXHASH)
  987. en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n");
  988. return 0;
  989. }
  990. return -EINVAL;
  991. }
  992. static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,
  993. u8 *hfunc)
  994. {
  995. struct mlx4_en_priv *priv = netdev_priv(dev);
  996. u32 n = mlx4_en_get_rxfh_indir_size(dev);
  997. u32 i, rss_rings;
  998. int err = 0;
  999. rss_rings = priv->prof->rss_rings ?: n;
  1000. rss_rings = rounddown_pow_of_two(rss_rings);
  1001. for (i = 0; i < n; i++) {
  1002. if (!ring_index)
  1003. break;
  1004. ring_index[i] = i % rss_rings;
  1005. }
  1006. if (key)
  1007. memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE);
  1008. if (hfunc)
  1009. *hfunc = priv->rss_hash_fn;
  1010. return err;
  1011. }
  1012. static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
  1013. const u8 *key, const u8 hfunc)
  1014. {
  1015. struct mlx4_en_priv *priv = netdev_priv(dev);
  1016. u32 n = mlx4_en_get_rxfh_indir_size(dev);
  1017. struct mlx4_en_dev *mdev = priv->mdev;
  1018. int port_up = 0;
  1019. int err = 0;
  1020. int i;
  1021. int rss_rings = 0;
  1022. /* Calculate RSS table size and make sure flows are spread evenly
  1023. * between rings
  1024. */
  1025. for (i = 0; i < n; i++) {
  1026. if (!ring_index)
  1027. break;
  1028. if (i > 0 && !ring_index[i] && !rss_rings)
  1029. rss_rings = i;
  1030. if (ring_index[i] != (i % (rss_rings ?: n)))
  1031. return -EINVAL;
  1032. }
  1033. if (!rss_rings)
  1034. rss_rings = n;
  1035. /* RSS table size must be an order of 2 */
  1036. if (!is_power_of_2(rss_rings))
  1037. return -EINVAL;
  1038. if (hfunc != ETH_RSS_HASH_NO_CHANGE) {
  1039. err = mlx4_en_check_rxfh_func(dev, hfunc);
  1040. if (err)
  1041. return err;
  1042. }
  1043. mutex_lock(&mdev->state_lock);
  1044. if (priv->port_up) {
  1045. port_up = 1;
  1046. mlx4_en_stop_port(dev, 1);
  1047. }
  1048. if (ring_index)
  1049. priv->prof->rss_rings = rss_rings;
  1050. if (key)
  1051. memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE);
  1052. if (hfunc != ETH_RSS_HASH_NO_CHANGE)
  1053. priv->rss_hash_fn = hfunc;
  1054. if (port_up) {
  1055. err = mlx4_en_start_port(dev);
  1056. if (err)
  1057. en_err(priv, "Failed starting port\n");
  1058. }
  1059. mutex_unlock(&mdev->state_lock);
  1060. return err;
  1061. }
  1062. #define all_zeros_or_all_ones(field) \
  1063. ((field) == 0 || (field) == (__force typeof(field))-1)
  1064. static int mlx4_en_validate_flow(struct net_device *dev,
  1065. struct ethtool_rxnfc *cmd)
  1066. {
  1067. struct ethtool_usrip4_spec *l3_mask;
  1068. struct ethtool_tcpip4_spec *l4_mask;
  1069. struct ethhdr *eth_mask;
  1070. if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
  1071. return -EINVAL;
  1072. if (cmd->fs.flow_type & FLOW_MAC_EXT) {
  1073. /* dest mac mask must be ff:ff:ff:ff:ff:ff */
  1074. if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
  1075. return -EINVAL;
  1076. }
  1077. switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
  1078. case TCP_V4_FLOW:
  1079. case UDP_V4_FLOW:
  1080. if (cmd->fs.m_u.tcp_ip4_spec.tos)
  1081. return -EINVAL;
  1082. l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
  1083. /* don't allow mask which isn't all 0 or 1 */
  1084. if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
  1085. !all_zeros_or_all_ones(l4_mask->ip4dst) ||
  1086. !all_zeros_or_all_ones(l4_mask->psrc) ||
  1087. !all_zeros_or_all_ones(l4_mask->pdst))
  1088. return -EINVAL;
  1089. break;
  1090. case IP_USER_FLOW:
  1091. l3_mask = &cmd->fs.m_u.usr_ip4_spec;
  1092. if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
  1093. cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
  1094. (!l3_mask->ip4src && !l3_mask->ip4dst) ||
  1095. !all_zeros_or_all_ones(l3_mask->ip4src) ||
  1096. !all_zeros_or_all_ones(l3_mask->ip4dst))
  1097. return -EINVAL;
  1098. break;
  1099. case ETHER_FLOW:
  1100. eth_mask = &cmd->fs.m_u.ether_spec;
  1101. /* source mac mask must not be set */
  1102. if (!is_zero_ether_addr(eth_mask->h_source))
  1103. return -EINVAL;
  1104. /* dest mac mask must be ff:ff:ff:ff:ff:ff */
  1105. if (!is_broadcast_ether_addr(eth_mask->h_dest))
  1106. return -EINVAL;
  1107. if (!all_zeros_or_all_ones(eth_mask->h_proto))
  1108. return -EINVAL;
  1109. break;
  1110. default:
  1111. return -EINVAL;
  1112. }
  1113. if ((cmd->fs.flow_type & FLOW_EXT)) {
  1114. if (cmd->fs.m_ext.vlan_etype ||
  1115. !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
  1116. 0 ||
  1117. (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
  1118. cpu_to_be16(VLAN_VID_MASK)))
  1119. return -EINVAL;
  1120. if (cmd->fs.m_ext.vlan_tci) {
  1121. if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
  1122. return -EINVAL;
  1123. }
  1124. }
  1125. return 0;
  1126. }
  1127. static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
  1128. struct list_head *rule_list_h,
  1129. struct mlx4_spec_list *spec_l2,
  1130. unsigned char *mac)
  1131. {
  1132. int err = 0;
  1133. __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
  1134. spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
  1135. memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
  1136. memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
  1137. if ((cmd->fs.flow_type & FLOW_EXT) &&
  1138. (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
  1139. spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
  1140. spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
  1141. }
  1142. list_add_tail(&spec_l2->list, rule_list_h);
  1143. return err;
  1144. }
  1145. static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
  1146. struct ethtool_rxnfc *cmd,
  1147. struct list_head *rule_list_h,
  1148. struct mlx4_spec_list *spec_l2,
  1149. __be32 ipv4_dst)
  1150. {
  1151. #ifdef CONFIG_INET
  1152. unsigned char mac[ETH_ALEN];
  1153. if (!ipv4_is_multicast(ipv4_dst)) {
  1154. if (cmd->fs.flow_type & FLOW_MAC_EXT)
  1155. memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
  1156. else
  1157. memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
  1158. } else {
  1159. ip_eth_mc_map(ipv4_dst, mac);
  1160. }
  1161. return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
  1162. #else
  1163. return -EINVAL;
  1164. #endif
  1165. }
  1166. static int add_ip_rule(struct mlx4_en_priv *priv,
  1167. struct ethtool_rxnfc *cmd,
  1168. struct list_head *list_h)
  1169. {
  1170. int err;
  1171. struct mlx4_spec_list *spec_l2 = NULL;
  1172. struct mlx4_spec_list *spec_l3 = NULL;
  1173. struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
  1174. spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
  1175. spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
  1176. if (!spec_l2 || !spec_l3) {
  1177. err = -ENOMEM;
  1178. goto free_spec;
  1179. }
  1180. err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
  1181. cmd->fs.h_u.
  1182. usr_ip4_spec.ip4dst);
  1183. if (err)
  1184. goto free_spec;
  1185. spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
  1186. spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
  1187. if (l3_mask->ip4src)
  1188. spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
  1189. spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
  1190. if (l3_mask->ip4dst)
  1191. spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
  1192. list_add_tail(&spec_l3->list, list_h);
  1193. return 0;
  1194. free_spec:
  1195. kfree(spec_l2);
  1196. kfree(spec_l3);
  1197. return err;
  1198. }
  1199. static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
  1200. struct ethtool_rxnfc *cmd,
  1201. struct list_head *list_h, int proto)
  1202. {
  1203. int err;
  1204. struct mlx4_spec_list *spec_l2 = NULL;
  1205. struct mlx4_spec_list *spec_l3 = NULL;
  1206. struct mlx4_spec_list *spec_l4 = NULL;
  1207. struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
  1208. spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
  1209. spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
  1210. spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
  1211. if (!spec_l2 || !spec_l3 || !spec_l4) {
  1212. err = -ENOMEM;
  1213. goto free_spec;
  1214. }
  1215. spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
  1216. if (proto == TCP_V4_FLOW) {
  1217. err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
  1218. spec_l2,
  1219. cmd->fs.h_u.
  1220. tcp_ip4_spec.ip4dst);
  1221. if (err)
  1222. goto free_spec;
  1223. spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
  1224. spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
  1225. spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
  1226. spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
  1227. spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
  1228. } else {
  1229. err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
  1230. spec_l2,
  1231. cmd->fs.h_u.
  1232. udp_ip4_spec.ip4dst);
  1233. if (err)
  1234. goto free_spec;
  1235. spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
  1236. spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
  1237. spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
  1238. spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
  1239. spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
  1240. }
  1241. if (l4_mask->ip4src)
  1242. spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
  1243. if (l4_mask->ip4dst)
  1244. spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
  1245. if (l4_mask->psrc)
  1246. spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
  1247. if (l4_mask->pdst)
  1248. spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
  1249. list_add_tail(&spec_l3->list, list_h);
  1250. list_add_tail(&spec_l4->list, list_h);
  1251. return 0;
  1252. free_spec:
  1253. kfree(spec_l2);
  1254. kfree(spec_l3);
  1255. kfree(spec_l4);
  1256. return err;
  1257. }
  1258. static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
  1259. struct ethtool_rxnfc *cmd,
  1260. struct list_head *rule_list_h)
  1261. {
  1262. int err;
  1263. struct ethhdr *eth_spec;
  1264. struct mlx4_spec_list *spec_l2;
  1265. struct mlx4_en_priv *priv = netdev_priv(dev);
  1266. err = mlx4_en_validate_flow(dev, cmd);
  1267. if (err)
  1268. return err;
  1269. switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
  1270. case ETHER_FLOW:
  1271. spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
  1272. if (!spec_l2)
  1273. return -ENOMEM;
  1274. eth_spec = &cmd->fs.h_u.ether_spec;
  1275. mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
  1276. &eth_spec->h_dest[0]);
  1277. spec_l2->eth.ether_type = eth_spec->h_proto;
  1278. if (eth_spec->h_proto)
  1279. spec_l2->eth.ether_type_enable = 1;
  1280. break;
  1281. case IP_USER_FLOW:
  1282. err = add_ip_rule(priv, cmd, rule_list_h);
  1283. break;
  1284. case TCP_V4_FLOW:
  1285. err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
  1286. break;
  1287. case UDP_V4_FLOW:
  1288. err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
  1289. break;
  1290. }
  1291. return err;
  1292. }
  1293. static int mlx4_en_flow_replace(struct net_device *dev,
  1294. struct ethtool_rxnfc *cmd)
  1295. {
  1296. int err;
  1297. struct mlx4_en_priv *priv = netdev_priv(dev);
  1298. struct ethtool_flow_id *loc_rule;
  1299. struct mlx4_spec_list *spec, *tmp_spec;
  1300. u32 qpn;
  1301. u64 reg_id;
  1302. struct mlx4_net_trans_rule rule = {
  1303. .queue_mode = MLX4_NET_TRANS_Q_FIFO,
  1304. .exclusive = 0,
  1305. .allow_loopback = 1,
  1306. .promisc_mode = MLX4_FS_REGULAR,
  1307. };
  1308. rule.port = priv->port;
  1309. rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
  1310. INIT_LIST_HEAD(&rule.list);
  1311. /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */
  1312. if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
  1313. qpn = priv->drop_qp.qpn;
  1314. else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
  1315. qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
  1316. } else {
  1317. if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
  1318. en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
  1319. cmd->fs.ring_cookie);
  1320. return -EINVAL;
  1321. }
  1322. qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
  1323. if (!qpn) {
  1324. en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
  1325. cmd->fs.ring_cookie);
  1326. return -EINVAL;
  1327. }
  1328. }
  1329. rule.qpn = qpn;
  1330. err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
  1331. if (err)
  1332. goto out_free_list;
  1333. loc_rule = &priv->ethtool_rules[cmd->fs.location];
  1334. if (loc_rule->id) {
  1335. err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
  1336. if (err) {
  1337. en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
  1338. cmd->fs.location, loc_rule->id);
  1339. goto out_free_list;
  1340. }
  1341. loc_rule->id = 0;
  1342. memset(&loc_rule->flow_spec, 0,
  1343. sizeof(struct ethtool_rx_flow_spec));
  1344. list_del(&loc_rule->list);
  1345. }
  1346. err = mlx4_flow_attach(priv->mdev->dev, &rule, &reg_id);
  1347. if (err) {
  1348. en_err(priv, "Fail to attach network rule at location %d\n",
  1349. cmd->fs.location);
  1350. goto out_free_list;
  1351. }
  1352. loc_rule->id = reg_id;
  1353. memcpy(&loc_rule->flow_spec, &cmd->fs,
  1354. sizeof(struct ethtool_rx_flow_spec));
  1355. list_add_tail(&loc_rule->list, &priv->ethtool_list);
  1356. out_free_list:
  1357. list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
  1358. list_del(&spec->list);
  1359. kfree(spec);
  1360. }
  1361. return err;
  1362. }
  1363. static int mlx4_en_flow_detach(struct net_device *dev,
  1364. struct ethtool_rxnfc *cmd)
  1365. {
  1366. int err = 0;
  1367. struct ethtool_flow_id *rule;
  1368. struct mlx4_en_priv *priv = netdev_priv(dev);
  1369. if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
  1370. return -EINVAL;
  1371. rule = &priv->ethtool_rules[cmd->fs.location];
  1372. if (!rule->id) {
  1373. err = -ENOENT;
  1374. goto out;
  1375. }
  1376. err = mlx4_flow_detach(priv->mdev->dev, rule->id);
  1377. if (err) {
  1378. en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
  1379. cmd->fs.location, rule->id);
  1380. goto out;
  1381. }
  1382. rule->id = 0;
  1383. memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
  1384. list_del(&rule->list);
  1385. out:
  1386. return err;
  1387. }
  1388. static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
  1389. int loc)
  1390. {
  1391. int err = 0;
  1392. struct ethtool_flow_id *rule;
  1393. struct mlx4_en_priv *priv = netdev_priv(dev);
  1394. if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
  1395. return -EINVAL;
  1396. rule = &priv->ethtool_rules[loc];
  1397. if (rule->id)
  1398. memcpy(&cmd->fs, &rule->flow_spec,
  1399. sizeof(struct ethtool_rx_flow_spec));
  1400. else
  1401. err = -ENOENT;
  1402. return err;
  1403. }
  1404. static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
  1405. {
  1406. int i, res = 0;
  1407. for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
  1408. if (priv->ethtool_rules[i].id)
  1409. res++;
  1410. }
  1411. return res;
  1412. }
  1413. static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
  1414. u32 *rule_locs)
  1415. {
  1416. struct mlx4_en_priv *priv = netdev_priv(dev);
  1417. struct mlx4_en_dev *mdev = priv->mdev;
  1418. int err = 0;
  1419. int i = 0, priority = 0;
  1420. if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
  1421. cmd->cmd == ETHTOOL_GRXCLSRULE ||
  1422. cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
  1423. (mdev->dev->caps.steering_mode !=
  1424. MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
  1425. return -EINVAL;
  1426. switch (cmd->cmd) {
  1427. case ETHTOOL_GRXRINGS:
  1428. cmd->data = priv->rx_ring_num;
  1429. break;
  1430. case ETHTOOL_GRXCLSRLCNT:
  1431. cmd->rule_cnt = mlx4_en_get_num_flows(priv);
  1432. break;
  1433. case ETHTOOL_GRXCLSRULE:
  1434. err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
  1435. break;
  1436. case ETHTOOL_GRXCLSRLALL:
  1437. while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
  1438. err = mlx4_en_get_flow(dev, cmd, i);
  1439. if (!err)
  1440. rule_locs[priority++] = i;
  1441. i++;
  1442. }
  1443. err = 0;
  1444. break;
  1445. default:
  1446. err = -EOPNOTSUPP;
  1447. break;
  1448. }
  1449. return err;
  1450. }
  1451. static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
  1452. {
  1453. int err = 0;
  1454. struct mlx4_en_priv *priv = netdev_priv(dev);
  1455. struct mlx4_en_dev *mdev = priv->mdev;
  1456. if (mdev->dev->caps.steering_mode !=
  1457. MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
  1458. return -EINVAL;
  1459. switch (cmd->cmd) {
  1460. case ETHTOOL_SRXCLSRLINS:
  1461. err = mlx4_en_flow_replace(dev, cmd);
  1462. break;
  1463. case ETHTOOL_SRXCLSRLDEL:
  1464. err = mlx4_en_flow_detach(dev, cmd);
  1465. break;
  1466. default:
  1467. en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
  1468. return -EINVAL;
  1469. }
  1470. return err;
  1471. }
  1472. static void mlx4_en_get_channels(struct net_device *dev,
  1473. struct ethtool_channels *channel)
  1474. {
  1475. struct mlx4_en_priv *priv = netdev_priv(dev);
  1476. memset(channel, 0, sizeof(*channel));
  1477. channel->max_rx = MAX_RX_RINGS;
  1478. channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
  1479. channel->rx_count = priv->rx_ring_num;
  1480. channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP;
  1481. }
  1482. static int mlx4_en_set_channels(struct net_device *dev,
  1483. struct ethtool_channels *channel)
  1484. {
  1485. struct mlx4_en_priv *priv = netdev_priv(dev);
  1486. struct mlx4_en_dev *mdev = priv->mdev;
  1487. struct mlx4_en_port_profile new_prof;
  1488. struct mlx4_en_priv *tmp;
  1489. int port_up = 0;
  1490. int err = 0;
  1491. if (channel->other_count || channel->combined_count ||
  1492. channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP ||
  1493. channel->rx_count > MAX_RX_RINGS ||
  1494. !channel->tx_count || !channel->rx_count)
  1495. return -EINVAL;
  1496. if (channel->tx_count * MLX4_EN_NUM_UP <= priv->xdp_ring_num) {
  1497. en_err(priv, "Minimum %d tx channels required with XDP on\n",
  1498. priv->xdp_ring_num / MLX4_EN_NUM_UP + 1);
  1499. return -EINVAL;
  1500. }
  1501. tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
  1502. if (!tmp)
  1503. return -ENOMEM;
  1504. mutex_lock(&mdev->state_lock);
  1505. memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
  1506. new_prof.num_tx_rings_p_up = channel->tx_count;
  1507. new_prof.tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP;
  1508. new_prof.rx_ring_num = channel->rx_count;
  1509. err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof);
  1510. if (err)
  1511. goto out;
  1512. if (priv->port_up) {
  1513. port_up = 1;
  1514. mlx4_en_stop_port(dev, 1);
  1515. }
  1516. mlx4_en_safe_replace_resources(priv, tmp);
  1517. netif_set_real_num_tx_queues(dev, priv->tx_ring_num -
  1518. priv->xdp_ring_num);
  1519. netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
  1520. if (dev->num_tc)
  1521. mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP);
  1522. en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num);
  1523. en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
  1524. if (port_up) {
  1525. err = mlx4_en_start_port(dev);
  1526. if (err)
  1527. en_err(priv, "Failed starting port\n");
  1528. }
  1529. err = mlx4_en_moderation_update(priv);
  1530. out:
  1531. kfree(tmp);
  1532. mutex_unlock(&mdev->state_lock);
  1533. return err;
  1534. }
  1535. static int mlx4_en_get_ts_info(struct net_device *dev,
  1536. struct ethtool_ts_info *info)
  1537. {
  1538. struct mlx4_en_priv *priv = netdev_priv(dev);
  1539. struct mlx4_en_dev *mdev = priv->mdev;
  1540. int ret;
  1541. ret = ethtool_op_get_ts_info(dev, info);
  1542. if (ret)
  1543. return ret;
  1544. if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
  1545. info->so_timestamping |=
  1546. SOF_TIMESTAMPING_TX_HARDWARE |
  1547. SOF_TIMESTAMPING_RX_HARDWARE |
  1548. SOF_TIMESTAMPING_RAW_HARDWARE;
  1549. info->tx_types =
  1550. (1 << HWTSTAMP_TX_OFF) |
  1551. (1 << HWTSTAMP_TX_ON);
  1552. info->rx_filters =
  1553. (1 << HWTSTAMP_FILTER_NONE) |
  1554. (1 << HWTSTAMP_FILTER_ALL);
  1555. if (mdev->ptp_clock)
  1556. info->phc_index = ptp_clock_index(mdev->ptp_clock);
  1557. }
  1558. return ret;
  1559. }
  1560. static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
  1561. {
  1562. struct mlx4_en_priv *priv = netdev_priv(dev);
  1563. struct mlx4_en_dev *mdev = priv->mdev;
  1564. bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
  1565. bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
  1566. bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV);
  1567. bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV);
  1568. int i;
  1569. int ret = 0;
  1570. if (bf_enabled_new != bf_enabled_old) {
  1571. if (bf_enabled_new) {
  1572. bool bf_supported = true;
  1573. for (i = 0; i < priv->tx_ring_num; i++)
  1574. bf_supported &= priv->tx_ring[i]->bf_alloced;
  1575. if (!bf_supported) {
  1576. en_err(priv, "BlueFlame is not supported\n");
  1577. return -EINVAL;
  1578. }
  1579. priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
  1580. } else {
  1581. priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
  1582. }
  1583. for (i = 0; i < priv->tx_ring_num; i++)
  1584. priv->tx_ring[i]->bf_enabled = bf_enabled_new;
  1585. en_info(priv, "BlueFlame %s\n",
  1586. bf_enabled_new ? "Enabled" : "Disabled");
  1587. }
  1588. if (phv_enabled_new != phv_enabled_old) {
  1589. ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new);
  1590. if (ret)
  1591. return ret;
  1592. else if (phv_enabled_new)
  1593. priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
  1594. else
  1595. priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV;
  1596. en_info(priv, "PHV bit %s\n",
  1597. phv_enabled_new ? "Enabled" : "Disabled");
  1598. }
  1599. return 0;
  1600. }
  1601. static u32 mlx4_en_get_priv_flags(struct net_device *dev)
  1602. {
  1603. struct mlx4_en_priv *priv = netdev_priv(dev);
  1604. return priv->pflags;
  1605. }
  1606. static int mlx4_en_get_tunable(struct net_device *dev,
  1607. const struct ethtool_tunable *tuna,
  1608. void *data)
  1609. {
  1610. const struct mlx4_en_priv *priv = netdev_priv(dev);
  1611. int ret = 0;
  1612. switch (tuna->id) {
  1613. case ETHTOOL_TX_COPYBREAK:
  1614. *(u32 *)data = priv->prof->inline_thold;
  1615. break;
  1616. default:
  1617. ret = -EINVAL;
  1618. break;
  1619. }
  1620. return ret;
  1621. }
  1622. static int mlx4_en_set_tunable(struct net_device *dev,
  1623. const struct ethtool_tunable *tuna,
  1624. const void *data)
  1625. {
  1626. struct mlx4_en_priv *priv = netdev_priv(dev);
  1627. int val, ret = 0;
  1628. switch (tuna->id) {
  1629. case ETHTOOL_TX_COPYBREAK:
  1630. val = *(u32 *)data;
  1631. if (val < MIN_PKT_LEN || val > MAX_INLINE)
  1632. ret = -EINVAL;
  1633. else
  1634. priv->prof->inline_thold = val;
  1635. break;
  1636. default:
  1637. ret = -EINVAL;
  1638. break;
  1639. }
  1640. return ret;
  1641. }
  1642. static int mlx4_en_get_module_info(struct net_device *dev,
  1643. struct ethtool_modinfo *modinfo)
  1644. {
  1645. struct mlx4_en_priv *priv = netdev_priv(dev);
  1646. struct mlx4_en_dev *mdev = priv->mdev;
  1647. int ret;
  1648. u8 data[4];
  1649. /* Read first 2 bytes to get Module & REV ID */
  1650. ret = mlx4_get_module_info(mdev->dev, priv->port,
  1651. 0/*offset*/, 2/*size*/, data);
  1652. if (ret < 2)
  1653. return -EIO;
  1654. switch (data[0] /* identifier */) {
  1655. case MLX4_MODULE_ID_QSFP:
  1656. modinfo->type = ETH_MODULE_SFF_8436;
  1657. modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
  1658. break;
  1659. case MLX4_MODULE_ID_QSFP_PLUS:
  1660. if (data[1] >= 0x3) { /* revision id */
  1661. modinfo->type = ETH_MODULE_SFF_8636;
  1662. modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
  1663. } else {
  1664. modinfo->type = ETH_MODULE_SFF_8436;
  1665. modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
  1666. }
  1667. break;
  1668. case MLX4_MODULE_ID_QSFP28:
  1669. modinfo->type = ETH_MODULE_SFF_8636;
  1670. modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
  1671. break;
  1672. case MLX4_MODULE_ID_SFP:
  1673. modinfo->type = ETH_MODULE_SFF_8472;
  1674. modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
  1675. break;
  1676. default:
  1677. return -ENOSYS;
  1678. }
  1679. return 0;
  1680. }
  1681. static int mlx4_en_get_module_eeprom(struct net_device *dev,
  1682. struct ethtool_eeprom *ee,
  1683. u8 *data)
  1684. {
  1685. struct mlx4_en_priv *priv = netdev_priv(dev);
  1686. struct mlx4_en_dev *mdev = priv->mdev;
  1687. int offset = ee->offset;
  1688. int i = 0, ret;
  1689. if (ee->len == 0)
  1690. return -EINVAL;
  1691. memset(data, 0, ee->len);
  1692. while (i < ee->len) {
  1693. en_dbg(DRV, priv,
  1694. "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
  1695. i, offset, ee->len - i);
  1696. ret = mlx4_get_module_info(mdev->dev, priv->port,
  1697. offset, ee->len - i, data + i);
  1698. if (!ret) /* Done reading */
  1699. return 0;
  1700. if (ret < 0) {
  1701. en_err(priv,
  1702. "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
  1703. i, offset, ee->len - i, ret);
  1704. return 0;
  1705. }
  1706. i += ret;
  1707. offset += ret;
  1708. }
  1709. return 0;
  1710. }
  1711. static int mlx4_en_set_phys_id(struct net_device *dev,
  1712. enum ethtool_phys_id_state state)
  1713. {
  1714. int err;
  1715. u16 beacon_duration;
  1716. struct mlx4_en_priv *priv = netdev_priv(dev);
  1717. struct mlx4_en_dev *mdev = priv->mdev;
  1718. if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON))
  1719. return -EOPNOTSUPP;
  1720. switch (state) {
  1721. case ETHTOOL_ID_ACTIVE:
  1722. beacon_duration = PORT_BEACON_MAX_LIMIT;
  1723. break;
  1724. case ETHTOOL_ID_INACTIVE:
  1725. beacon_duration = 0;
  1726. break;
  1727. default:
  1728. return -EOPNOTSUPP;
  1729. }
  1730. err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration);
  1731. return err;
  1732. }
  1733. const struct ethtool_ops mlx4_en_ethtool_ops = {
  1734. .get_drvinfo = mlx4_en_get_drvinfo,
  1735. .get_link_ksettings = mlx4_en_get_link_ksettings,
  1736. .set_link_ksettings = mlx4_en_set_link_ksettings,
  1737. .get_link = ethtool_op_get_link,
  1738. .get_strings = mlx4_en_get_strings,
  1739. .get_sset_count = mlx4_en_get_sset_count,
  1740. .get_ethtool_stats = mlx4_en_get_ethtool_stats,
  1741. .self_test = mlx4_en_self_test,
  1742. .set_phys_id = mlx4_en_set_phys_id,
  1743. .get_wol = mlx4_en_get_wol,
  1744. .set_wol = mlx4_en_set_wol,
  1745. .get_msglevel = mlx4_en_get_msglevel,
  1746. .set_msglevel = mlx4_en_set_msglevel,
  1747. .get_coalesce = mlx4_en_get_coalesce,
  1748. .set_coalesce = mlx4_en_set_coalesce,
  1749. .get_pauseparam = mlx4_en_get_pauseparam,
  1750. .set_pauseparam = mlx4_en_set_pauseparam,
  1751. .get_ringparam = mlx4_en_get_ringparam,
  1752. .set_ringparam = mlx4_en_set_ringparam,
  1753. .get_rxnfc = mlx4_en_get_rxnfc,
  1754. .set_rxnfc = mlx4_en_set_rxnfc,
  1755. .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
  1756. .get_rxfh_key_size = mlx4_en_get_rxfh_key_size,
  1757. .get_rxfh = mlx4_en_get_rxfh,
  1758. .set_rxfh = mlx4_en_set_rxfh,
  1759. .get_channels = mlx4_en_get_channels,
  1760. .set_channels = mlx4_en_set_channels,
  1761. .get_ts_info = mlx4_en_get_ts_info,
  1762. .set_priv_flags = mlx4_en_set_priv_flags,
  1763. .get_priv_flags = mlx4_en_get_priv_flags,
  1764. .get_tunable = mlx4_en_get_tunable,
  1765. .set_tunable = mlx4_en_set_tunable,
  1766. .get_module_info = mlx4_en_get_module_info,
  1767. .get_module_eeprom = mlx4_en_get_module_eeprom
  1768. };