fm10k.h 15 KB

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  1. /* Intel(R) Ethernet Switch Host Interface Driver
  2. * Copyright(c) 2013 - 2016 Intel Corporation.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * The full GNU General Public License is included in this distribution in
  14. * the file called "COPYING".
  15. *
  16. * Contact Information:
  17. * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  18. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  19. */
  20. #ifndef _FM10K_H_
  21. #define _FM10K_H_
  22. #include <linux/types.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/cpumask.h>
  25. #include <linux/rtnetlink.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/pci.h>
  28. #include "fm10k_pf.h"
  29. #include "fm10k_vf.h"
  30. #define FM10K_MAX_JUMBO_FRAME_SIZE 15342 /* Maximum supported size 15K */
  31. #define MAX_QUEUES FM10K_MAX_QUEUES_PF
  32. #define FM10K_MIN_RXD 128
  33. #define FM10K_MAX_RXD 4096
  34. #define FM10K_DEFAULT_RXD 256
  35. #define FM10K_MIN_TXD 128
  36. #define FM10K_MAX_TXD 4096
  37. #define FM10K_DEFAULT_TXD 256
  38. #define FM10K_DEFAULT_TX_WORK 256
  39. #define FM10K_RXBUFFER_256 256
  40. #define FM10K_RX_HDR_LEN FM10K_RXBUFFER_256
  41. #define FM10K_RXBUFFER_2048 2048
  42. #define FM10K_RX_BUFSZ FM10K_RXBUFFER_2048
  43. /* How many Rx Buffers do we bundle into one write to the hardware ? */
  44. #define FM10K_RX_BUFFER_WRITE 16 /* Must be power of 2 */
  45. #define FM10K_MAX_STATIONS 63
  46. struct fm10k_l2_accel {
  47. int size;
  48. u16 count;
  49. u16 dglort;
  50. struct rcu_head rcu;
  51. struct net_device *macvlan[0];
  52. };
  53. enum fm10k_ring_state_t {
  54. __FM10K_TX_DETECT_HANG,
  55. __FM10K_HANG_CHECK_ARMED,
  56. __FM10K_TX_XPS_INIT_DONE,
  57. };
  58. #define check_for_tx_hang(ring) \
  59. test_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
  60. #define set_check_for_tx_hang(ring) \
  61. set_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
  62. #define clear_check_for_tx_hang(ring) \
  63. clear_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
  64. struct fm10k_tx_buffer {
  65. struct fm10k_tx_desc *next_to_watch;
  66. struct sk_buff *skb;
  67. unsigned int bytecount;
  68. u16 gso_segs;
  69. u16 tx_flags;
  70. DEFINE_DMA_UNMAP_ADDR(dma);
  71. DEFINE_DMA_UNMAP_LEN(len);
  72. };
  73. struct fm10k_rx_buffer {
  74. dma_addr_t dma;
  75. struct page *page;
  76. u32 page_offset;
  77. };
  78. struct fm10k_queue_stats {
  79. u64 packets;
  80. u64 bytes;
  81. };
  82. struct fm10k_tx_queue_stats {
  83. u64 restart_queue;
  84. u64 csum_err;
  85. u64 tx_busy;
  86. u64 tx_done_old;
  87. u64 csum_good;
  88. };
  89. struct fm10k_rx_queue_stats {
  90. u64 alloc_failed;
  91. u64 csum_err;
  92. u64 errors;
  93. u64 csum_good;
  94. u64 switch_errors;
  95. u64 drops;
  96. u64 pp_errors;
  97. u64 link_errors;
  98. u64 length_errors;
  99. };
  100. struct fm10k_ring {
  101. struct fm10k_q_vector *q_vector;/* backpointer to host q_vector */
  102. struct net_device *netdev; /* netdev ring belongs to */
  103. struct device *dev; /* device for DMA mapping */
  104. struct fm10k_l2_accel __rcu *l2_accel; /* L2 acceleration list */
  105. void *desc; /* descriptor ring memory */
  106. union {
  107. struct fm10k_tx_buffer *tx_buffer;
  108. struct fm10k_rx_buffer *rx_buffer;
  109. };
  110. u32 __iomem *tail;
  111. unsigned long state;
  112. dma_addr_t dma; /* phys. address of descriptor ring */
  113. unsigned int size; /* length in bytes */
  114. u8 queue_index; /* needed for queue management */
  115. u8 reg_idx; /* holds the special value that gets
  116. * the hardware register offset
  117. * associated with this ring, which is
  118. * different for DCB and RSS modes
  119. */
  120. u8 qos_pc; /* priority class of queue */
  121. u16 vid; /* default VLAN ID of queue */
  122. u16 count; /* amount of descriptors */
  123. u16 next_to_alloc;
  124. u16 next_to_use;
  125. u16 next_to_clean;
  126. struct fm10k_queue_stats stats;
  127. struct u64_stats_sync syncp;
  128. union {
  129. /* Tx */
  130. struct fm10k_tx_queue_stats tx_stats;
  131. /* Rx */
  132. struct {
  133. struct fm10k_rx_queue_stats rx_stats;
  134. struct sk_buff *skb;
  135. };
  136. };
  137. } ____cacheline_internodealigned_in_smp;
  138. struct fm10k_ring_container {
  139. struct fm10k_ring *ring; /* pointer to linked list of rings */
  140. unsigned int total_bytes; /* total bytes processed this int */
  141. unsigned int total_packets; /* total packets processed this int */
  142. u16 work_limit; /* total work allowed per interrupt */
  143. u16 itr; /* interrupt throttle rate value */
  144. u8 itr_scale; /* ITR adjustment based on PCI speed */
  145. u8 count; /* total number of rings in vector */
  146. };
  147. #define FM10K_ITR_MAX 0x0FFF /* maximum value for ITR */
  148. #define FM10K_ITR_10K 100 /* 100us */
  149. #define FM10K_ITR_20K 50 /* 50us */
  150. #define FM10K_ITR_40K 25 /* 25us */
  151. #define FM10K_ITR_ADAPTIVE 0x8000 /* adaptive interrupt moderation flag */
  152. #define ITR_IS_ADAPTIVE(itr) (!!(itr & FM10K_ITR_ADAPTIVE))
  153. #define FM10K_TX_ITR_DEFAULT FM10K_ITR_40K
  154. #define FM10K_RX_ITR_DEFAULT FM10K_ITR_20K
  155. #define FM10K_ITR_ENABLE (FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR)
  156. static inline struct netdev_queue *txring_txq(const struct fm10k_ring *ring)
  157. {
  158. return &ring->netdev->_tx[ring->queue_index];
  159. }
  160. /* iterator for handling rings in ring container */
  161. #define fm10k_for_each_ring(pos, head) \
  162. for (pos = &(head).ring[(head).count]; (--pos) >= (head).ring;)
  163. #define MAX_Q_VECTORS 256
  164. #define MIN_Q_VECTORS 1
  165. enum fm10k_non_q_vectors {
  166. FM10K_MBX_VECTOR,
  167. #define NON_Q_VECTORS_VF NON_Q_VECTORS_PF
  168. NON_Q_VECTORS_PF
  169. };
  170. #define NON_Q_VECTORS(hw) (((hw)->mac.type == fm10k_mac_pf) ? \
  171. NON_Q_VECTORS_PF : \
  172. NON_Q_VECTORS_VF)
  173. #define MIN_MSIX_COUNT(hw) (MIN_Q_VECTORS + NON_Q_VECTORS(hw))
  174. struct fm10k_q_vector {
  175. struct fm10k_intfc *interface;
  176. u32 __iomem *itr; /* pointer to ITR register for this vector */
  177. u16 v_idx; /* index of q_vector within interface array */
  178. struct fm10k_ring_container rx, tx;
  179. struct napi_struct napi;
  180. cpumask_t affinity_mask;
  181. char name[IFNAMSIZ + 9];
  182. #ifdef CONFIG_DEBUG_FS
  183. struct dentry *dbg_q_vector;
  184. #endif /* CONFIG_DEBUG_FS */
  185. struct rcu_head rcu; /* to avoid race with update stats on free */
  186. /* for dynamic allocation of rings associated with this q_vector */
  187. struct fm10k_ring ring[0] ____cacheline_internodealigned_in_smp;
  188. };
  189. enum fm10k_ring_f_enum {
  190. RING_F_RSS,
  191. RING_F_QOS,
  192. RING_F_ARRAY_SIZE /* must be last in enum set */
  193. };
  194. struct fm10k_ring_feature {
  195. u16 limit; /* upper limit on feature indices */
  196. u16 indices; /* current value of indices */
  197. u16 mask; /* Mask used for feature to ring mapping */
  198. u16 offset; /* offset to start of feature */
  199. };
  200. struct fm10k_iov_data {
  201. unsigned int num_vfs;
  202. unsigned int next_vf_mbx;
  203. struct rcu_head rcu;
  204. struct fm10k_vf_info vf_info[0];
  205. };
  206. struct fm10k_udp_port {
  207. struct list_head list;
  208. sa_family_t sa_family;
  209. __be16 port;
  210. };
  211. /* one work queue for entire driver */
  212. extern struct workqueue_struct *fm10k_workqueue;
  213. struct fm10k_intfc {
  214. unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
  215. struct net_device *netdev;
  216. struct fm10k_l2_accel *l2_accel; /* pointer to L2 acceleration list */
  217. struct pci_dev *pdev;
  218. unsigned long state;
  219. u32 flags;
  220. #define FM10K_FLAG_RESET_REQUESTED (u32)(BIT(0))
  221. #define FM10K_FLAG_RSS_FIELD_IPV4_UDP (u32)(BIT(1))
  222. #define FM10K_FLAG_RSS_FIELD_IPV6_UDP (u32)(BIT(2))
  223. #define FM10K_FLAG_RX_TS_ENABLED (u32)(BIT(3))
  224. #define FM10K_FLAG_SWPRI_CONFIG (u32)(BIT(4))
  225. #define FM10K_FLAG_DEBUG_STATS (u32)(BIT(5))
  226. int xcast_mode;
  227. /* Tx fast path data */
  228. int num_tx_queues;
  229. u16 tx_itr;
  230. /* Rx fast path data */
  231. int num_rx_queues;
  232. u16 rx_itr;
  233. /* TX */
  234. struct fm10k_ring *tx_ring[MAX_QUEUES] ____cacheline_aligned_in_smp;
  235. u64 restart_queue;
  236. u64 tx_busy;
  237. u64 tx_csum_errors;
  238. u64 alloc_failed;
  239. u64 rx_csum_errors;
  240. u64 tx_bytes_nic;
  241. u64 tx_packets_nic;
  242. u64 rx_bytes_nic;
  243. u64 rx_packets_nic;
  244. u64 rx_drops_nic;
  245. u64 rx_overrun_pf;
  246. u64 rx_overrun_vf;
  247. /* Debug Statistics */
  248. u64 hw_sm_mbx_full;
  249. u64 hw_csum_tx_good;
  250. u64 hw_csum_rx_good;
  251. u64 rx_switch_errors;
  252. u64 rx_drops;
  253. u64 rx_pp_errors;
  254. u64 rx_link_errors;
  255. u64 rx_length_errors;
  256. u32 tx_timeout_count;
  257. /* RX */
  258. struct fm10k_ring *rx_ring[MAX_QUEUES];
  259. /* Queueing vectors */
  260. struct fm10k_q_vector *q_vector[MAX_Q_VECTORS];
  261. struct msix_entry *msix_entries;
  262. int num_q_vectors; /* current number of q_vectors for device */
  263. struct fm10k_ring_feature ring_feature[RING_F_ARRAY_SIZE];
  264. /* SR-IOV information management structure */
  265. struct fm10k_iov_data *iov_data;
  266. struct fm10k_hw_stats stats;
  267. struct fm10k_hw hw;
  268. u32 __iomem *uc_addr;
  269. u32 __iomem *sw_addr;
  270. u16 msg_enable;
  271. u16 tx_ring_count;
  272. u16 rx_ring_count;
  273. struct timer_list service_timer;
  274. struct work_struct service_task;
  275. unsigned long next_stats_update;
  276. unsigned long next_tx_hang_check;
  277. unsigned long last_reset;
  278. unsigned long link_down_event;
  279. bool host_ready;
  280. bool lport_map_failed;
  281. u32 reta[FM10K_RETA_SIZE];
  282. u32 rssrk[FM10K_RSSRK_SIZE];
  283. /* UDP encapsulation port tracking information */
  284. struct list_head vxlan_port;
  285. struct list_head geneve_port;
  286. #ifdef CONFIG_DEBUG_FS
  287. struct dentry *dbg_intfc;
  288. #endif /* CONFIG_DEBUG_FS */
  289. #ifdef CONFIG_DCB
  290. u8 pfc_en;
  291. #endif
  292. u8 rx_pause;
  293. /* GLORT resources in use by PF */
  294. u16 glort;
  295. u16 glort_count;
  296. /* VLAN ID for updating multicast/unicast lists */
  297. u16 vid;
  298. };
  299. enum fm10k_state_t {
  300. __FM10K_RESETTING,
  301. __FM10K_DOWN,
  302. __FM10K_SERVICE_SCHED,
  303. __FM10K_SERVICE_DISABLE,
  304. __FM10K_MBX_LOCK,
  305. __FM10K_LINK_DOWN,
  306. __FM10K_UPDATING_STATS,
  307. };
  308. static inline void fm10k_mbx_lock(struct fm10k_intfc *interface)
  309. {
  310. /* busy loop if we cannot obtain the lock as some calls
  311. * such as ndo_set_rx_mode may be made in atomic context
  312. */
  313. while (test_and_set_bit(__FM10K_MBX_LOCK, &interface->state))
  314. udelay(20);
  315. }
  316. static inline void fm10k_mbx_unlock(struct fm10k_intfc *interface)
  317. {
  318. /* flush memory to make sure state is correct */
  319. smp_mb__before_atomic();
  320. clear_bit(__FM10K_MBX_LOCK, &interface->state);
  321. }
  322. static inline int fm10k_mbx_trylock(struct fm10k_intfc *interface)
  323. {
  324. return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state);
  325. }
  326. /* fm10k_test_staterr - test bits in Rx descriptor status and error fields */
  327. static inline __le32 fm10k_test_staterr(union fm10k_rx_desc *rx_desc,
  328. const u32 stat_err_bits)
  329. {
  330. return rx_desc->d.staterr & cpu_to_le32(stat_err_bits);
  331. }
  332. /* fm10k_desc_unused - calculate if we have unused descriptors */
  333. static inline u16 fm10k_desc_unused(struct fm10k_ring *ring)
  334. {
  335. s16 unused = ring->next_to_clean - ring->next_to_use - 1;
  336. return likely(unused < 0) ? unused + ring->count : unused;
  337. }
  338. #define FM10K_TX_DESC(R, i) \
  339. (&(((struct fm10k_tx_desc *)((R)->desc))[i]))
  340. #define FM10K_RX_DESC(R, i) \
  341. (&(((union fm10k_rx_desc *)((R)->desc))[i]))
  342. #define FM10K_MAX_TXD_PWR 14
  343. #define FM10K_MAX_DATA_PER_TXD (1u << FM10K_MAX_TXD_PWR)
  344. /* Tx Descriptors needed, worst case */
  345. #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), FM10K_MAX_DATA_PER_TXD)
  346. #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
  347. enum fm10k_tx_flags {
  348. /* Tx offload flags */
  349. FM10K_TX_FLAGS_CSUM = 0x01,
  350. };
  351. /* This structure is stored as little endian values as that is the native
  352. * format of the Rx descriptor. The ordering of these fields is reversed
  353. * from the actual ftag header to allow for a single bswap to take care
  354. * of placing all of the values in network order
  355. */
  356. union fm10k_ftag_info {
  357. __le64 ftag;
  358. struct {
  359. /* dglort and sglort combined into a single 32bit desc read */
  360. __le32 glort;
  361. /* upper 16 bits of VLAN are reserved 0 for swpri_type_user */
  362. __le32 vlan;
  363. } d;
  364. struct {
  365. __le16 dglort;
  366. __le16 sglort;
  367. __le16 vlan;
  368. __le16 swpri_type_user;
  369. } w;
  370. };
  371. struct fm10k_cb {
  372. union {
  373. __le64 tstamp;
  374. unsigned long ts_tx_timeout;
  375. };
  376. union fm10k_ftag_info fi;
  377. };
  378. #define FM10K_CB(skb) ((struct fm10k_cb *)(skb)->cb)
  379. /* main */
  380. extern char fm10k_driver_name[];
  381. extern const char fm10k_driver_version[];
  382. int fm10k_init_queueing_scheme(struct fm10k_intfc *interface);
  383. void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface);
  384. __be16 fm10k_tx_encap_offload(struct sk_buff *skb);
  385. netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb,
  386. struct fm10k_ring *tx_ring);
  387. void fm10k_tx_timeout_reset(struct fm10k_intfc *interface);
  388. u64 fm10k_get_tx_pending(struct fm10k_ring *ring, bool in_sw);
  389. bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring);
  390. void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count);
  391. /* PCI */
  392. void fm10k_mbx_free_irq(struct fm10k_intfc *);
  393. int fm10k_mbx_request_irq(struct fm10k_intfc *);
  394. void fm10k_qv_free_irq(struct fm10k_intfc *interface);
  395. int fm10k_qv_request_irq(struct fm10k_intfc *interface);
  396. int fm10k_register_pci_driver(void);
  397. void fm10k_unregister_pci_driver(void);
  398. void fm10k_up(struct fm10k_intfc *interface);
  399. void fm10k_down(struct fm10k_intfc *interface);
  400. void fm10k_update_stats(struct fm10k_intfc *interface);
  401. void fm10k_service_event_schedule(struct fm10k_intfc *interface);
  402. void fm10k_update_rx_drop_en(struct fm10k_intfc *interface);
  403. #ifdef CONFIG_NET_POLL_CONTROLLER
  404. void fm10k_netpoll(struct net_device *netdev);
  405. #endif
  406. /* Netdev */
  407. struct net_device *fm10k_alloc_netdev(const struct fm10k_info *info);
  408. int fm10k_setup_rx_resources(struct fm10k_ring *);
  409. int fm10k_setup_tx_resources(struct fm10k_ring *);
  410. void fm10k_free_rx_resources(struct fm10k_ring *);
  411. void fm10k_free_tx_resources(struct fm10k_ring *);
  412. void fm10k_clean_all_rx_rings(struct fm10k_intfc *);
  413. void fm10k_clean_all_tx_rings(struct fm10k_intfc *);
  414. void fm10k_unmap_and_free_tx_resource(struct fm10k_ring *,
  415. struct fm10k_tx_buffer *);
  416. void fm10k_restore_rx_state(struct fm10k_intfc *);
  417. void fm10k_reset_rx_state(struct fm10k_intfc *);
  418. int fm10k_setup_tc(struct net_device *dev, u8 tc);
  419. int fm10k_open(struct net_device *netdev);
  420. int fm10k_close(struct net_device *netdev);
  421. /* Ethtool */
  422. void fm10k_set_ethtool_ops(struct net_device *dev);
  423. void fm10k_write_reta(struct fm10k_intfc *interface, const u32 *indir);
  424. /* IOV */
  425. s32 fm10k_iov_event(struct fm10k_intfc *interface);
  426. s32 fm10k_iov_mbx(struct fm10k_intfc *interface);
  427. void fm10k_iov_suspend(struct pci_dev *pdev);
  428. int fm10k_iov_resume(struct pci_dev *pdev);
  429. void fm10k_iov_disable(struct pci_dev *pdev);
  430. int fm10k_iov_configure(struct pci_dev *pdev, int num_vfs);
  431. s32 fm10k_iov_update_pvid(struct fm10k_intfc *interface, u16 glort, u16 pvid);
  432. int fm10k_ndo_set_vf_mac(struct net_device *netdev, int vf_idx, u8 *mac);
  433. int fm10k_ndo_set_vf_vlan(struct net_device *netdev,
  434. int vf_idx, u16 vid, u8 qos, __be16 vlan_proto);
  435. int fm10k_ndo_set_vf_bw(struct net_device *netdev, int vf_idx,
  436. int __always_unused min_rate, int max_rate);
  437. int fm10k_ndo_get_vf_config(struct net_device *netdev,
  438. int vf_idx, struct ifla_vf_info *ivi);
  439. /* DebugFS */
  440. #ifdef CONFIG_DEBUG_FS
  441. void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector);
  442. void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector);
  443. void fm10k_dbg_intfc_init(struct fm10k_intfc *interface);
  444. void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface);
  445. void fm10k_dbg_init(void);
  446. void fm10k_dbg_exit(void);
  447. #else
  448. static inline void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector) {}
  449. static inline void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector) {}
  450. static inline void fm10k_dbg_intfc_init(struct fm10k_intfc *interface) {}
  451. static inline void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface) {}
  452. static inline void fm10k_dbg_init(void) {}
  453. static inline void fm10k_dbg_exit(void) {}
  454. #endif /* CONFIG_DEBUG_FS */
  455. /* DCB */
  456. #ifdef CONFIG_DCB
  457. void fm10k_dcbnl_set_ops(struct net_device *dev);
  458. #else
  459. static inline void fm10k_dcbnl_set_ops(struct net_device *dev) {}
  460. #endif
  461. #endif /* _FM10K_H_ */