cnic.c 149 KB

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  1. /* cnic.c: QLogic CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2014 Broadcom Corporation
  4. * Copyright (c) 2014-2015 QLogic Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation.
  9. *
  10. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  11. * Previously modified and maintained by: Michael Chan <mchan@broadcom.com>
  12. * Maintained By: Dept-HSGLinuxNICDev@qlogic.com
  13. */
  14. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/errno.h>
  18. #include <linux/list.h>
  19. #include <linux/slab.h>
  20. #include <linux/pci.h>
  21. #include <linux/init.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/uio_driver.h>
  24. #include <linux/in.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/delay.h>
  27. #include <linux/ethtool.h>
  28. #include <linux/if_vlan.h>
  29. #include <linux/prefetch.h>
  30. #include <linux/random.h>
  31. #if IS_ENABLED(CONFIG_VLAN_8021Q)
  32. #define BCM_VLAN 1
  33. #endif
  34. #include <net/ip.h>
  35. #include <net/tcp.h>
  36. #include <net/route.h>
  37. #include <net/ipv6.h>
  38. #include <net/ip6_route.h>
  39. #include <net/ip6_checksum.h>
  40. #include <scsi/iscsi_if.h>
  41. #define BCM_CNIC 1
  42. #include "cnic_if.h"
  43. #include "bnx2.h"
  44. #include "bnx2x/bnx2x.h"
  45. #include "bnx2x/bnx2x_reg.h"
  46. #include "bnx2x/bnx2x_fw_defs.h"
  47. #include "bnx2x/bnx2x_hsi.h"
  48. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  49. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  50. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  51. #include "cnic.h"
  52. #include "cnic_defs.h"
  53. #define CNIC_MODULE_NAME "cnic"
  54. static char version[] =
  55. "QLogic " CNIC_MODULE_NAME "Driver v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  56. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  57. "Chen (zongxi@broadcom.com");
  58. MODULE_DESCRIPTION("QLogic cnic Driver");
  59. MODULE_LICENSE("GPL");
  60. MODULE_VERSION(CNIC_MODULE_VERSION);
  61. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  62. static LIST_HEAD(cnic_dev_list);
  63. static LIST_HEAD(cnic_udev_list);
  64. static DEFINE_RWLOCK(cnic_dev_lock);
  65. static DEFINE_MUTEX(cnic_lock);
  66. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  67. /* helper function, assuming cnic_lock is held */
  68. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  69. {
  70. return rcu_dereference_protected(cnic_ulp_tbl[type],
  71. lockdep_is_held(&cnic_lock));
  72. }
  73. static int cnic_service_bnx2(void *, void *);
  74. static int cnic_service_bnx2x(void *, void *);
  75. static int cnic_ctl(void *, struct cnic_ctl_info *);
  76. static struct cnic_ops cnic_bnx2_ops = {
  77. .cnic_owner = THIS_MODULE,
  78. .cnic_handler = cnic_service_bnx2,
  79. .cnic_ctl = cnic_ctl,
  80. };
  81. static struct cnic_ops cnic_bnx2x_ops = {
  82. .cnic_owner = THIS_MODULE,
  83. .cnic_handler = cnic_service_bnx2x,
  84. .cnic_ctl = cnic_ctl,
  85. };
  86. static struct workqueue_struct *cnic_wq;
  87. static void cnic_shutdown_rings(struct cnic_dev *);
  88. static void cnic_init_rings(struct cnic_dev *);
  89. static int cnic_cm_set_pg(struct cnic_sock *);
  90. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  91. {
  92. struct cnic_uio_dev *udev = uinfo->priv;
  93. struct cnic_dev *dev;
  94. if (!capable(CAP_NET_ADMIN))
  95. return -EPERM;
  96. if (udev->uio_dev != -1)
  97. return -EBUSY;
  98. rtnl_lock();
  99. dev = udev->dev;
  100. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  101. rtnl_unlock();
  102. return -ENODEV;
  103. }
  104. udev->uio_dev = iminor(inode);
  105. cnic_shutdown_rings(dev);
  106. cnic_init_rings(dev);
  107. rtnl_unlock();
  108. return 0;
  109. }
  110. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  111. {
  112. struct cnic_uio_dev *udev = uinfo->priv;
  113. udev->uio_dev = -1;
  114. return 0;
  115. }
  116. static inline void cnic_hold(struct cnic_dev *dev)
  117. {
  118. atomic_inc(&dev->ref_count);
  119. }
  120. static inline void cnic_put(struct cnic_dev *dev)
  121. {
  122. atomic_dec(&dev->ref_count);
  123. }
  124. static inline void csk_hold(struct cnic_sock *csk)
  125. {
  126. atomic_inc(&csk->ref_count);
  127. }
  128. static inline void csk_put(struct cnic_sock *csk)
  129. {
  130. atomic_dec(&csk->ref_count);
  131. }
  132. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  133. {
  134. struct cnic_dev *cdev;
  135. read_lock(&cnic_dev_lock);
  136. list_for_each_entry(cdev, &cnic_dev_list, list) {
  137. if (netdev == cdev->netdev) {
  138. cnic_hold(cdev);
  139. read_unlock(&cnic_dev_lock);
  140. return cdev;
  141. }
  142. }
  143. read_unlock(&cnic_dev_lock);
  144. return NULL;
  145. }
  146. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  147. {
  148. atomic_inc(&ulp_ops->ref_count);
  149. }
  150. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  151. {
  152. atomic_dec(&ulp_ops->ref_count);
  153. }
  154. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  155. {
  156. struct cnic_local *cp = dev->cnic_priv;
  157. struct cnic_eth_dev *ethdev = cp->ethdev;
  158. struct drv_ctl_info info;
  159. struct drv_ctl_io *io = &info.data.io;
  160. memset(&info, 0, sizeof(struct drv_ctl_info));
  161. info.cmd = DRV_CTL_CTX_WR_CMD;
  162. io->cid_addr = cid_addr;
  163. io->offset = off;
  164. io->data = val;
  165. ethdev->drv_ctl(dev->netdev, &info);
  166. }
  167. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  168. {
  169. struct cnic_local *cp = dev->cnic_priv;
  170. struct cnic_eth_dev *ethdev = cp->ethdev;
  171. struct drv_ctl_info info;
  172. struct drv_ctl_io *io = &info.data.io;
  173. memset(&info, 0, sizeof(struct drv_ctl_info));
  174. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  175. io->offset = off;
  176. io->dma_addr = addr;
  177. ethdev->drv_ctl(dev->netdev, &info);
  178. }
  179. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  180. {
  181. struct cnic_local *cp = dev->cnic_priv;
  182. struct cnic_eth_dev *ethdev = cp->ethdev;
  183. struct drv_ctl_info info;
  184. struct drv_ctl_l2_ring *ring = &info.data.ring;
  185. memset(&info, 0, sizeof(struct drv_ctl_info));
  186. if (start)
  187. info.cmd = DRV_CTL_START_L2_CMD;
  188. else
  189. info.cmd = DRV_CTL_STOP_L2_CMD;
  190. ring->cid = cid;
  191. ring->client_id = cl_id;
  192. ethdev->drv_ctl(dev->netdev, &info);
  193. }
  194. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  195. {
  196. struct cnic_local *cp = dev->cnic_priv;
  197. struct cnic_eth_dev *ethdev = cp->ethdev;
  198. struct drv_ctl_info info;
  199. struct drv_ctl_io *io = &info.data.io;
  200. memset(&info, 0, sizeof(struct drv_ctl_info));
  201. info.cmd = DRV_CTL_IO_WR_CMD;
  202. io->offset = off;
  203. io->data = val;
  204. ethdev->drv_ctl(dev->netdev, &info);
  205. }
  206. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  207. {
  208. struct cnic_local *cp = dev->cnic_priv;
  209. struct cnic_eth_dev *ethdev = cp->ethdev;
  210. struct drv_ctl_info info;
  211. struct drv_ctl_io *io = &info.data.io;
  212. memset(&info, 0, sizeof(struct drv_ctl_info));
  213. info.cmd = DRV_CTL_IO_RD_CMD;
  214. io->offset = off;
  215. ethdev->drv_ctl(dev->netdev, &info);
  216. return io->data;
  217. }
  218. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg, int state)
  219. {
  220. struct cnic_local *cp = dev->cnic_priv;
  221. struct cnic_eth_dev *ethdev = cp->ethdev;
  222. struct drv_ctl_info info;
  223. struct fcoe_capabilities *fcoe_cap =
  224. &info.data.register_data.fcoe_features;
  225. memset(&info, 0, sizeof(struct drv_ctl_info));
  226. if (reg) {
  227. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  228. if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
  229. memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
  230. } else {
  231. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  232. }
  233. info.data.ulp_type = ulp_type;
  234. info.drv_state = state;
  235. ethdev->drv_ctl(dev->netdev, &info);
  236. }
  237. static int cnic_in_use(struct cnic_sock *csk)
  238. {
  239. return test_bit(SK_F_INUSE, &csk->flags);
  240. }
  241. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  242. {
  243. struct cnic_local *cp = dev->cnic_priv;
  244. struct cnic_eth_dev *ethdev = cp->ethdev;
  245. struct drv_ctl_info info;
  246. memset(&info, 0, sizeof(struct drv_ctl_info));
  247. info.cmd = cmd;
  248. info.data.credit.credit_count = count;
  249. ethdev->drv_ctl(dev->netdev, &info);
  250. }
  251. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  252. {
  253. u32 i;
  254. if (!cp->ctx_tbl)
  255. return -EINVAL;
  256. for (i = 0; i < cp->max_cid_space; i++) {
  257. if (cp->ctx_tbl[i].cid == cid) {
  258. *l5_cid = i;
  259. return 0;
  260. }
  261. }
  262. return -EINVAL;
  263. }
  264. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  265. struct cnic_sock *csk)
  266. {
  267. struct iscsi_path path_req;
  268. char *buf = NULL;
  269. u16 len = 0;
  270. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  271. struct cnic_ulp_ops *ulp_ops;
  272. struct cnic_uio_dev *udev = cp->udev;
  273. int rc = 0, retry = 0;
  274. if (!udev || udev->uio_dev == -1)
  275. return -ENODEV;
  276. if (csk) {
  277. len = sizeof(path_req);
  278. buf = (char *) &path_req;
  279. memset(&path_req, 0, len);
  280. msg_type = ISCSI_KEVENT_PATH_REQ;
  281. path_req.handle = (u64) csk->l5_cid;
  282. if (test_bit(SK_F_IPV6, &csk->flags)) {
  283. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  284. sizeof(struct in6_addr));
  285. path_req.ip_addr_len = 16;
  286. } else {
  287. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  288. sizeof(struct in_addr));
  289. path_req.ip_addr_len = 4;
  290. }
  291. path_req.vlan_id = csk->vlan_id;
  292. path_req.pmtu = csk->mtu;
  293. }
  294. while (retry < 3) {
  295. rc = 0;
  296. rcu_read_lock();
  297. ulp_ops = rcu_dereference(cp->ulp_ops[CNIC_ULP_ISCSI]);
  298. if (ulp_ops)
  299. rc = ulp_ops->iscsi_nl_send_msg(
  300. cp->ulp_handle[CNIC_ULP_ISCSI],
  301. msg_type, buf, len);
  302. rcu_read_unlock();
  303. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  304. break;
  305. msleep(100);
  306. retry++;
  307. }
  308. return rc;
  309. }
  310. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  311. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  312. char *buf, u16 len)
  313. {
  314. int rc = -EINVAL;
  315. switch (msg_type) {
  316. case ISCSI_UEVENT_PATH_UPDATE: {
  317. struct cnic_local *cp;
  318. u32 l5_cid;
  319. struct cnic_sock *csk;
  320. struct iscsi_path *path_resp;
  321. if (len < sizeof(*path_resp))
  322. break;
  323. path_resp = (struct iscsi_path *) buf;
  324. cp = dev->cnic_priv;
  325. l5_cid = (u32) path_resp->handle;
  326. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  327. break;
  328. if (!rcu_access_pointer(cp->ulp_ops[CNIC_ULP_L4])) {
  329. rc = -ENODEV;
  330. break;
  331. }
  332. csk = &cp->csk_tbl[l5_cid];
  333. csk_hold(csk);
  334. if (cnic_in_use(csk) &&
  335. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  336. csk->vlan_id = path_resp->vlan_id;
  337. memcpy(csk->ha, path_resp->mac_addr, ETH_ALEN);
  338. if (test_bit(SK_F_IPV6, &csk->flags))
  339. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  340. sizeof(struct in6_addr));
  341. else
  342. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  343. sizeof(struct in_addr));
  344. if (is_valid_ether_addr(csk->ha)) {
  345. cnic_cm_set_pg(csk);
  346. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  347. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  348. cnic_cm_upcall(cp, csk,
  349. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  350. clear_bit(SK_F_CONNECT_START, &csk->flags);
  351. }
  352. }
  353. csk_put(csk);
  354. rc = 0;
  355. }
  356. }
  357. return rc;
  358. }
  359. static int cnic_offld_prep(struct cnic_sock *csk)
  360. {
  361. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  362. return 0;
  363. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  364. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  365. return 0;
  366. }
  367. return 1;
  368. }
  369. static int cnic_close_prep(struct cnic_sock *csk)
  370. {
  371. clear_bit(SK_F_CONNECT_START, &csk->flags);
  372. smp_mb__after_atomic();
  373. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  374. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  375. msleep(1);
  376. return 1;
  377. }
  378. return 0;
  379. }
  380. static int cnic_abort_prep(struct cnic_sock *csk)
  381. {
  382. clear_bit(SK_F_CONNECT_START, &csk->flags);
  383. smp_mb__after_atomic();
  384. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  385. msleep(1);
  386. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  387. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  388. return 1;
  389. }
  390. return 0;
  391. }
  392. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  393. {
  394. struct cnic_dev *dev;
  395. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  396. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  397. return -EINVAL;
  398. }
  399. mutex_lock(&cnic_lock);
  400. if (cnic_ulp_tbl_prot(ulp_type)) {
  401. pr_err("%s: Type %d has already been registered\n",
  402. __func__, ulp_type);
  403. mutex_unlock(&cnic_lock);
  404. return -EBUSY;
  405. }
  406. read_lock(&cnic_dev_lock);
  407. list_for_each_entry(dev, &cnic_dev_list, list) {
  408. struct cnic_local *cp = dev->cnic_priv;
  409. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  410. }
  411. read_unlock(&cnic_dev_lock);
  412. atomic_set(&ulp_ops->ref_count, 0);
  413. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  414. mutex_unlock(&cnic_lock);
  415. /* Prevent race conditions with netdev_event */
  416. rtnl_lock();
  417. list_for_each_entry(dev, &cnic_dev_list, list) {
  418. struct cnic_local *cp = dev->cnic_priv;
  419. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  420. ulp_ops->cnic_init(dev);
  421. }
  422. rtnl_unlock();
  423. return 0;
  424. }
  425. int cnic_unregister_driver(int ulp_type)
  426. {
  427. struct cnic_dev *dev;
  428. struct cnic_ulp_ops *ulp_ops;
  429. int i = 0;
  430. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  431. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  432. return -EINVAL;
  433. }
  434. mutex_lock(&cnic_lock);
  435. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  436. if (!ulp_ops) {
  437. pr_err("%s: Type %d has not been registered\n",
  438. __func__, ulp_type);
  439. goto out_unlock;
  440. }
  441. read_lock(&cnic_dev_lock);
  442. list_for_each_entry(dev, &cnic_dev_list, list) {
  443. struct cnic_local *cp = dev->cnic_priv;
  444. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  445. pr_err("%s: Type %d still has devices registered\n",
  446. __func__, ulp_type);
  447. read_unlock(&cnic_dev_lock);
  448. goto out_unlock;
  449. }
  450. }
  451. read_unlock(&cnic_dev_lock);
  452. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  453. mutex_unlock(&cnic_lock);
  454. synchronize_rcu();
  455. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  456. msleep(100);
  457. i++;
  458. }
  459. if (atomic_read(&ulp_ops->ref_count) != 0)
  460. pr_warn("%s: Failed waiting for ref count to go to zero\n",
  461. __func__);
  462. return 0;
  463. out_unlock:
  464. mutex_unlock(&cnic_lock);
  465. return -EINVAL;
  466. }
  467. static int cnic_start_hw(struct cnic_dev *);
  468. static void cnic_stop_hw(struct cnic_dev *);
  469. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  470. void *ulp_ctx)
  471. {
  472. struct cnic_local *cp = dev->cnic_priv;
  473. struct cnic_ulp_ops *ulp_ops;
  474. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  475. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  476. return -EINVAL;
  477. }
  478. mutex_lock(&cnic_lock);
  479. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  480. pr_err("%s: Driver with type %d has not been registered\n",
  481. __func__, ulp_type);
  482. mutex_unlock(&cnic_lock);
  483. return -EAGAIN;
  484. }
  485. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  486. pr_err("%s: Type %d has already been registered to this device\n",
  487. __func__, ulp_type);
  488. mutex_unlock(&cnic_lock);
  489. return -EBUSY;
  490. }
  491. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  492. cp->ulp_handle[ulp_type] = ulp_ctx;
  493. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  494. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  495. cnic_hold(dev);
  496. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  497. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  498. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  499. mutex_unlock(&cnic_lock);
  500. cnic_ulp_ctl(dev, ulp_type, true, DRV_ACTIVE);
  501. return 0;
  502. }
  503. EXPORT_SYMBOL(cnic_register_driver);
  504. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  505. {
  506. struct cnic_local *cp = dev->cnic_priv;
  507. int i = 0;
  508. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  509. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  510. return -EINVAL;
  511. }
  512. if (ulp_type == CNIC_ULP_ISCSI)
  513. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  514. mutex_lock(&cnic_lock);
  515. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  516. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  517. cnic_put(dev);
  518. } else {
  519. pr_err("%s: device not registered to this ulp type %d\n",
  520. __func__, ulp_type);
  521. mutex_unlock(&cnic_lock);
  522. return -EINVAL;
  523. }
  524. mutex_unlock(&cnic_lock);
  525. if (ulp_type == CNIC_ULP_FCOE)
  526. dev->fcoe_cap = NULL;
  527. synchronize_rcu();
  528. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  529. i < 20) {
  530. msleep(100);
  531. i++;
  532. }
  533. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  534. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  535. if (test_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  536. cnic_ulp_ctl(dev, ulp_type, false, DRV_UNLOADED);
  537. else
  538. cnic_ulp_ctl(dev, ulp_type, false, DRV_INACTIVE);
  539. return 0;
  540. }
  541. EXPORT_SYMBOL(cnic_unregister_driver);
  542. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  543. u32 next)
  544. {
  545. id_tbl->start = start_id;
  546. id_tbl->max = size;
  547. id_tbl->next = next;
  548. spin_lock_init(&id_tbl->lock);
  549. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  550. if (!id_tbl->table)
  551. return -ENOMEM;
  552. return 0;
  553. }
  554. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  555. {
  556. kfree(id_tbl->table);
  557. id_tbl->table = NULL;
  558. }
  559. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  560. {
  561. int ret = -1;
  562. id -= id_tbl->start;
  563. if (id >= id_tbl->max)
  564. return ret;
  565. spin_lock(&id_tbl->lock);
  566. if (!test_bit(id, id_tbl->table)) {
  567. set_bit(id, id_tbl->table);
  568. ret = 0;
  569. }
  570. spin_unlock(&id_tbl->lock);
  571. return ret;
  572. }
  573. /* Returns -1 if not successful */
  574. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  575. {
  576. u32 id;
  577. spin_lock(&id_tbl->lock);
  578. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  579. if (id >= id_tbl->max) {
  580. id = -1;
  581. if (id_tbl->next != 0) {
  582. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  583. if (id >= id_tbl->next)
  584. id = -1;
  585. }
  586. }
  587. if (id < id_tbl->max) {
  588. set_bit(id, id_tbl->table);
  589. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  590. id += id_tbl->start;
  591. }
  592. spin_unlock(&id_tbl->lock);
  593. return id;
  594. }
  595. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  596. {
  597. if (id == -1)
  598. return;
  599. id -= id_tbl->start;
  600. if (id >= id_tbl->max)
  601. return;
  602. clear_bit(id, id_tbl->table);
  603. }
  604. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  605. {
  606. int i;
  607. if (!dma->pg_arr)
  608. return;
  609. for (i = 0; i < dma->num_pages; i++) {
  610. if (dma->pg_arr[i]) {
  611. dma_free_coherent(&dev->pcidev->dev, CNIC_PAGE_SIZE,
  612. dma->pg_arr[i], dma->pg_map_arr[i]);
  613. dma->pg_arr[i] = NULL;
  614. }
  615. }
  616. if (dma->pgtbl) {
  617. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  618. dma->pgtbl, dma->pgtbl_map);
  619. dma->pgtbl = NULL;
  620. }
  621. kfree(dma->pg_arr);
  622. dma->pg_arr = NULL;
  623. dma->num_pages = 0;
  624. }
  625. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  626. {
  627. int i;
  628. __le32 *page_table = (__le32 *) dma->pgtbl;
  629. for (i = 0; i < dma->num_pages; i++) {
  630. /* Each entry needs to be in big endian format. */
  631. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  632. page_table++;
  633. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  634. page_table++;
  635. }
  636. }
  637. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  638. {
  639. int i;
  640. __le32 *page_table = (__le32 *) dma->pgtbl;
  641. for (i = 0; i < dma->num_pages; i++) {
  642. /* Each entry needs to be in little endian format. */
  643. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  644. page_table++;
  645. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  646. page_table++;
  647. }
  648. }
  649. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  650. int pages, int use_pg_tbl)
  651. {
  652. int i, size;
  653. struct cnic_local *cp = dev->cnic_priv;
  654. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  655. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  656. if (dma->pg_arr == NULL)
  657. return -ENOMEM;
  658. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  659. dma->num_pages = pages;
  660. for (i = 0; i < pages; i++) {
  661. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  662. CNIC_PAGE_SIZE,
  663. &dma->pg_map_arr[i],
  664. GFP_ATOMIC);
  665. if (dma->pg_arr[i] == NULL)
  666. goto error;
  667. }
  668. if (!use_pg_tbl)
  669. return 0;
  670. dma->pgtbl_size = ((pages * 8) + CNIC_PAGE_SIZE - 1) &
  671. ~(CNIC_PAGE_SIZE - 1);
  672. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  673. &dma->pgtbl_map, GFP_ATOMIC);
  674. if (dma->pgtbl == NULL)
  675. goto error;
  676. cp->setup_pgtbl(dev, dma);
  677. return 0;
  678. error:
  679. cnic_free_dma(dev, dma);
  680. return -ENOMEM;
  681. }
  682. static void cnic_free_context(struct cnic_dev *dev)
  683. {
  684. struct cnic_local *cp = dev->cnic_priv;
  685. int i;
  686. for (i = 0; i < cp->ctx_blks; i++) {
  687. if (cp->ctx_arr[i].ctx) {
  688. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  689. cp->ctx_arr[i].ctx,
  690. cp->ctx_arr[i].mapping);
  691. cp->ctx_arr[i].ctx = NULL;
  692. }
  693. }
  694. }
  695. static void __cnic_free_uio_rings(struct cnic_uio_dev *udev)
  696. {
  697. if (udev->l2_buf) {
  698. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  699. udev->l2_buf, udev->l2_buf_map);
  700. udev->l2_buf = NULL;
  701. }
  702. if (udev->l2_ring) {
  703. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  704. udev->l2_ring, udev->l2_ring_map);
  705. udev->l2_ring = NULL;
  706. }
  707. }
  708. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  709. {
  710. uio_unregister_device(&udev->cnic_uinfo);
  711. __cnic_free_uio_rings(udev);
  712. pci_dev_put(udev->pdev);
  713. kfree(udev);
  714. }
  715. static void cnic_free_uio(struct cnic_uio_dev *udev)
  716. {
  717. if (!udev)
  718. return;
  719. write_lock(&cnic_dev_lock);
  720. list_del_init(&udev->list);
  721. write_unlock(&cnic_dev_lock);
  722. __cnic_free_uio(udev);
  723. }
  724. static void cnic_free_resc(struct cnic_dev *dev)
  725. {
  726. struct cnic_local *cp = dev->cnic_priv;
  727. struct cnic_uio_dev *udev = cp->udev;
  728. if (udev) {
  729. udev->dev = NULL;
  730. cp->udev = NULL;
  731. if (udev->uio_dev == -1)
  732. __cnic_free_uio_rings(udev);
  733. }
  734. cnic_free_context(dev);
  735. kfree(cp->ctx_arr);
  736. cp->ctx_arr = NULL;
  737. cp->ctx_blks = 0;
  738. cnic_free_dma(dev, &cp->gbl_buf_info);
  739. cnic_free_dma(dev, &cp->kwq_info);
  740. cnic_free_dma(dev, &cp->kwq_16_data_info);
  741. cnic_free_dma(dev, &cp->kcq2.dma);
  742. cnic_free_dma(dev, &cp->kcq1.dma);
  743. kfree(cp->iscsi_tbl);
  744. cp->iscsi_tbl = NULL;
  745. kfree(cp->ctx_tbl);
  746. cp->ctx_tbl = NULL;
  747. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  748. cnic_free_id_tbl(&cp->cid_tbl);
  749. }
  750. static int cnic_alloc_context(struct cnic_dev *dev)
  751. {
  752. struct cnic_local *cp = dev->cnic_priv;
  753. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  754. int i, k, arr_size;
  755. cp->ctx_blk_size = CNIC_PAGE_SIZE;
  756. cp->cids_per_blk = CNIC_PAGE_SIZE / 128;
  757. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  758. sizeof(struct cnic_ctx);
  759. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  760. if (cp->ctx_arr == NULL)
  761. return -ENOMEM;
  762. k = 0;
  763. for (i = 0; i < 2; i++) {
  764. u32 j, reg, off, lo, hi;
  765. if (i == 0)
  766. off = BNX2_PG_CTX_MAP;
  767. else
  768. off = BNX2_ISCSI_CTX_MAP;
  769. reg = cnic_reg_rd_ind(dev, off);
  770. lo = reg >> 16;
  771. hi = reg & 0xffff;
  772. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  773. cp->ctx_arr[k].cid = j;
  774. }
  775. cp->ctx_blks = k;
  776. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  777. cp->ctx_blks = 0;
  778. return -ENOMEM;
  779. }
  780. for (i = 0; i < cp->ctx_blks; i++) {
  781. cp->ctx_arr[i].ctx =
  782. dma_alloc_coherent(&dev->pcidev->dev,
  783. CNIC_PAGE_SIZE,
  784. &cp->ctx_arr[i].mapping,
  785. GFP_KERNEL);
  786. if (cp->ctx_arr[i].ctx == NULL)
  787. return -ENOMEM;
  788. }
  789. }
  790. return 0;
  791. }
  792. static u16 cnic_bnx2_next_idx(u16 idx)
  793. {
  794. return idx + 1;
  795. }
  796. static u16 cnic_bnx2_hw_idx(u16 idx)
  797. {
  798. return idx;
  799. }
  800. static u16 cnic_bnx2x_next_idx(u16 idx)
  801. {
  802. idx++;
  803. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  804. idx++;
  805. return idx;
  806. }
  807. static u16 cnic_bnx2x_hw_idx(u16 idx)
  808. {
  809. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  810. idx++;
  811. return idx;
  812. }
  813. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  814. bool use_pg_tbl)
  815. {
  816. int err, i, use_page_tbl = 0;
  817. struct kcqe **kcq;
  818. if (use_pg_tbl)
  819. use_page_tbl = 1;
  820. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  821. if (err)
  822. return err;
  823. kcq = (struct kcqe **) info->dma.pg_arr;
  824. info->kcq = kcq;
  825. info->next_idx = cnic_bnx2_next_idx;
  826. info->hw_idx = cnic_bnx2_hw_idx;
  827. if (use_pg_tbl)
  828. return 0;
  829. info->next_idx = cnic_bnx2x_next_idx;
  830. info->hw_idx = cnic_bnx2x_hw_idx;
  831. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  832. struct bnx2x_bd_chain_next *next =
  833. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  834. int j = i + 1;
  835. if (j >= KCQ_PAGE_CNT)
  836. j = 0;
  837. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  838. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  839. }
  840. return 0;
  841. }
  842. static int __cnic_alloc_uio_rings(struct cnic_uio_dev *udev, int pages)
  843. {
  844. struct cnic_local *cp = udev->dev->cnic_priv;
  845. if (udev->l2_ring)
  846. return 0;
  847. udev->l2_ring_size = pages * CNIC_PAGE_SIZE;
  848. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  849. &udev->l2_ring_map,
  850. GFP_KERNEL | __GFP_COMP);
  851. if (!udev->l2_ring)
  852. return -ENOMEM;
  853. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  854. udev->l2_buf_size = CNIC_PAGE_ALIGN(udev->l2_buf_size);
  855. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  856. &udev->l2_buf_map,
  857. GFP_KERNEL | __GFP_COMP);
  858. if (!udev->l2_buf) {
  859. __cnic_free_uio_rings(udev);
  860. return -ENOMEM;
  861. }
  862. return 0;
  863. }
  864. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  865. {
  866. struct cnic_local *cp = dev->cnic_priv;
  867. struct cnic_uio_dev *udev;
  868. list_for_each_entry(udev, &cnic_udev_list, list) {
  869. if (udev->pdev == dev->pcidev) {
  870. udev->dev = dev;
  871. if (__cnic_alloc_uio_rings(udev, pages)) {
  872. udev->dev = NULL;
  873. return -ENOMEM;
  874. }
  875. cp->udev = udev;
  876. return 0;
  877. }
  878. }
  879. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  880. if (!udev)
  881. return -ENOMEM;
  882. udev->uio_dev = -1;
  883. udev->dev = dev;
  884. udev->pdev = dev->pcidev;
  885. if (__cnic_alloc_uio_rings(udev, pages))
  886. goto err_udev;
  887. list_add(&udev->list, &cnic_udev_list);
  888. pci_dev_get(udev->pdev);
  889. cp->udev = udev;
  890. return 0;
  891. err_udev:
  892. kfree(udev);
  893. return -ENOMEM;
  894. }
  895. static int cnic_init_uio(struct cnic_dev *dev)
  896. {
  897. struct cnic_local *cp = dev->cnic_priv;
  898. struct cnic_uio_dev *udev = cp->udev;
  899. struct uio_info *uinfo;
  900. int ret = 0;
  901. if (!udev)
  902. return -ENOMEM;
  903. uinfo = &udev->cnic_uinfo;
  904. uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
  905. uinfo->mem[0].internal_addr = dev->regview;
  906. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  907. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  908. uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
  909. TX_MAX_TSS_RINGS + 1);
  910. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  911. CNIC_PAGE_MASK;
  912. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  913. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  914. else
  915. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  916. uinfo->name = "bnx2_cnic";
  917. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  918. uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
  919. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  920. CNIC_PAGE_MASK;
  921. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  922. uinfo->name = "bnx2x_cnic";
  923. }
  924. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  925. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  926. uinfo->mem[2].size = udev->l2_ring_size;
  927. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  928. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  929. uinfo->mem[3].size = udev->l2_buf_size;
  930. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  931. uinfo->version = CNIC_MODULE_VERSION;
  932. uinfo->irq = UIO_IRQ_CUSTOM;
  933. uinfo->open = cnic_uio_open;
  934. uinfo->release = cnic_uio_close;
  935. if (udev->uio_dev == -1) {
  936. if (!uinfo->priv) {
  937. uinfo->priv = udev;
  938. ret = uio_register_device(&udev->pdev->dev, uinfo);
  939. }
  940. } else {
  941. cnic_init_rings(dev);
  942. }
  943. return ret;
  944. }
  945. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  946. {
  947. struct cnic_local *cp = dev->cnic_priv;
  948. int ret;
  949. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  950. if (ret)
  951. goto error;
  952. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  953. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  954. if (ret)
  955. goto error;
  956. ret = cnic_alloc_context(dev);
  957. if (ret)
  958. goto error;
  959. ret = cnic_alloc_uio_rings(dev, 2);
  960. if (ret)
  961. goto error;
  962. ret = cnic_init_uio(dev);
  963. if (ret)
  964. goto error;
  965. return 0;
  966. error:
  967. cnic_free_resc(dev);
  968. return ret;
  969. }
  970. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  971. {
  972. struct cnic_local *cp = dev->cnic_priv;
  973. struct bnx2x *bp = netdev_priv(dev->netdev);
  974. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  975. int total_mem, blks, i;
  976. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  977. blks = total_mem / ctx_blk_size;
  978. if (total_mem % ctx_blk_size)
  979. blks++;
  980. if (blks > cp->ethdev->ctx_tbl_len)
  981. return -ENOMEM;
  982. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  983. if (cp->ctx_arr == NULL)
  984. return -ENOMEM;
  985. cp->ctx_blks = blks;
  986. cp->ctx_blk_size = ctx_blk_size;
  987. if (!CHIP_IS_E1(bp))
  988. cp->ctx_align = 0;
  989. else
  990. cp->ctx_align = ctx_blk_size;
  991. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  992. for (i = 0; i < blks; i++) {
  993. cp->ctx_arr[i].ctx =
  994. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  995. &cp->ctx_arr[i].mapping,
  996. GFP_KERNEL);
  997. if (cp->ctx_arr[i].ctx == NULL)
  998. return -ENOMEM;
  999. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  1000. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  1001. cnic_free_context(dev);
  1002. cp->ctx_blk_size += cp->ctx_align;
  1003. i = -1;
  1004. continue;
  1005. }
  1006. }
  1007. }
  1008. return 0;
  1009. }
  1010. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  1011. {
  1012. struct cnic_local *cp = dev->cnic_priv;
  1013. struct bnx2x *bp = netdev_priv(dev->netdev);
  1014. struct cnic_eth_dev *ethdev = cp->ethdev;
  1015. u32 start_cid = ethdev->starting_cid;
  1016. int i, j, n, ret, pages;
  1017. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  1018. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  1019. cp->iscsi_start_cid = start_cid;
  1020. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  1021. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  1022. cp->max_cid_space += dev->max_fcoe_conn;
  1023. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  1024. if (!cp->fcoe_init_cid)
  1025. cp->fcoe_init_cid = 0x10;
  1026. }
  1027. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  1028. GFP_KERNEL);
  1029. if (!cp->iscsi_tbl)
  1030. goto error;
  1031. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  1032. cp->max_cid_space, GFP_KERNEL);
  1033. if (!cp->ctx_tbl)
  1034. goto error;
  1035. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  1036. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  1037. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1038. }
  1039. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1040. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1041. pages = CNIC_PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1042. CNIC_PAGE_SIZE;
  1043. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1044. if (ret)
  1045. return -ENOMEM;
  1046. n = CNIC_PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1047. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1048. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1049. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1050. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1051. off;
  1052. if ((i % n) == (n - 1))
  1053. j++;
  1054. }
  1055. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1056. if (ret)
  1057. goto error;
  1058. if (CNIC_SUPPORTS_FCOE(bp)) {
  1059. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1060. if (ret)
  1061. goto error;
  1062. }
  1063. pages = CNIC_PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / CNIC_PAGE_SIZE;
  1064. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1065. if (ret)
  1066. goto error;
  1067. ret = cnic_alloc_bnx2x_context(dev);
  1068. if (ret)
  1069. goto error;
  1070. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  1071. return 0;
  1072. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1073. cp->l2_rx_ring_size = 15;
  1074. ret = cnic_alloc_uio_rings(dev, 4);
  1075. if (ret)
  1076. goto error;
  1077. ret = cnic_init_uio(dev);
  1078. if (ret)
  1079. goto error;
  1080. return 0;
  1081. error:
  1082. cnic_free_resc(dev);
  1083. return -ENOMEM;
  1084. }
  1085. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1086. {
  1087. return cp->max_kwq_idx -
  1088. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1089. }
  1090. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1091. u32 num_wqes)
  1092. {
  1093. struct cnic_local *cp = dev->cnic_priv;
  1094. struct kwqe *prod_qe;
  1095. u16 prod, sw_prod, i;
  1096. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1097. return -EAGAIN; /* bnx2 is down */
  1098. spin_lock_bh(&cp->cnic_ulp_lock);
  1099. if (num_wqes > cnic_kwq_avail(cp) &&
  1100. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1101. spin_unlock_bh(&cp->cnic_ulp_lock);
  1102. return -EAGAIN;
  1103. }
  1104. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1105. prod = cp->kwq_prod_idx;
  1106. sw_prod = prod & MAX_KWQ_IDX;
  1107. for (i = 0; i < num_wqes; i++) {
  1108. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1109. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1110. prod++;
  1111. sw_prod = prod & MAX_KWQ_IDX;
  1112. }
  1113. cp->kwq_prod_idx = prod;
  1114. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1115. spin_unlock_bh(&cp->cnic_ulp_lock);
  1116. return 0;
  1117. }
  1118. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1119. union l5cm_specific_data *l5_data)
  1120. {
  1121. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1122. dma_addr_t map;
  1123. map = ctx->kwqe_data_mapping;
  1124. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1125. l5_data->phy_address.hi = (u64) map >> 32;
  1126. return ctx->kwqe_data;
  1127. }
  1128. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1129. u32 type, union l5cm_specific_data *l5_data)
  1130. {
  1131. struct cnic_local *cp = dev->cnic_priv;
  1132. struct bnx2x *bp = netdev_priv(dev->netdev);
  1133. struct l5cm_spe kwqe;
  1134. struct kwqe_16 *kwq[1];
  1135. u16 type_16;
  1136. int ret;
  1137. kwqe.hdr.conn_and_cmd_data =
  1138. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1139. BNX2X_HW_CID(bp, cid)));
  1140. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1141. type_16 |= (bp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1142. SPE_HDR_FUNCTION_ID;
  1143. kwqe.hdr.type = cpu_to_le16(type_16);
  1144. kwqe.hdr.reserved1 = 0;
  1145. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1146. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1147. kwq[0] = (struct kwqe_16 *) &kwqe;
  1148. spin_lock_bh(&cp->cnic_ulp_lock);
  1149. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1150. spin_unlock_bh(&cp->cnic_ulp_lock);
  1151. if (ret == 1)
  1152. return 0;
  1153. return ret;
  1154. }
  1155. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1156. struct kcqe *cqes[], u32 num_cqes)
  1157. {
  1158. struct cnic_local *cp = dev->cnic_priv;
  1159. struct cnic_ulp_ops *ulp_ops;
  1160. rcu_read_lock();
  1161. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1162. if (likely(ulp_ops)) {
  1163. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1164. cqes, num_cqes);
  1165. }
  1166. rcu_read_unlock();
  1167. }
  1168. static void cnic_bnx2x_set_tcp_options(struct cnic_dev *dev, int time_stamps,
  1169. int en_tcp_dack)
  1170. {
  1171. struct bnx2x *bp = netdev_priv(dev->netdev);
  1172. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1173. u16 tstorm_flags = 0;
  1174. if (time_stamps) {
  1175. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1176. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1177. }
  1178. if (en_tcp_dack)
  1179. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN;
  1180. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1181. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), xstorm_flags);
  1182. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1183. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), tstorm_flags);
  1184. }
  1185. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1186. {
  1187. struct cnic_local *cp = dev->cnic_priv;
  1188. struct bnx2x *bp = netdev_priv(dev->netdev);
  1189. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1190. int hq_bds, pages;
  1191. u32 pfid = bp->pfid;
  1192. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1193. cp->num_ccells = req1->num_ccells_per_conn;
  1194. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1195. cp->num_iscsi_tasks;
  1196. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1197. BNX2X_ISCSI_R2TQE_SIZE;
  1198. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1199. pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
  1200. hq_bds = pages * (CNIC_PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1201. cp->num_cqs = req1->num_cqs;
  1202. if (!dev->max_iscsi_conn)
  1203. return 0;
  1204. /* init Tstorm RAM */
  1205. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1206. req1->rq_num_wqes);
  1207. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1208. CNIC_PAGE_SIZE);
  1209. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1210. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1211. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1212. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1213. req1->num_tasks_per_conn);
  1214. /* init Ustorm RAM */
  1215. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1216. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1217. req1->rq_buffer_size);
  1218. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1219. CNIC_PAGE_SIZE);
  1220. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1221. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1222. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1223. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1224. req1->num_tasks_per_conn);
  1225. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1226. req1->rq_num_wqes);
  1227. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1228. req1->cq_num_wqes);
  1229. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1230. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1231. /* init Xstorm RAM */
  1232. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1233. CNIC_PAGE_SIZE);
  1234. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1235. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1236. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1237. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1238. req1->num_tasks_per_conn);
  1239. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1240. hq_bds);
  1241. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1242. req1->num_tasks_per_conn);
  1243. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1244. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1245. /* init Cstorm RAM */
  1246. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1247. CNIC_PAGE_SIZE);
  1248. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1249. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1250. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1251. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1252. req1->num_tasks_per_conn);
  1253. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1254. req1->cq_num_wqes);
  1255. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1256. hq_bds);
  1257. cnic_bnx2x_set_tcp_options(dev,
  1258. req1->flags & ISCSI_KWQE_INIT1_TIME_STAMPS_ENABLE,
  1259. req1->flags & ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE);
  1260. return 0;
  1261. }
  1262. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1263. {
  1264. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1265. struct bnx2x *bp = netdev_priv(dev->netdev);
  1266. u32 pfid = bp->pfid;
  1267. struct iscsi_kcqe kcqe;
  1268. struct kcqe *cqes[1];
  1269. memset(&kcqe, 0, sizeof(kcqe));
  1270. if (!dev->max_iscsi_conn) {
  1271. kcqe.completion_status =
  1272. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1273. goto done;
  1274. }
  1275. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1276. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1277. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1278. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1279. req2->error_bit_map[1]);
  1280. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1281. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1282. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1283. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1284. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1285. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1286. req2->error_bit_map[1]);
  1287. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1288. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1289. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1290. done:
  1291. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1292. cqes[0] = (struct kcqe *) &kcqe;
  1293. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1294. return 0;
  1295. }
  1296. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1297. {
  1298. struct cnic_local *cp = dev->cnic_priv;
  1299. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1300. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1301. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1302. cnic_free_dma(dev, &iscsi->hq_info);
  1303. cnic_free_dma(dev, &iscsi->r2tq_info);
  1304. cnic_free_dma(dev, &iscsi->task_array_info);
  1305. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1306. } else {
  1307. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1308. }
  1309. ctx->cid = 0;
  1310. }
  1311. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1312. {
  1313. u32 cid;
  1314. int ret, pages;
  1315. struct cnic_local *cp = dev->cnic_priv;
  1316. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1317. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1318. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1319. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1320. if (cid == -1) {
  1321. ret = -ENOMEM;
  1322. goto error;
  1323. }
  1324. ctx->cid = cid;
  1325. return 0;
  1326. }
  1327. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1328. if (cid == -1) {
  1329. ret = -ENOMEM;
  1330. goto error;
  1331. }
  1332. ctx->cid = cid;
  1333. pages = CNIC_PAGE_ALIGN(cp->task_array_size) / CNIC_PAGE_SIZE;
  1334. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1335. if (ret)
  1336. goto error;
  1337. pages = CNIC_PAGE_ALIGN(cp->r2tq_size) / CNIC_PAGE_SIZE;
  1338. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1339. if (ret)
  1340. goto error;
  1341. pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
  1342. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1343. if (ret)
  1344. goto error;
  1345. return 0;
  1346. error:
  1347. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1348. return ret;
  1349. }
  1350. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1351. struct regpair *ctx_addr)
  1352. {
  1353. struct cnic_local *cp = dev->cnic_priv;
  1354. struct cnic_eth_dev *ethdev = cp->ethdev;
  1355. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1356. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1357. unsigned long align_off = 0;
  1358. dma_addr_t ctx_map;
  1359. void *ctx;
  1360. if (cp->ctx_align) {
  1361. unsigned long mask = cp->ctx_align - 1;
  1362. if (cp->ctx_arr[blk].mapping & mask)
  1363. align_off = cp->ctx_align -
  1364. (cp->ctx_arr[blk].mapping & mask);
  1365. }
  1366. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1367. (off * BNX2X_CONTEXT_MEM_SIZE);
  1368. ctx = cp->ctx_arr[blk].ctx + align_off +
  1369. (off * BNX2X_CONTEXT_MEM_SIZE);
  1370. if (init)
  1371. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1372. ctx_addr->lo = ctx_map & 0xffffffff;
  1373. ctx_addr->hi = (u64) ctx_map >> 32;
  1374. return ctx;
  1375. }
  1376. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1377. u32 num)
  1378. {
  1379. struct cnic_local *cp = dev->cnic_priv;
  1380. struct bnx2x *bp = netdev_priv(dev->netdev);
  1381. struct iscsi_kwqe_conn_offload1 *req1 =
  1382. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1383. struct iscsi_kwqe_conn_offload2 *req2 =
  1384. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1385. struct iscsi_kwqe_conn_offload3 *req3;
  1386. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1387. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1388. u32 cid = ctx->cid;
  1389. u32 hw_cid = BNX2X_HW_CID(bp, cid);
  1390. struct iscsi_context *ictx;
  1391. struct regpair context_addr;
  1392. int i, j, n = 2, n_max;
  1393. u8 port = BP_PORT(bp);
  1394. ctx->ctx_flags = 0;
  1395. if (!req2->num_additional_wqes)
  1396. return -EINVAL;
  1397. n_max = req2->num_additional_wqes + 2;
  1398. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1399. if (ictx == NULL)
  1400. return -ENOMEM;
  1401. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1402. ictx->xstorm_ag_context.hq_prod = 1;
  1403. ictx->xstorm_st_context.iscsi.first_burst_length =
  1404. ISCSI_DEF_FIRST_BURST_LEN;
  1405. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1406. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1407. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1408. req1->sq_page_table_addr_lo;
  1409. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1410. req1->sq_page_table_addr_hi;
  1411. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1412. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1413. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1414. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1415. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1416. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1417. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1418. iscsi->hq_info.pgtbl[0];
  1419. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1420. iscsi->hq_info.pgtbl[1];
  1421. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1422. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1423. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1424. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1425. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1426. iscsi->r2tq_info.pgtbl[0];
  1427. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1428. iscsi->r2tq_info.pgtbl[1];
  1429. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1430. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1431. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1432. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1433. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1434. BNX2X_ISCSI_PBL_NOT_CACHED;
  1435. ictx->xstorm_st_context.iscsi.flags.flags |=
  1436. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1437. ictx->xstorm_st_context.iscsi.flags.flags |=
  1438. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1439. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1440. ETH_P_8021Q;
  1441. if (BNX2X_CHIP_IS_E2_PLUS(bp) &&
  1442. bp->common.chip_port_mode == CHIP_2_PORT_MODE) {
  1443. port = 0;
  1444. }
  1445. ictx->xstorm_st_context.common.flags =
  1446. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1447. ictx->xstorm_st_context.common.flags =
  1448. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1449. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1450. /* TSTORM requires the base address of RQ DB & not PTE */
  1451. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1452. req2->rq_page_table_addr_lo & CNIC_PAGE_MASK;
  1453. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1454. req2->rq_page_table_addr_hi;
  1455. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1456. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1457. ictx->tstorm_st_context.tcp.flags2 |=
  1458. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1459. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1460. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1461. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1462. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1463. req2->rq_page_table_addr_lo;
  1464. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1465. req2->rq_page_table_addr_hi;
  1466. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1467. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1468. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1469. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1470. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1471. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1472. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1473. iscsi->r2tq_info.pgtbl[0];
  1474. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1475. iscsi->r2tq_info.pgtbl[1];
  1476. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1477. req1->cq_page_table_addr_lo;
  1478. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1479. req1->cq_page_table_addr_hi;
  1480. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1481. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1482. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1483. ictx->ustorm_st_context.task_pbe_cache_index =
  1484. BNX2X_ISCSI_PBL_NOT_CACHED;
  1485. ictx->ustorm_st_context.task_pdu_cache_index =
  1486. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1487. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1488. if (j == 3) {
  1489. if (n >= n_max)
  1490. break;
  1491. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1492. j = 0;
  1493. }
  1494. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1495. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1496. req3->qp_first_pte[j].hi;
  1497. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1498. req3->qp_first_pte[j].lo;
  1499. }
  1500. ictx->ustorm_st_context.task_pbl_base.lo =
  1501. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1502. ictx->ustorm_st_context.task_pbl_base.hi =
  1503. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1504. ictx->ustorm_st_context.tce_phy_addr.lo =
  1505. iscsi->task_array_info.pgtbl[0];
  1506. ictx->ustorm_st_context.tce_phy_addr.hi =
  1507. iscsi->task_array_info.pgtbl[1];
  1508. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1509. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1510. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1511. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1512. ISCSI_DEF_MAX_BURST_LEN;
  1513. ictx->ustorm_st_context.negotiated_rx |=
  1514. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1515. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1516. ictx->cstorm_st_context.hq_pbl_base.lo =
  1517. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1518. ictx->cstorm_st_context.hq_pbl_base.hi =
  1519. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1520. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1521. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1522. ictx->cstorm_st_context.task_pbl_base.lo =
  1523. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1524. ictx->cstorm_st_context.task_pbl_base.hi =
  1525. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1526. /* CSTORM and USTORM initialization is different, CSTORM requires
  1527. * CQ DB base & not PTE addr */
  1528. ictx->cstorm_st_context.cq_db_base.lo =
  1529. req1->cq_page_table_addr_lo & CNIC_PAGE_MASK;
  1530. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1531. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1532. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1533. for (i = 0; i < cp->num_cqs; i++) {
  1534. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1535. ISCSI_INITIAL_SN;
  1536. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1537. ISCSI_INITIAL_SN;
  1538. }
  1539. ictx->xstorm_ag_context.cdu_reserved =
  1540. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1541. ISCSI_CONNECTION_TYPE);
  1542. ictx->ustorm_ag_context.cdu_usage =
  1543. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1544. ISCSI_CONNECTION_TYPE);
  1545. return 0;
  1546. }
  1547. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1548. u32 num, int *work)
  1549. {
  1550. struct iscsi_kwqe_conn_offload1 *req1;
  1551. struct iscsi_kwqe_conn_offload2 *req2;
  1552. struct cnic_local *cp = dev->cnic_priv;
  1553. struct bnx2x *bp = netdev_priv(dev->netdev);
  1554. struct cnic_context *ctx;
  1555. struct iscsi_kcqe kcqe;
  1556. struct kcqe *cqes[1];
  1557. u32 l5_cid;
  1558. int ret = 0;
  1559. if (num < 2) {
  1560. *work = num;
  1561. return -EINVAL;
  1562. }
  1563. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1564. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1565. if ((num - 2) < req2->num_additional_wqes) {
  1566. *work = num;
  1567. return -EINVAL;
  1568. }
  1569. *work = 2 + req2->num_additional_wqes;
  1570. l5_cid = req1->iscsi_conn_id;
  1571. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1572. return -EINVAL;
  1573. memset(&kcqe, 0, sizeof(kcqe));
  1574. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1575. kcqe.iscsi_conn_id = l5_cid;
  1576. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1577. ctx = &cp->ctx_tbl[l5_cid];
  1578. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1579. kcqe.completion_status =
  1580. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1581. goto done;
  1582. }
  1583. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1584. atomic_dec(&cp->iscsi_conn);
  1585. goto done;
  1586. }
  1587. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1588. if (ret) {
  1589. atomic_dec(&cp->iscsi_conn);
  1590. ret = 0;
  1591. goto done;
  1592. }
  1593. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1594. if (ret < 0) {
  1595. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1596. atomic_dec(&cp->iscsi_conn);
  1597. goto done;
  1598. }
  1599. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1600. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(bp, cp->ctx_tbl[l5_cid].cid);
  1601. done:
  1602. cqes[0] = (struct kcqe *) &kcqe;
  1603. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1604. return 0;
  1605. }
  1606. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1607. {
  1608. struct cnic_local *cp = dev->cnic_priv;
  1609. struct iscsi_kwqe_conn_update *req =
  1610. (struct iscsi_kwqe_conn_update *) kwqe;
  1611. void *data;
  1612. union l5cm_specific_data l5_data;
  1613. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1614. int ret;
  1615. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1616. return -EINVAL;
  1617. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1618. if (!data)
  1619. return -ENOMEM;
  1620. memcpy(data, kwqe, sizeof(struct kwqe));
  1621. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1622. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1623. return ret;
  1624. }
  1625. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1626. {
  1627. struct cnic_local *cp = dev->cnic_priv;
  1628. struct bnx2x *bp = netdev_priv(dev->netdev);
  1629. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1630. union l5cm_specific_data l5_data;
  1631. int ret;
  1632. u32 hw_cid;
  1633. init_waitqueue_head(&ctx->waitq);
  1634. ctx->wait_cond = 0;
  1635. memset(&l5_data, 0, sizeof(l5_data));
  1636. hw_cid = BNX2X_HW_CID(bp, ctx->cid);
  1637. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1638. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1639. if (ret == 0) {
  1640. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1641. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1642. return -EBUSY;
  1643. }
  1644. return 0;
  1645. }
  1646. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1647. {
  1648. struct cnic_local *cp = dev->cnic_priv;
  1649. struct iscsi_kwqe_conn_destroy *req =
  1650. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1651. u32 l5_cid = req->reserved0;
  1652. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1653. int ret = 0;
  1654. struct iscsi_kcqe kcqe;
  1655. struct kcqe *cqes[1];
  1656. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1657. goto skip_cfc_delete;
  1658. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1659. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1660. if (delta > (2 * HZ))
  1661. delta = 0;
  1662. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1663. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1664. goto destroy_reply;
  1665. }
  1666. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1667. skip_cfc_delete:
  1668. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1669. if (!ret) {
  1670. atomic_dec(&cp->iscsi_conn);
  1671. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1672. }
  1673. destroy_reply:
  1674. memset(&kcqe, 0, sizeof(kcqe));
  1675. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1676. kcqe.iscsi_conn_id = l5_cid;
  1677. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1678. kcqe.iscsi_conn_context_id = req->context_id;
  1679. cqes[0] = (struct kcqe *) &kcqe;
  1680. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1681. return 0;
  1682. }
  1683. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1684. struct l4_kwq_connect_req1 *kwqe1,
  1685. struct l4_kwq_connect_req3 *kwqe3,
  1686. struct l5cm_active_conn_buffer *conn_buf)
  1687. {
  1688. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1689. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1690. &conn_buf->xstorm_conn_buffer;
  1691. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1692. &conn_buf->tstorm_conn_buffer;
  1693. struct regpair context_addr;
  1694. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1695. struct in6_addr src_ip, dst_ip;
  1696. int i;
  1697. u32 *addrp;
  1698. addrp = (u32 *) &conn_addr->local_ip_addr;
  1699. for (i = 0; i < 4; i++, addrp++)
  1700. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1701. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1702. for (i = 0; i < 4; i++, addrp++)
  1703. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1704. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1705. xstorm_buf->context_addr.hi = context_addr.hi;
  1706. xstorm_buf->context_addr.lo = context_addr.lo;
  1707. xstorm_buf->mss = 0xffff;
  1708. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1709. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1710. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1711. xstorm_buf->pseudo_header_checksum =
  1712. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1713. if (kwqe3->ka_timeout) {
  1714. tstorm_buf->ka_enable = 1;
  1715. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1716. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1717. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1718. }
  1719. tstorm_buf->max_rt_time = 0xffffffff;
  1720. }
  1721. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1722. {
  1723. struct bnx2x *bp = netdev_priv(dev->netdev);
  1724. u32 pfid = bp->pfid;
  1725. u8 *mac = dev->mac_addr;
  1726. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1727. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1728. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1729. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1730. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1731. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1732. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1733. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1734. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1735. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1736. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1737. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1738. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1739. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1740. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1741. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1742. mac[4]);
  1743. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1744. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1745. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1746. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1747. mac[2]);
  1748. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1749. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1750. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1751. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1752. mac[0]);
  1753. }
  1754. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1755. u32 num, int *work)
  1756. {
  1757. struct cnic_local *cp = dev->cnic_priv;
  1758. struct bnx2x *bp = netdev_priv(dev->netdev);
  1759. struct l4_kwq_connect_req1 *kwqe1 =
  1760. (struct l4_kwq_connect_req1 *) wqes[0];
  1761. struct l4_kwq_connect_req3 *kwqe3;
  1762. struct l5cm_active_conn_buffer *conn_buf;
  1763. struct l5cm_conn_addr_params *conn_addr;
  1764. union l5cm_specific_data l5_data;
  1765. u32 l5_cid = kwqe1->pg_cid;
  1766. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1767. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1768. int ret;
  1769. if (num < 2) {
  1770. *work = num;
  1771. return -EINVAL;
  1772. }
  1773. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1774. *work = 3;
  1775. else
  1776. *work = 2;
  1777. if (num < *work) {
  1778. *work = num;
  1779. return -EINVAL;
  1780. }
  1781. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1782. netdev_err(dev->netdev, "conn_buf size too big\n");
  1783. return -ENOMEM;
  1784. }
  1785. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1786. if (!conn_buf)
  1787. return -ENOMEM;
  1788. memset(conn_buf, 0, sizeof(*conn_buf));
  1789. conn_addr = &conn_buf->conn_addr_buf;
  1790. conn_addr->remote_addr_0 = csk->ha[0];
  1791. conn_addr->remote_addr_1 = csk->ha[1];
  1792. conn_addr->remote_addr_2 = csk->ha[2];
  1793. conn_addr->remote_addr_3 = csk->ha[3];
  1794. conn_addr->remote_addr_4 = csk->ha[4];
  1795. conn_addr->remote_addr_5 = csk->ha[5];
  1796. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1797. struct l4_kwq_connect_req2 *kwqe2 =
  1798. (struct l4_kwq_connect_req2 *) wqes[1];
  1799. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1800. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1801. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1802. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1803. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1804. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1805. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1806. }
  1807. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1808. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1809. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1810. conn_addr->local_tcp_port = kwqe1->src_port;
  1811. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1812. conn_addr->pmtu = kwqe3->pmtu;
  1813. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1814. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1815. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(bp->pfid), csk->vlan_id);
  1816. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1817. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1818. if (!ret)
  1819. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1820. return ret;
  1821. }
  1822. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1823. {
  1824. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1825. union l5cm_specific_data l5_data;
  1826. int ret;
  1827. memset(&l5_data, 0, sizeof(l5_data));
  1828. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1829. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1830. return ret;
  1831. }
  1832. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1833. {
  1834. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1835. union l5cm_specific_data l5_data;
  1836. int ret;
  1837. memset(&l5_data, 0, sizeof(l5_data));
  1838. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1839. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1840. return ret;
  1841. }
  1842. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1843. {
  1844. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1845. struct l4_kcq kcqe;
  1846. struct kcqe *cqes[1];
  1847. memset(&kcqe, 0, sizeof(kcqe));
  1848. kcqe.pg_host_opaque = req->host_opaque;
  1849. kcqe.pg_cid = req->host_opaque;
  1850. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1851. cqes[0] = (struct kcqe *) &kcqe;
  1852. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1853. return 0;
  1854. }
  1855. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1856. {
  1857. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1858. struct l4_kcq kcqe;
  1859. struct kcqe *cqes[1];
  1860. memset(&kcqe, 0, sizeof(kcqe));
  1861. kcqe.pg_host_opaque = req->pg_host_opaque;
  1862. kcqe.pg_cid = req->pg_cid;
  1863. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1864. cqes[0] = (struct kcqe *) &kcqe;
  1865. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1866. return 0;
  1867. }
  1868. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1869. {
  1870. struct fcoe_kwqe_stat *req;
  1871. struct fcoe_stat_ramrod_params *fcoe_stat;
  1872. union l5cm_specific_data l5_data;
  1873. struct cnic_local *cp = dev->cnic_priv;
  1874. struct bnx2x *bp = netdev_priv(dev->netdev);
  1875. int ret;
  1876. u32 cid;
  1877. req = (struct fcoe_kwqe_stat *) kwqe;
  1878. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  1879. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1880. if (!fcoe_stat)
  1881. return -ENOMEM;
  1882. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1883. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1884. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1885. FCOE_CONNECTION_TYPE, &l5_data);
  1886. return ret;
  1887. }
  1888. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1889. u32 num, int *work)
  1890. {
  1891. int ret;
  1892. struct cnic_local *cp = dev->cnic_priv;
  1893. struct bnx2x *bp = netdev_priv(dev->netdev);
  1894. u32 cid;
  1895. struct fcoe_init_ramrod_params *fcoe_init;
  1896. struct fcoe_kwqe_init1 *req1;
  1897. struct fcoe_kwqe_init2 *req2;
  1898. struct fcoe_kwqe_init3 *req3;
  1899. union l5cm_specific_data l5_data;
  1900. if (num < 3) {
  1901. *work = num;
  1902. return -EINVAL;
  1903. }
  1904. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1905. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1906. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1907. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1908. *work = 1;
  1909. return -EINVAL;
  1910. }
  1911. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1912. *work = 2;
  1913. return -EINVAL;
  1914. }
  1915. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1916. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1917. return -ENOMEM;
  1918. }
  1919. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1920. if (!fcoe_init)
  1921. return -ENOMEM;
  1922. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1923. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1924. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1925. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1926. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1927. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1928. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1929. fcoe_init->sb_num = cp->status_blk_num;
  1930. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1931. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1932. cp->kcq2.sw_prod_idx = 0;
  1933. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  1934. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1935. FCOE_CONNECTION_TYPE, &l5_data);
  1936. *work = 3;
  1937. return ret;
  1938. }
  1939. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1940. u32 num, int *work)
  1941. {
  1942. int ret = 0;
  1943. u32 cid = -1, l5_cid;
  1944. struct cnic_local *cp = dev->cnic_priv;
  1945. struct bnx2x *bp = netdev_priv(dev->netdev);
  1946. struct fcoe_kwqe_conn_offload1 *req1;
  1947. struct fcoe_kwqe_conn_offload2 *req2;
  1948. struct fcoe_kwqe_conn_offload3 *req3;
  1949. struct fcoe_kwqe_conn_offload4 *req4;
  1950. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1951. struct cnic_context *ctx;
  1952. struct fcoe_context *fctx;
  1953. struct regpair ctx_addr;
  1954. union l5cm_specific_data l5_data;
  1955. struct fcoe_kcqe kcqe;
  1956. struct kcqe *cqes[1];
  1957. if (num < 4) {
  1958. *work = num;
  1959. return -EINVAL;
  1960. }
  1961. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1962. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1963. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1964. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1965. *work = 4;
  1966. l5_cid = req1->fcoe_conn_id;
  1967. if (l5_cid >= dev->max_fcoe_conn)
  1968. goto err_reply;
  1969. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1970. ctx = &cp->ctx_tbl[l5_cid];
  1971. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1972. goto err_reply;
  1973. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1974. if (ret) {
  1975. ret = 0;
  1976. goto err_reply;
  1977. }
  1978. cid = ctx->cid;
  1979. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1980. if (fctx) {
  1981. u32 hw_cid = BNX2X_HW_CID(bp, cid);
  1982. u32 val;
  1983. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1984. FCOE_CONNECTION_TYPE);
  1985. fctx->xstorm_ag_context.cdu_reserved = val;
  1986. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1987. FCOE_CONNECTION_TYPE);
  1988. fctx->ustorm_ag_context.cdu_usage = val;
  1989. }
  1990. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1991. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1992. goto err_reply;
  1993. }
  1994. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1995. if (!fcoe_offload)
  1996. goto err_reply;
  1997. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1998. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1999. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  2000. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  2001. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  2002. cid = BNX2X_HW_CID(bp, cid);
  2003. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  2004. FCOE_CONNECTION_TYPE, &l5_data);
  2005. if (!ret)
  2006. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  2007. return ret;
  2008. err_reply:
  2009. if (cid != -1)
  2010. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  2011. memset(&kcqe, 0, sizeof(kcqe));
  2012. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  2013. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  2014. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  2015. cqes[0] = (struct kcqe *) &kcqe;
  2016. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2017. return ret;
  2018. }
  2019. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  2020. {
  2021. struct fcoe_kwqe_conn_enable_disable *req;
  2022. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  2023. union l5cm_specific_data l5_data;
  2024. int ret;
  2025. u32 cid, l5_cid;
  2026. struct cnic_local *cp = dev->cnic_priv;
  2027. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2028. cid = req->context_id;
  2029. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  2030. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  2031. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  2032. return -ENOMEM;
  2033. }
  2034. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2035. if (!fcoe_enable)
  2036. return -ENOMEM;
  2037. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  2038. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  2039. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  2040. FCOE_CONNECTION_TYPE, &l5_data);
  2041. return ret;
  2042. }
  2043. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  2044. {
  2045. struct fcoe_kwqe_conn_enable_disable *req;
  2046. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  2047. union l5cm_specific_data l5_data;
  2048. int ret;
  2049. u32 cid, l5_cid;
  2050. struct cnic_local *cp = dev->cnic_priv;
  2051. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2052. cid = req->context_id;
  2053. l5_cid = req->conn_id;
  2054. if (l5_cid >= dev->max_fcoe_conn)
  2055. return -EINVAL;
  2056. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2057. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2058. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2059. return -ENOMEM;
  2060. }
  2061. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2062. if (!fcoe_disable)
  2063. return -ENOMEM;
  2064. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2065. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2066. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2067. FCOE_CONNECTION_TYPE, &l5_data);
  2068. return ret;
  2069. }
  2070. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2071. {
  2072. struct fcoe_kwqe_conn_destroy *req;
  2073. union l5cm_specific_data l5_data;
  2074. int ret;
  2075. u32 cid, l5_cid;
  2076. struct cnic_local *cp = dev->cnic_priv;
  2077. struct cnic_context *ctx;
  2078. struct fcoe_kcqe kcqe;
  2079. struct kcqe *cqes[1];
  2080. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2081. cid = req->context_id;
  2082. l5_cid = req->conn_id;
  2083. if (l5_cid >= dev->max_fcoe_conn)
  2084. return -EINVAL;
  2085. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2086. ctx = &cp->ctx_tbl[l5_cid];
  2087. init_waitqueue_head(&ctx->waitq);
  2088. ctx->wait_cond = 0;
  2089. memset(&kcqe, 0, sizeof(kcqe));
  2090. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2091. memset(&l5_data, 0, sizeof(l5_data));
  2092. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2093. FCOE_CONNECTION_TYPE, &l5_data);
  2094. if (ret == 0) {
  2095. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2096. if (ctx->wait_cond)
  2097. kcqe.completion_status = 0;
  2098. }
  2099. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2100. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2101. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2102. kcqe.fcoe_conn_id = req->conn_id;
  2103. kcqe.fcoe_conn_context_id = cid;
  2104. cqes[0] = (struct kcqe *) &kcqe;
  2105. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2106. return ret;
  2107. }
  2108. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2109. {
  2110. struct cnic_local *cp = dev->cnic_priv;
  2111. u32 i;
  2112. for (i = start_cid; i < cp->max_cid_space; i++) {
  2113. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2114. int j;
  2115. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2116. msleep(10);
  2117. for (j = 0; j < 5; j++) {
  2118. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2119. break;
  2120. msleep(20);
  2121. }
  2122. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2123. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2124. ctx->cid);
  2125. }
  2126. }
  2127. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2128. {
  2129. struct fcoe_kwqe_destroy *req;
  2130. union l5cm_specific_data l5_data;
  2131. struct cnic_local *cp = dev->cnic_priv;
  2132. struct bnx2x *bp = netdev_priv(dev->netdev);
  2133. int ret;
  2134. u32 cid;
  2135. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2136. req = (struct fcoe_kwqe_destroy *) kwqe;
  2137. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  2138. memset(&l5_data, 0, sizeof(l5_data));
  2139. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2140. FCOE_CONNECTION_TYPE, &l5_data);
  2141. return ret;
  2142. }
  2143. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2144. {
  2145. struct cnic_local *cp = dev->cnic_priv;
  2146. struct kcqe kcqe;
  2147. struct kcqe *cqes[1];
  2148. u32 cid;
  2149. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2150. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2151. u32 kcqe_op;
  2152. int ulp_type;
  2153. cid = kwqe->kwqe_info0;
  2154. memset(&kcqe, 0, sizeof(kcqe));
  2155. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2156. u32 l5_cid = 0;
  2157. ulp_type = CNIC_ULP_FCOE;
  2158. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2159. struct fcoe_kwqe_conn_enable_disable *req;
  2160. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2161. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2162. cid = req->context_id;
  2163. l5_cid = req->conn_id;
  2164. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2165. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2166. } else {
  2167. return;
  2168. }
  2169. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2170. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2171. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2172. kcqe.kcqe_info2 = cid;
  2173. kcqe.kcqe_info0 = l5_cid;
  2174. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2175. ulp_type = CNIC_ULP_ISCSI;
  2176. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2177. cid = kwqe->kwqe_info1;
  2178. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2179. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2180. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2181. kcqe.kcqe_info2 = cid;
  2182. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2183. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2184. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2185. ulp_type = CNIC_ULP_L4;
  2186. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2187. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2188. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2189. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2190. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2191. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2192. else
  2193. return;
  2194. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2195. KCQE_FLAGS_LAYER_MASK_L4;
  2196. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2197. l4kcqe->cid = cid;
  2198. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2199. } else {
  2200. return;
  2201. }
  2202. cqes[0] = &kcqe;
  2203. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2204. }
  2205. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2206. struct kwqe *wqes[], u32 num_wqes)
  2207. {
  2208. int i, work, ret;
  2209. u32 opcode;
  2210. struct kwqe *kwqe;
  2211. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2212. return -EAGAIN; /* bnx2 is down */
  2213. for (i = 0; i < num_wqes; ) {
  2214. kwqe = wqes[i];
  2215. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2216. work = 1;
  2217. switch (opcode) {
  2218. case ISCSI_KWQE_OPCODE_INIT1:
  2219. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2220. break;
  2221. case ISCSI_KWQE_OPCODE_INIT2:
  2222. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2223. break;
  2224. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2225. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2226. num_wqes - i, &work);
  2227. break;
  2228. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2229. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2230. break;
  2231. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2232. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2233. break;
  2234. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2235. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2236. &work);
  2237. break;
  2238. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2239. ret = cnic_bnx2x_close(dev, kwqe);
  2240. break;
  2241. case L4_KWQE_OPCODE_VALUE_RESET:
  2242. ret = cnic_bnx2x_reset(dev, kwqe);
  2243. break;
  2244. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2245. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2246. break;
  2247. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2248. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2249. break;
  2250. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2251. ret = 0;
  2252. break;
  2253. default:
  2254. ret = 0;
  2255. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2256. opcode);
  2257. break;
  2258. }
  2259. if (ret < 0) {
  2260. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2261. opcode);
  2262. /* Possibly bnx2x parity error, send completion
  2263. * to ulp drivers with error code to speed up
  2264. * cleanup and reset recovery.
  2265. */
  2266. if (ret == -EIO || ret == -EAGAIN)
  2267. cnic_bnx2x_kwqe_err(dev, kwqe);
  2268. }
  2269. i += work;
  2270. }
  2271. return 0;
  2272. }
  2273. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2274. struct kwqe *wqes[], u32 num_wqes)
  2275. {
  2276. struct bnx2x *bp = netdev_priv(dev->netdev);
  2277. int i, work, ret;
  2278. u32 opcode;
  2279. struct kwqe *kwqe;
  2280. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2281. return -EAGAIN; /* bnx2 is down */
  2282. if (!BNX2X_CHIP_IS_E2_PLUS(bp))
  2283. return -EINVAL;
  2284. for (i = 0; i < num_wqes; ) {
  2285. kwqe = wqes[i];
  2286. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2287. work = 1;
  2288. switch (opcode) {
  2289. case FCOE_KWQE_OPCODE_INIT1:
  2290. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2291. num_wqes - i, &work);
  2292. break;
  2293. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2294. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2295. num_wqes - i, &work);
  2296. break;
  2297. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2298. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2299. break;
  2300. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2301. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2302. break;
  2303. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2304. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2305. break;
  2306. case FCOE_KWQE_OPCODE_DESTROY:
  2307. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2308. break;
  2309. case FCOE_KWQE_OPCODE_STAT:
  2310. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2311. break;
  2312. default:
  2313. ret = 0;
  2314. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2315. opcode);
  2316. break;
  2317. }
  2318. if (ret < 0) {
  2319. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2320. opcode);
  2321. /* Possibly bnx2x parity error, send completion
  2322. * to ulp drivers with error code to speed up
  2323. * cleanup and reset recovery.
  2324. */
  2325. if (ret == -EIO || ret == -EAGAIN)
  2326. cnic_bnx2x_kwqe_err(dev, kwqe);
  2327. }
  2328. i += work;
  2329. }
  2330. return 0;
  2331. }
  2332. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2333. u32 num_wqes)
  2334. {
  2335. int ret = -EINVAL;
  2336. u32 layer_code;
  2337. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2338. return -EAGAIN; /* bnx2x is down */
  2339. if (!num_wqes)
  2340. return 0;
  2341. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2342. switch (layer_code) {
  2343. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2344. case KWQE_FLAGS_LAYER_MASK_L4:
  2345. case KWQE_FLAGS_LAYER_MASK_L2:
  2346. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2347. break;
  2348. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2349. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2350. break;
  2351. }
  2352. return ret;
  2353. }
  2354. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2355. {
  2356. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2357. return KCQE_FLAGS_LAYER_MASK_L4;
  2358. return opflag & KCQE_FLAGS_LAYER_MASK;
  2359. }
  2360. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2361. {
  2362. struct cnic_local *cp = dev->cnic_priv;
  2363. int i, j, comp = 0;
  2364. i = 0;
  2365. j = 1;
  2366. while (num_cqes) {
  2367. struct cnic_ulp_ops *ulp_ops;
  2368. int ulp_type;
  2369. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2370. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2371. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2372. comp++;
  2373. while (j < num_cqes) {
  2374. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2375. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2376. break;
  2377. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2378. comp++;
  2379. j++;
  2380. }
  2381. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2382. ulp_type = CNIC_ULP_RDMA;
  2383. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2384. ulp_type = CNIC_ULP_ISCSI;
  2385. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2386. ulp_type = CNIC_ULP_FCOE;
  2387. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2388. ulp_type = CNIC_ULP_L4;
  2389. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2390. goto end;
  2391. else {
  2392. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2393. kcqe_op_flag);
  2394. goto end;
  2395. }
  2396. rcu_read_lock();
  2397. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2398. if (likely(ulp_ops)) {
  2399. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2400. cp->completed_kcq + i, j);
  2401. }
  2402. rcu_read_unlock();
  2403. end:
  2404. num_cqes -= j;
  2405. i += j;
  2406. j = 1;
  2407. }
  2408. if (unlikely(comp))
  2409. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2410. }
  2411. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2412. {
  2413. struct cnic_local *cp = dev->cnic_priv;
  2414. u16 i, ri, hw_prod, last;
  2415. struct kcqe *kcqe;
  2416. int kcqe_cnt = 0, last_cnt = 0;
  2417. i = ri = last = info->sw_prod_idx;
  2418. ri &= MAX_KCQ_IDX;
  2419. hw_prod = *info->hw_prod_idx_ptr;
  2420. hw_prod = info->hw_idx(hw_prod);
  2421. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2422. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2423. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2424. i = info->next_idx(i);
  2425. ri = i & MAX_KCQ_IDX;
  2426. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2427. last_cnt = kcqe_cnt;
  2428. last = i;
  2429. }
  2430. }
  2431. info->sw_prod_idx = last;
  2432. return last_cnt;
  2433. }
  2434. static int cnic_l2_completion(struct cnic_local *cp)
  2435. {
  2436. u16 hw_cons, sw_cons;
  2437. struct cnic_uio_dev *udev = cp->udev;
  2438. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2439. (udev->l2_ring + (2 * CNIC_PAGE_SIZE));
  2440. u32 cmd;
  2441. int comp = 0;
  2442. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2443. return 0;
  2444. hw_cons = *cp->rx_cons_ptr;
  2445. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2446. hw_cons++;
  2447. sw_cons = cp->rx_cons;
  2448. while (sw_cons != hw_cons) {
  2449. u8 cqe_fp_flags;
  2450. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2451. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2452. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2453. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2454. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2455. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2456. cmd == RAMROD_CMD_ID_ETH_HALT)
  2457. comp++;
  2458. }
  2459. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2460. }
  2461. return comp;
  2462. }
  2463. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2464. {
  2465. u16 rx_cons, tx_cons;
  2466. int comp = 0;
  2467. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2468. return;
  2469. rx_cons = *cp->rx_cons_ptr;
  2470. tx_cons = *cp->tx_cons_ptr;
  2471. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2472. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2473. comp = cnic_l2_completion(cp);
  2474. cp->tx_cons = tx_cons;
  2475. cp->rx_cons = rx_cons;
  2476. if (cp->udev)
  2477. uio_event_notify(&cp->udev->cnic_uinfo);
  2478. }
  2479. if (comp)
  2480. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2481. }
  2482. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2483. {
  2484. struct cnic_local *cp = dev->cnic_priv;
  2485. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2486. int kcqe_cnt;
  2487. /* status block index must be read before reading other fields */
  2488. rmb();
  2489. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2490. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2491. service_kcqes(dev, kcqe_cnt);
  2492. /* Tell compiler that status_blk fields can change. */
  2493. barrier();
  2494. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2495. /* status block index must be read first */
  2496. rmb();
  2497. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2498. }
  2499. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2500. cnic_chk_pkt_rings(cp);
  2501. return status_idx;
  2502. }
  2503. static int cnic_service_bnx2(void *data, void *status_blk)
  2504. {
  2505. struct cnic_dev *dev = data;
  2506. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2507. struct status_block *sblk = status_blk;
  2508. return sblk->status_idx;
  2509. }
  2510. return cnic_service_bnx2_queues(dev);
  2511. }
  2512. static void cnic_service_bnx2_msix(unsigned long data)
  2513. {
  2514. struct cnic_dev *dev = (struct cnic_dev *) data;
  2515. struct cnic_local *cp = dev->cnic_priv;
  2516. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2517. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2518. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2519. }
  2520. static void cnic_doirq(struct cnic_dev *dev)
  2521. {
  2522. struct cnic_local *cp = dev->cnic_priv;
  2523. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2524. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2525. prefetch(cp->status_blk.gen);
  2526. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2527. tasklet_schedule(&cp->cnic_irq_task);
  2528. }
  2529. }
  2530. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2531. {
  2532. struct cnic_dev *dev = dev_instance;
  2533. struct cnic_local *cp = dev->cnic_priv;
  2534. if (cp->ack_int)
  2535. cp->ack_int(dev);
  2536. cnic_doirq(dev);
  2537. return IRQ_HANDLED;
  2538. }
  2539. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2540. u16 index, u8 op, u8 update)
  2541. {
  2542. struct bnx2x *bp = netdev_priv(dev->netdev);
  2543. u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp) * 32 +
  2544. COMMAND_REG_INT_ACK);
  2545. struct igu_ack_register igu_ack;
  2546. igu_ack.status_block_index = index;
  2547. igu_ack.sb_id_and_flags =
  2548. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2549. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2550. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2551. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2552. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2553. }
  2554. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2555. u16 index, u8 op, u8 update)
  2556. {
  2557. struct igu_regular cmd_data;
  2558. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2559. cmd_data.sb_id_and_flags =
  2560. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2561. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2562. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2563. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2564. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2565. }
  2566. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2567. {
  2568. struct cnic_local *cp = dev->cnic_priv;
  2569. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2570. IGU_INT_DISABLE, 0);
  2571. }
  2572. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2573. {
  2574. struct cnic_local *cp = dev->cnic_priv;
  2575. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2576. IGU_INT_DISABLE, 0);
  2577. }
  2578. static void cnic_arm_bnx2x_msix(struct cnic_dev *dev, u32 idx)
  2579. {
  2580. struct cnic_local *cp = dev->cnic_priv;
  2581. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, idx,
  2582. IGU_INT_ENABLE, 1);
  2583. }
  2584. static void cnic_arm_bnx2x_e2_msix(struct cnic_dev *dev, u32 idx)
  2585. {
  2586. struct cnic_local *cp = dev->cnic_priv;
  2587. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, idx,
  2588. IGU_INT_ENABLE, 1);
  2589. }
  2590. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2591. {
  2592. u32 last_status = *info->status_idx_ptr;
  2593. int kcqe_cnt;
  2594. /* status block index must be read before reading the KCQ */
  2595. rmb();
  2596. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2597. service_kcqes(dev, kcqe_cnt);
  2598. /* Tell compiler that sblk fields can change. */
  2599. barrier();
  2600. last_status = *info->status_idx_ptr;
  2601. /* status block index must be read before reading the KCQ */
  2602. rmb();
  2603. }
  2604. return last_status;
  2605. }
  2606. static void cnic_service_bnx2x_bh(unsigned long data)
  2607. {
  2608. struct cnic_dev *dev = (struct cnic_dev *) data;
  2609. struct cnic_local *cp = dev->cnic_priv;
  2610. struct bnx2x *bp = netdev_priv(dev->netdev);
  2611. u32 status_idx, new_status_idx;
  2612. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2613. return;
  2614. while (1) {
  2615. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2616. CNIC_WR16(dev, cp->kcq1.io_addr,
  2617. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2618. if (!CNIC_SUPPORTS_FCOE(bp)) {
  2619. cp->arm_int(dev, status_idx);
  2620. break;
  2621. }
  2622. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2623. if (new_status_idx != status_idx)
  2624. continue;
  2625. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2626. MAX_KCQ_IDX);
  2627. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2628. status_idx, IGU_INT_ENABLE, 1);
  2629. break;
  2630. }
  2631. }
  2632. static int cnic_service_bnx2x(void *data, void *status_blk)
  2633. {
  2634. struct cnic_dev *dev = data;
  2635. struct cnic_local *cp = dev->cnic_priv;
  2636. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2637. cnic_doirq(dev);
  2638. cnic_chk_pkt_rings(cp);
  2639. return 0;
  2640. }
  2641. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2642. {
  2643. struct cnic_ulp_ops *ulp_ops;
  2644. if (if_type == CNIC_ULP_ISCSI)
  2645. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2646. mutex_lock(&cnic_lock);
  2647. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2648. lockdep_is_held(&cnic_lock));
  2649. if (!ulp_ops) {
  2650. mutex_unlock(&cnic_lock);
  2651. return;
  2652. }
  2653. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2654. mutex_unlock(&cnic_lock);
  2655. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2656. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2657. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2658. }
  2659. static void cnic_ulp_stop(struct cnic_dev *dev)
  2660. {
  2661. struct cnic_local *cp = dev->cnic_priv;
  2662. int if_type;
  2663. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2664. cnic_ulp_stop_one(cp, if_type);
  2665. }
  2666. static void cnic_ulp_start(struct cnic_dev *dev)
  2667. {
  2668. struct cnic_local *cp = dev->cnic_priv;
  2669. int if_type;
  2670. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2671. struct cnic_ulp_ops *ulp_ops;
  2672. mutex_lock(&cnic_lock);
  2673. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2674. lockdep_is_held(&cnic_lock));
  2675. if (!ulp_ops || !ulp_ops->cnic_start) {
  2676. mutex_unlock(&cnic_lock);
  2677. continue;
  2678. }
  2679. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2680. mutex_unlock(&cnic_lock);
  2681. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2682. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2683. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2684. }
  2685. }
  2686. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2687. {
  2688. struct cnic_local *cp = dev->cnic_priv;
  2689. struct cnic_ulp_ops *ulp_ops;
  2690. int rc;
  2691. mutex_lock(&cnic_lock);
  2692. ulp_ops = rcu_dereference_protected(cp->ulp_ops[ulp_type],
  2693. lockdep_is_held(&cnic_lock));
  2694. if (ulp_ops && ulp_ops->cnic_get_stats)
  2695. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2696. else
  2697. rc = -ENODEV;
  2698. mutex_unlock(&cnic_lock);
  2699. return rc;
  2700. }
  2701. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2702. {
  2703. struct cnic_dev *dev = data;
  2704. int ulp_type = CNIC_ULP_ISCSI;
  2705. switch (info->cmd) {
  2706. case CNIC_CTL_STOP_CMD:
  2707. cnic_hold(dev);
  2708. cnic_ulp_stop(dev);
  2709. cnic_stop_hw(dev);
  2710. cnic_put(dev);
  2711. break;
  2712. case CNIC_CTL_START_CMD:
  2713. cnic_hold(dev);
  2714. if (!cnic_start_hw(dev))
  2715. cnic_ulp_start(dev);
  2716. cnic_put(dev);
  2717. break;
  2718. case CNIC_CTL_STOP_ISCSI_CMD: {
  2719. struct cnic_local *cp = dev->cnic_priv;
  2720. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2721. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2722. break;
  2723. }
  2724. case CNIC_CTL_COMPLETION_CMD: {
  2725. struct cnic_ctl_completion *comp = &info->data.comp;
  2726. u32 cid = BNX2X_SW_CID(comp->cid);
  2727. u32 l5_cid;
  2728. struct cnic_local *cp = dev->cnic_priv;
  2729. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2730. break;
  2731. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2732. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2733. if (unlikely(comp->error)) {
  2734. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2735. netdev_err(dev->netdev,
  2736. "CID %x CFC delete comp error %x\n",
  2737. cid, comp->error);
  2738. }
  2739. ctx->wait_cond = 1;
  2740. wake_up(&ctx->waitq);
  2741. }
  2742. break;
  2743. }
  2744. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2745. ulp_type = CNIC_ULP_FCOE;
  2746. /* fall through */
  2747. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2748. cnic_hold(dev);
  2749. cnic_copy_ulp_stats(dev, ulp_type);
  2750. cnic_put(dev);
  2751. break;
  2752. default:
  2753. return -EINVAL;
  2754. }
  2755. return 0;
  2756. }
  2757. static void cnic_ulp_init(struct cnic_dev *dev)
  2758. {
  2759. int i;
  2760. struct cnic_local *cp = dev->cnic_priv;
  2761. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2762. struct cnic_ulp_ops *ulp_ops;
  2763. mutex_lock(&cnic_lock);
  2764. ulp_ops = cnic_ulp_tbl_prot(i);
  2765. if (!ulp_ops || !ulp_ops->cnic_init) {
  2766. mutex_unlock(&cnic_lock);
  2767. continue;
  2768. }
  2769. ulp_get(ulp_ops);
  2770. mutex_unlock(&cnic_lock);
  2771. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2772. ulp_ops->cnic_init(dev);
  2773. ulp_put(ulp_ops);
  2774. }
  2775. }
  2776. static void cnic_ulp_exit(struct cnic_dev *dev)
  2777. {
  2778. int i;
  2779. struct cnic_local *cp = dev->cnic_priv;
  2780. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2781. struct cnic_ulp_ops *ulp_ops;
  2782. mutex_lock(&cnic_lock);
  2783. ulp_ops = cnic_ulp_tbl_prot(i);
  2784. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2785. mutex_unlock(&cnic_lock);
  2786. continue;
  2787. }
  2788. ulp_get(ulp_ops);
  2789. mutex_unlock(&cnic_lock);
  2790. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2791. ulp_ops->cnic_exit(dev);
  2792. ulp_put(ulp_ops);
  2793. }
  2794. }
  2795. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2796. {
  2797. struct cnic_dev *dev = csk->dev;
  2798. struct l4_kwq_offload_pg *l4kwqe;
  2799. struct kwqe *wqes[1];
  2800. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2801. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2802. wqes[0] = (struct kwqe *) l4kwqe;
  2803. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2804. l4kwqe->flags =
  2805. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2806. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2807. l4kwqe->da0 = csk->ha[0];
  2808. l4kwqe->da1 = csk->ha[1];
  2809. l4kwqe->da2 = csk->ha[2];
  2810. l4kwqe->da3 = csk->ha[3];
  2811. l4kwqe->da4 = csk->ha[4];
  2812. l4kwqe->da5 = csk->ha[5];
  2813. l4kwqe->sa0 = dev->mac_addr[0];
  2814. l4kwqe->sa1 = dev->mac_addr[1];
  2815. l4kwqe->sa2 = dev->mac_addr[2];
  2816. l4kwqe->sa3 = dev->mac_addr[3];
  2817. l4kwqe->sa4 = dev->mac_addr[4];
  2818. l4kwqe->sa5 = dev->mac_addr[5];
  2819. l4kwqe->etype = ETH_P_IP;
  2820. l4kwqe->ipid_start = DEF_IPID_START;
  2821. l4kwqe->host_opaque = csk->l5_cid;
  2822. if (csk->vlan_id) {
  2823. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2824. l4kwqe->vlan_tag = csk->vlan_id;
  2825. l4kwqe->l2hdr_nbytes += 4;
  2826. }
  2827. return dev->submit_kwqes(dev, wqes, 1);
  2828. }
  2829. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2830. {
  2831. struct cnic_dev *dev = csk->dev;
  2832. struct l4_kwq_update_pg *l4kwqe;
  2833. struct kwqe *wqes[1];
  2834. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2835. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2836. wqes[0] = (struct kwqe *) l4kwqe;
  2837. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2838. l4kwqe->flags =
  2839. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2840. l4kwqe->pg_cid = csk->pg_cid;
  2841. l4kwqe->da0 = csk->ha[0];
  2842. l4kwqe->da1 = csk->ha[1];
  2843. l4kwqe->da2 = csk->ha[2];
  2844. l4kwqe->da3 = csk->ha[3];
  2845. l4kwqe->da4 = csk->ha[4];
  2846. l4kwqe->da5 = csk->ha[5];
  2847. l4kwqe->pg_host_opaque = csk->l5_cid;
  2848. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2849. return dev->submit_kwqes(dev, wqes, 1);
  2850. }
  2851. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2852. {
  2853. struct cnic_dev *dev = csk->dev;
  2854. struct l4_kwq_upload *l4kwqe;
  2855. struct kwqe *wqes[1];
  2856. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2857. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2858. wqes[0] = (struct kwqe *) l4kwqe;
  2859. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2860. l4kwqe->flags =
  2861. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2862. l4kwqe->cid = csk->pg_cid;
  2863. return dev->submit_kwqes(dev, wqes, 1);
  2864. }
  2865. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2866. {
  2867. struct cnic_dev *dev = csk->dev;
  2868. struct l4_kwq_connect_req1 *l4kwqe1;
  2869. struct l4_kwq_connect_req2 *l4kwqe2;
  2870. struct l4_kwq_connect_req3 *l4kwqe3;
  2871. struct kwqe *wqes[3];
  2872. u8 tcp_flags = 0;
  2873. int num_wqes = 2;
  2874. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2875. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2876. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2877. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2878. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2879. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2880. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2881. l4kwqe3->flags =
  2882. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2883. l4kwqe3->ka_timeout = csk->ka_timeout;
  2884. l4kwqe3->ka_interval = csk->ka_interval;
  2885. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2886. l4kwqe3->tos = csk->tos;
  2887. l4kwqe3->ttl = csk->ttl;
  2888. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2889. l4kwqe3->pmtu = csk->mtu;
  2890. l4kwqe3->rcv_buf = csk->rcv_buf;
  2891. l4kwqe3->snd_buf = csk->snd_buf;
  2892. l4kwqe3->seed = csk->seed;
  2893. wqes[0] = (struct kwqe *) l4kwqe1;
  2894. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2895. wqes[1] = (struct kwqe *) l4kwqe2;
  2896. wqes[2] = (struct kwqe *) l4kwqe3;
  2897. num_wqes = 3;
  2898. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2899. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2900. l4kwqe2->flags =
  2901. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2902. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2903. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2904. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2905. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2906. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2907. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2908. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2909. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2910. sizeof(struct tcphdr);
  2911. } else {
  2912. wqes[1] = (struct kwqe *) l4kwqe3;
  2913. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2914. sizeof(struct tcphdr);
  2915. }
  2916. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2917. l4kwqe1->flags =
  2918. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2919. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2920. l4kwqe1->cid = csk->cid;
  2921. l4kwqe1->pg_cid = csk->pg_cid;
  2922. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2923. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2924. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2925. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2926. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2927. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2928. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2929. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2930. if (csk->tcp_flags & SK_TCP_NAGLE)
  2931. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2932. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2933. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2934. if (csk->tcp_flags & SK_TCP_SACK)
  2935. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2936. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2937. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2938. l4kwqe1->tcp_flags = tcp_flags;
  2939. return dev->submit_kwqes(dev, wqes, num_wqes);
  2940. }
  2941. static int cnic_cm_close_req(struct cnic_sock *csk)
  2942. {
  2943. struct cnic_dev *dev = csk->dev;
  2944. struct l4_kwq_close_req *l4kwqe;
  2945. struct kwqe *wqes[1];
  2946. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2947. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2948. wqes[0] = (struct kwqe *) l4kwqe;
  2949. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2950. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2951. l4kwqe->cid = csk->cid;
  2952. return dev->submit_kwqes(dev, wqes, 1);
  2953. }
  2954. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2955. {
  2956. struct cnic_dev *dev = csk->dev;
  2957. struct l4_kwq_reset_req *l4kwqe;
  2958. struct kwqe *wqes[1];
  2959. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2960. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2961. wqes[0] = (struct kwqe *) l4kwqe;
  2962. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2963. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2964. l4kwqe->cid = csk->cid;
  2965. return dev->submit_kwqes(dev, wqes, 1);
  2966. }
  2967. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2968. u32 l5_cid, struct cnic_sock **csk, void *context)
  2969. {
  2970. struct cnic_local *cp = dev->cnic_priv;
  2971. struct cnic_sock *csk1;
  2972. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2973. return -EINVAL;
  2974. if (cp->ctx_tbl) {
  2975. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2976. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2977. return -EAGAIN;
  2978. }
  2979. csk1 = &cp->csk_tbl[l5_cid];
  2980. if (atomic_read(&csk1->ref_count))
  2981. return -EAGAIN;
  2982. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2983. return -EBUSY;
  2984. csk1->dev = dev;
  2985. csk1->cid = cid;
  2986. csk1->l5_cid = l5_cid;
  2987. csk1->ulp_type = ulp_type;
  2988. csk1->context = context;
  2989. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2990. csk1->ka_interval = DEF_KA_INTERVAL;
  2991. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2992. csk1->tos = DEF_TOS;
  2993. csk1->ttl = DEF_TTL;
  2994. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2995. csk1->rcv_buf = DEF_RCV_BUF;
  2996. csk1->snd_buf = DEF_SND_BUF;
  2997. csk1->seed = DEF_SEED;
  2998. csk1->tcp_flags = 0;
  2999. *csk = csk1;
  3000. return 0;
  3001. }
  3002. static void cnic_cm_cleanup(struct cnic_sock *csk)
  3003. {
  3004. if (csk->src_port) {
  3005. struct cnic_dev *dev = csk->dev;
  3006. struct cnic_local *cp = dev->cnic_priv;
  3007. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  3008. csk->src_port = 0;
  3009. }
  3010. }
  3011. static void cnic_close_conn(struct cnic_sock *csk)
  3012. {
  3013. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  3014. cnic_cm_upload_pg(csk);
  3015. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3016. }
  3017. cnic_cm_cleanup(csk);
  3018. }
  3019. static int cnic_cm_destroy(struct cnic_sock *csk)
  3020. {
  3021. if (!cnic_in_use(csk))
  3022. return -EINVAL;
  3023. csk_hold(csk);
  3024. clear_bit(SK_F_INUSE, &csk->flags);
  3025. smp_mb__after_atomic();
  3026. while (atomic_read(&csk->ref_count) != 1)
  3027. msleep(1);
  3028. cnic_cm_cleanup(csk);
  3029. csk->flags = 0;
  3030. csk_put(csk);
  3031. return 0;
  3032. }
  3033. static inline u16 cnic_get_vlan(struct net_device *dev,
  3034. struct net_device **vlan_dev)
  3035. {
  3036. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  3037. *vlan_dev = vlan_dev_real_dev(dev);
  3038. return vlan_dev_vlan_id(dev);
  3039. }
  3040. *vlan_dev = dev;
  3041. return 0;
  3042. }
  3043. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  3044. struct dst_entry **dst)
  3045. {
  3046. #if defined(CONFIG_INET)
  3047. struct rtable *rt;
  3048. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  3049. if (!IS_ERR(rt)) {
  3050. *dst = &rt->dst;
  3051. return 0;
  3052. }
  3053. return PTR_ERR(rt);
  3054. #else
  3055. return -ENETUNREACH;
  3056. #endif
  3057. }
  3058. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  3059. struct dst_entry **dst)
  3060. {
  3061. #if IS_ENABLED(CONFIG_IPV6)
  3062. struct flowi6 fl6;
  3063. memset(&fl6, 0, sizeof(fl6));
  3064. fl6.daddr = dst_addr->sin6_addr;
  3065. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  3066. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3067. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3068. if ((*dst)->error) {
  3069. dst_release(*dst);
  3070. *dst = NULL;
  3071. return -ENETUNREACH;
  3072. } else
  3073. return 0;
  3074. #endif
  3075. return -ENETUNREACH;
  3076. }
  3077. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3078. int ulp_type)
  3079. {
  3080. struct cnic_dev *dev = NULL;
  3081. struct dst_entry *dst;
  3082. struct net_device *netdev = NULL;
  3083. int err = -ENETUNREACH;
  3084. if (dst_addr->sin_family == AF_INET)
  3085. err = cnic_get_v4_route(dst_addr, &dst);
  3086. else if (dst_addr->sin_family == AF_INET6) {
  3087. struct sockaddr_in6 *dst_addr6 =
  3088. (struct sockaddr_in6 *) dst_addr;
  3089. err = cnic_get_v6_route(dst_addr6, &dst);
  3090. } else
  3091. return NULL;
  3092. if (err)
  3093. return NULL;
  3094. if (!dst->dev)
  3095. goto done;
  3096. cnic_get_vlan(dst->dev, &netdev);
  3097. dev = cnic_from_netdev(netdev);
  3098. done:
  3099. dst_release(dst);
  3100. if (dev)
  3101. cnic_put(dev);
  3102. return dev;
  3103. }
  3104. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3105. {
  3106. struct cnic_dev *dev = csk->dev;
  3107. struct cnic_local *cp = dev->cnic_priv;
  3108. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3109. }
  3110. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3111. {
  3112. struct cnic_dev *dev = csk->dev;
  3113. struct cnic_local *cp = dev->cnic_priv;
  3114. int is_v6, rc = 0;
  3115. struct dst_entry *dst = NULL;
  3116. struct net_device *realdev;
  3117. __be16 local_port;
  3118. u32 port_id;
  3119. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3120. saddr->remote.v6.sin6_family == AF_INET6)
  3121. is_v6 = 1;
  3122. else if (saddr->local.v4.sin_family == AF_INET &&
  3123. saddr->remote.v4.sin_family == AF_INET)
  3124. is_v6 = 0;
  3125. else
  3126. return -EINVAL;
  3127. clear_bit(SK_F_IPV6, &csk->flags);
  3128. if (is_v6) {
  3129. set_bit(SK_F_IPV6, &csk->flags);
  3130. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3131. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3132. sizeof(struct in6_addr));
  3133. csk->dst_port = saddr->remote.v6.sin6_port;
  3134. local_port = saddr->local.v6.sin6_port;
  3135. } else {
  3136. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3137. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3138. csk->dst_port = saddr->remote.v4.sin_port;
  3139. local_port = saddr->local.v4.sin_port;
  3140. }
  3141. csk->vlan_id = 0;
  3142. csk->mtu = dev->netdev->mtu;
  3143. if (dst && dst->dev) {
  3144. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3145. if (realdev == dev->netdev) {
  3146. csk->vlan_id = vlan;
  3147. csk->mtu = dst_mtu(dst);
  3148. }
  3149. }
  3150. port_id = be16_to_cpu(local_port);
  3151. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3152. port_id < CNIC_LOCAL_PORT_MAX) {
  3153. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3154. port_id = 0;
  3155. } else
  3156. port_id = 0;
  3157. if (!port_id) {
  3158. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3159. if (port_id == -1) {
  3160. rc = -ENOMEM;
  3161. goto err_out;
  3162. }
  3163. local_port = cpu_to_be16(port_id);
  3164. }
  3165. csk->src_port = local_port;
  3166. err_out:
  3167. dst_release(dst);
  3168. return rc;
  3169. }
  3170. static void cnic_init_csk_state(struct cnic_sock *csk)
  3171. {
  3172. csk->state = 0;
  3173. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3174. clear_bit(SK_F_CLOSING, &csk->flags);
  3175. }
  3176. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3177. {
  3178. struct cnic_local *cp = csk->dev->cnic_priv;
  3179. int err = 0;
  3180. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3181. return -EOPNOTSUPP;
  3182. if (!cnic_in_use(csk))
  3183. return -EINVAL;
  3184. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3185. return -EINVAL;
  3186. cnic_init_csk_state(csk);
  3187. err = cnic_get_route(csk, saddr);
  3188. if (err)
  3189. goto err_out;
  3190. err = cnic_resolve_addr(csk, saddr);
  3191. if (!err)
  3192. return 0;
  3193. err_out:
  3194. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3195. return err;
  3196. }
  3197. static int cnic_cm_abort(struct cnic_sock *csk)
  3198. {
  3199. struct cnic_local *cp = csk->dev->cnic_priv;
  3200. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3201. if (!cnic_in_use(csk))
  3202. return -EINVAL;
  3203. if (cnic_abort_prep(csk))
  3204. return cnic_cm_abort_req(csk);
  3205. /* Getting here means that we haven't started connect, or
  3206. * connect was not successful, or it has been reset by the target.
  3207. */
  3208. cp->close_conn(csk, opcode);
  3209. if (csk->state != opcode) {
  3210. /* Wait for remote reset sequence to complete */
  3211. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3212. msleep(1);
  3213. return -EALREADY;
  3214. }
  3215. return 0;
  3216. }
  3217. static int cnic_cm_close(struct cnic_sock *csk)
  3218. {
  3219. if (!cnic_in_use(csk))
  3220. return -EINVAL;
  3221. if (cnic_close_prep(csk)) {
  3222. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3223. return cnic_cm_close_req(csk);
  3224. } else {
  3225. /* Wait for remote reset sequence to complete */
  3226. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3227. msleep(1);
  3228. return -EALREADY;
  3229. }
  3230. return 0;
  3231. }
  3232. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3233. u8 opcode)
  3234. {
  3235. struct cnic_ulp_ops *ulp_ops;
  3236. int ulp_type = csk->ulp_type;
  3237. rcu_read_lock();
  3238. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3239. if (ulp_ops) {
  3240. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3241. ulp_ops->cm_connect_complete(csk);
  3242. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3243. ulp_ops->cm_close_complete(csk);
  3244. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3245. ulp_ops->cm_remote_abort(csk);
  3246. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3247. ulp_ops->cm_abort_complete(csk);
  3248. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3249. ulp_ops->cm_remote_close(csk);
  3250. }
  3251. rcu_read_unlock();
  3252. }
  3253. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3254. {
  3255. if (cnic_offld_prep(csk)) {
  3256. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3257. cnic_cm_update_pg(csk);
  3258. else
  3259. cnic_cm_offload_pg(csk);
  3260. }
  3261. return 0;
  3262. }
  3263. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3264. {
  3265. struct cnic_local *cp = dev->cnic_priv;
  3266. u32 l5_cid = kcqe->pg_host_opaque;
  3267. u8 opcode = kcqe->op_code;
  3268. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3269. csk_hold(csk);
  3270. if (!cnic_in_use(csk))
  3271. goto done;
  3272. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3273. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3274. goto done;
  3275. }
  3276. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3277. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3278. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3279. cnic_cm_upcall(cp, csk,
  3280. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3281. goto done;
  3282. }
  3283. csk->pg_cid = kcqe->pg_cid;
  3284. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3285. cnic_cm_conn_req(csk);
  3286. done:
  3287. csk_put(csk);
  3288. }
  3289. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3290. {
  3291. struct cnic_local *cp = dev->cnic_priv;
  3292. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3293. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3294. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3295. ctx->timestamp = jiffies;
  3296. ctx->wait_cond = 1;
  3297. wake_up(&ctx->waitq);
  3298. }
  3299. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3300. {
  3301. struct cnic_local *cp = dev->cnic_priv;
  3302. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3303. u8 opcode = l4kcqe->op_code;
  3304. u32 l5_cid;
  3305. struct cnic_sock *csk;
  3306. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3307. cnic_process_fcoe_term_conn(dev, kcqe);
  3308. return;
  3309. }
  3310. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3311. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3312. cnic_cm_process_offld_pg(dev, l4kcqe);
  3313. return;
  3314. }
  3315. l5_cid = l4kcqe->conn_id;
  3316. if (opcode & 0x80)
  3317. l5_cid = l4kcqe->cid;
  3318. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3319. return;
  3320. csk = &cp->csk_tbl[l5_cid];
  3321. csk_hold(csk);
  3322. if (!cnic_in_use(csk)) {
  3323. csk_put(csk);
  3324. return;
  3325. }
  3326. switch (opcode) {
  3327. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3328. if (l4kcqe->status != 0) {
  3329. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3330. cnic_cm_upcall(cp, csk,
  3331. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3332. }
  3333. break;
  3334. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3335. if (l4kcqe->status == 0)
  3336. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3337. else if (l4kcqe->status ==
  3338. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3339. set_bit(SK_F_HW_ERR, &csk->flags);
  3340. smp_mb__before_atomic();
  3341. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3342. cnic_cm_upcall(cp, csk, opcode);
  3343. break;
  3344. case L5CM_RAMROD_CMD_ID_CLOSE: {
  3345. struct iscsi_kcqe *l5kcqe = (struct iscsi_kcqe *) kcqe;
  3346. if (l4kcqe->status != 0 || l5kcqe->completion_status != 0) {
  3347. netdev_warn(dev->netdev, "RAMROD CLOSE compl with status 0x%x completion status 0x%x\n",
  3348. l4kcqe->status, l5kcqe->completion_status);
  3349. opcode = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3350. /* Fall through */
  3351. } else {
  3352. break;
  3353. }
  3354. }
  3355. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3356. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3357. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3358. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3359. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3360. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3361. set_bit(SK_F_HW_ERR, &csk->flags);
  3362. cp->close_conn(csk, opcode);
  3363. break;
  3364. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3365. /* after we already sent CLOSE_REQ */
  3366. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3367. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3368. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3369. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3370. else
  3371. cnic_cm_upcall(cp, csk, opcode);
  3372. break;
  3373. }
  3374. csk_put(csk);
  3375. }
  3376. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3377. {
  3378. struct cnic_dev *dev = data;
  3379. int i;
  3380. for (i = 0; i < num; i++)
  3381. cnic_cm_process_kcqe(dev, kcqe[i]);
  3382. }
  3383. static struct cnic_ulp_ops cm_ulp_ops = {
  3384. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3385. };
  3386. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3387. {
  3388. struct cnic_local *cp = dev->cnic_priv;
  3389. kfree(cp->csk_tbl);
  3390. cp->csk_tbl = NULL;
  3391. cnic_free_id_tbl(&cp->csk_port_tbl);
  3392. }
  3393. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3394. {
  3395. struct cnic_local *cp = dev->cnic_priv;
  3396. u32 port_id;
  3397. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3398. GFP_KERNEL);
  3399. if (!cp->csk_tbl)
  3400. return -ENOMEM;
  3401. port_id = prandom_u32();
  3402. port_id %= CNIC_LOCAL_PORT_RANGE;
  3403. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3404. CNIC_LOCAL_PORT_MIN, port_id)) {
  3405. cnic_cm_free_mem(dev);
  3406. return -ENOMEM;
  3407. }
  3408. return 0;
  3409. }
  3410. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3411. {
  3412. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3413. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3414. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3415. csk->state = opcode;
  3416. }
  3417. /* 1. If event opcode matches the expected event in csk->state
  3418. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3419. * event
  3420. * 3. If the expected event is 0, meaning the connection was never
  3421. * never established, we accept the opcode from cm_abort.
  3422. */
  3423. if (opcode == csk->state || csk->state == 0 ||
  3424. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3425. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3426. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3427. if (csk->state == 0)
  3428. csk->state = opcode;
  3429. return 1;
  3430. }
  3431. }
  3432. return 0;
  3433. }
  3434. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3435. {
  3436. struct cnic_dev *dev = csk->dev;
  3437. struct cnic_local *cp = dev->cnic_priv;
  3438. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3439. cnic_cm_upcall(cp, csk, opcode);
  3440. return;
  3441. }
  3442. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3443. cnic_close_conn(csk);
  3444. csk->state = opcode;
  3445. cnic_cm_upcall(cp, csk, opcode);
  3446. }
  3447. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3448. {
  3449. }
  3450. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3451. {
  3452. u32 seed;
  3453. seed = prandom_u32();
  3454. cnic_ctx_wr(dev, 45, 0, seed);
  3455. return 0;
  3456. }
  3457. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3458. {
  3459. struct cnic_dev *dev = csk->dev;
  3460. struct cnic_local *cp = dev->cnic_priv;
  3461. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3462. union l5cm_specific_data l5_data;
  3463. u32 cmd = 0;
  3464. int close_complete = 0;
  3465. switch (opcode) {
  3466. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3467. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3468. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3469. if (cnic_ready_to_close(csk, opcode)) {
  3470. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3471. close_complete = 1;
  3472. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3473. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3474. else
  3475. close_complete = 1;
  3476. }
  3477. break;
  3478. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3479. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3480. break;
  3481. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3482. close_complete = 1;
  3483. break;
  3484. }
  3485. if (cmd) {
  3486. memset(&l5_data, 0, sizeof(l5_data));
  3487. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3488. &l5_data);
  3489. } else if (close_complete) {
  3490. ctx->timestamp = jiffies;
  3491. cnic_close_conn(csk);
  3492. cnic_cm_upcall(cp, csk, csk->state);
  3493. }
  3494. }
  3495. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3496. {
  3497. struct cnic_local *cp = dev->cnic_priv;
  3498. if (!cp->ctx_tbl)
  3499. return;
  3500. if (!netif_running(dev->netdev))
  3501. return;
  3502. cnic_bnx2x_delete_wait(dev, 0);
  3503. cancel_delayed_work(&cp->delete_task);
  3504. flush_workqueue(cnic_wq);
  3505. if (atomic_read(&cp->iscsi_conn) != 0)
  3506. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3507. atomic_read(&cp->iscsi_conn));
  3508. }
  3509. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3510. {
  3511. struct bnx2x *bp = netdev_priv(dev->netdev);
  3512. u32 pfid = bp->pfid;
  3513. u32 port = BP_PORT(bp);
  3514. cnic_init_bnx2x_mac(dev);
  3515. cnic_bnx2x_set_tcp_options(dev, 0, 1);
  3516. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3517. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3518. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3519. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3520. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3521. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3522. DEF_MAX_DA_COUNT);
  3523. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3524. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3525. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3526. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3527. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3528. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3529. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3530. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3531. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3532. DEF_MAX_CWND);
  3533. return 0;
  3534. }
  3535. static void cnic_delete_task(struct work_struct *work)
  3536. {
  3537. struct cnic_local *cp;
  3538. struct cnic_dev *dev;
  3539. u32 i;
  3540. int need_resched = 0;
  3541. cp = container_of(work, struct cnic_local, delete_task.work);
  3542. dev = cp->dev;
  3543. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3544. struct drv_ctl_info info;
  3545. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3546. memset(&info, 0, sizeof(struct drv_ctl_info));
  3547. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3548. cp->ethdev->drv_ctl(dev->netdev, &info);
  3549. }
  3550. for (i = 0; i < cp->max_cid_space; i++) {
  3551. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3552. int err;
  3553. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3554. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3555. continue;
  3556. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3557. need_resched = 1;
  3558. continue;
  3559. }
  3560. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3561. continue;
  3562. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3563. cnic_free_bnx2x_conn_resc(dev, i);
  3564. if (!err) {
  3565. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3566. atomic_dec(&cp->iscsi_conn);
  3567. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3568. }
  3569. }
  3570. if (need_resched)
  3571. queue_delayed_work(cnic_wq, &cp->delete_task,
  3572. msecs_to_jiffies(10));
  3573. }
  3574. static int cnic_cm_open(struct cnic_dev *dev)
  3575. {
  3576. struct cnic_local *cp = dev->cnic_priv;
  3577. int err;
  3578. err = cnic_cm_alloc_mem(dev);
  3579. if (err)
  3580. return err;
  3581. err = cp->start_cm(dev);
  3582. if (err)
  3583. goto err_out;
  3584. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3585. dev->cm_create = cnic_cm_create;
  3586. dev->cm_destroy = cnic_cm_destroy;
  3587. dev->cm_connect = cnic_cm_connect;
  3588. dev->cm_abort = cnic_cm_abort;
  3589. dev->cm_close = cnic_cm_close;
  3590. dev->cm_select_dev = cnic_cm_select_dev;
  3591. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3592. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3593. return 0;
  3594. err_out:
  3595. cnic_cm_free_mem(dev);
  3596. return err;
  3597. }
  3598. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3599. {
  3600. struct cnic_local *cp = dev->cnic_priv;
  3601. int i;
  3602. if (!cp->csk_tbl)
  3603. return 0;
  3604. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3605. struct cnic_sock *csk = &cp->csk_tbl[i];
  3606. clear_bit(SK_F_INUSE, &csk->flags);
  3607. cnic_cm_cleanup(csk);
  3608. }
  3609. cnic_cm_free_mem(dev);
  3610. return 0;
  3611. }
  3612. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3613. {
  3614. u32 cid_addr;
  3615. int i;
  3616. cid_addr = GET_CID_ADDR(cid);
  3617. for (i = 0; i < CTX_SIZE; i += 4)
  3618. cnic_ctx_wr(dev, cid_addr, i, 0);
  3619. }
  3620. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3621. {
  3622. struct cnic_local *cp = dev->cnic_priv;
  3623. int ret = 0, i;
  3624. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3625. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3626. return 0;
  3627. for (i = 0; i < cp->ctx_blks; i++) {
  3628. int j;
  3629. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3630. u32 val;
  3631. memset(cp->ctx_arr[i].ctx, 0, CNIC_PAGE_SIZE);
  3632. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3633. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3634. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3635. (u64) cp->ctx_arr[i].mapping >> 32);
  3636. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3637. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3638. for (j = 0; j < 10; j++) {
  3639. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3640. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3641. break;
  3642. udelay(5);
  3643. }
  3644. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3645. ret = -EBUSY;
  3646. break;
  3647. }
  3648. }
  3649. return ret;
  3650. }
  3651. static void cnic_free_irq(struct cnic_dev *dev)
  3652. {
  3653. struct cnic_local *cp = dev->cnic_priv;
  3654. struct cnic_eth_dev *ethdev = cp->ethdev;
  3655. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3656. cp->disable_int_sync(dev);
  3657. tasklet_kill(&cp->cnic_irq_task);
  3658. free_irq(ethdev->irq_arr[0].vector, dev);
  3659. }
  3660. }
  3661. static int cnic_request_irq(struct cnic_dev *dev)
  3662. {
  3663. struct cnic_local *cp = dev->cnic_priv;
  3664. struct cnic_eth_dev *ethdev = cp->ethdev;
  3665. int err;
  3666. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3667. if (err)
  3668. tasklet_disable(&cp->cnic_irq_task);
  3669. return err;
  3670. }
  3671. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3672. {
  3673. struct cnic_local *cp = dev->cnic_priv;
  3674. struct cnic_eth_dev *ethdev = cp->ethdev;
  3675. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3676. int err, i = 0;
  3677. int sblk_num = cp->status_blk_num;
  3678. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3679. BNX2_HC_SB_CONFIG_1;
  3680. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3681. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3682. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3683. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3684. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3685. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3686. (unsigned long) dev);
  3687. err = cnic_request_irq(dev);
  3688. if (err)
  3689. return err;
  3690. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3691. i < 10) {
  3692. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3693. 1 << (11 + sblk_num));
  3694. udelay(10);
  3695. i++;
  3696. barrier();
  3697. }
  3698. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3699. cnic_free_irq(dev);
  3700. goto failed;
  3701. }
  3702. } else {
  3703. struct status_block *sblk = cp->status_blk.gen;
  3704. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3705. int i = 0;
  3706. while (sblk->status_completion_producer_index && i < 10) {
  3707. CNIC_WR(dev, BNX2_HC_COMMAND,
  3708. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3709. udelay(10);
  3710. i++;
  3711. barrier();
  3712. }
  3713. if (sblk->status_completion_producer_index)
  3714. goto failed;
  3715. }
  3716. return 0;
  3717. failed:
  3718. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3719. return -EBUSY;
  3720. }
  3721. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3722. {
  3723. struct cnic_local *cp = dev->cnic_priv;
  3724. struct cnic_eth_dev *ethdev = cp->ethdev;
  3725. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3726. return;
  3727. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3728. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3729. }
  3730. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3731. {
  3732. struct cnic_local *cp = dev->cnic_priv;
  3733. struct cnic_eth_dev *ethdev = cp->ethdev;
  3734. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3735. return;
  3736. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3737. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3738. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3739. synchronize_irq(ethdev->irq_arr[0].vector);
  3740. }
  3741. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3742. {
  3743. struct cnic_local *cp = dev->cnic_priv;
  3744. struct cnic_eth_dev *ethdev = cp->ethdev;
  3745. struct cnic_uio_dev *udev = cp->udev;
  3746. u32 cid_addr, tx_cid, sb_id;
  3747. u32 val, offset0, offset1, offset2, offset3;
  3748. int i;
  3749. struct bnx2_tx_bd *txbd;
  3750. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3751. struct status_block *s_blk = cp->status_blk.gen;
  3752. sb_id = cp->status_blk_num;
  3753. tx_cid = 20;
  3754. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3755. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3756. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3757. tx_cid = TX_TSS_CID + sb_id - 1;
  3758. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3759. (TX_TSS_CID << 7));
  3760. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3761. }
  3762. cp->tx_cons = *cp->tx_cons_ptr;
  3763. cid_addr = GET_CID_ADDR(tx_cid);
  3764. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  3765. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3766. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3767. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3768. offset0 = BNX2_L2CTX_TYPE_XI;
  3769. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3770. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3771. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3772. } else {
  3773. cnic_init_context(dev, tx_cid);
  3774. cnic_init_context(dev, tx_cid + 1);
  3775. offset0 = BNX2_L2CTX_TYPE;
  3776. offset1 = BNX2_L2CTX_CMD_TYPE;
  3777. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3778. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3779. }
  3780. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3781. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3782. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3783. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3784. txbd = udev->l2_ring;
  3785. buf_map = udev->l2_buf_map;
  3786. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i++, txbd++) {
  3787. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3788. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3789. }
  3790. val = (u64) ring_map >> 32;
  3791. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3792. txbd->tx_bd_haddr_hi = val;
  3793. val = (u64) ring_map & 0xffffffff;
  3794. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3795. txbd->tx_bd_haddr_lo = val;
  3796. }
  3797. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3798. {
  3799. struct cnic_local *cp = dev->cnic_priv;
  3800. struct cnic_eth_dev *ethdev = cp->ethdev;
  3801. struct cnic_uio_dev *udev = cp->udev;
  3802. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3803. int i;
  3804. struct bnx2_rx_bd *rxbd;
  3805. struct status_block *s_blk = cp->status_blk.gen;
  3806. dma_addr_t ring_map = udev->l2_ring_map;
  3807. sb_id = cp->status_blk_num;
  3808. cnic_init_context(dev, 2);
  3809. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3810. coal_reg = BNX2_HC_COMMAND;
  3811. coal_val = CNIC_RD(dev, coal_reg);
  3812. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3813. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3814. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3815. coal_reg = BNX2_HC_COALESCE_NOW;
  3816. coal_val = 1 << (11 + sb_id);
  3817. }
  3818. i = 0;
  3819. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3820. CNIC_WR(dev, coal_reg, coal_val);
  3821. udelay(10);
  3822. i++;
  3823. barrier();
  3824. }
  3825. cp->rx_cons = *cp->rx_cons_ptr;
  3826. cid_addr = GET_CID_ADDR(2);
  3827. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3828. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3829. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3830. if (sb_id == 0)
  3831. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3832. else
  3833. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3834. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3835. rxbd = udev->l2_ring + CNIC_PAGE_SIZE;
  3836. for (i = 0; i < BNX2_MAX_RX_DESC_CNT; i++, rxbd++) {
  3837. dma_addr_t buf_map;
  3838. int n = (i % cp->l2_rx_ring_size) + 1;
  3839. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3840. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3841. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3842. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3843. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3844. }
  3845. val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
  3846. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3847. rxbd->rx_bd_haddr_hi = val;
  3848. val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
  3849. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3850. rxbd->rx_bd_haddr_lo = val;
  3851. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3852. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3853. }
  3854. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3855. {
  3856. struct kwqe *wqes[1], l2kwqe;
  3857. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3858. wqes[0] = &l2kwqe;
  3859. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3860. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3861. KWQE_OPCODE_SHIFT) | 2;
  3862. dev->submit_kwqes(dev, wqes, 1);
  3863. }
  3864. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3865. {
  3866. struct cnic_local *cp = dev->cnic_priv;
  3867. u32 val;
  3868. val = cp->func << 2;
  3869. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3870. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3871. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3872. dev->mac_addr[0] = (u8) (val >> 8);
  3873. dev->mac_addr[1] = (u8) val;
  3874. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3875. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3876. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3877. dev->mac_addr[2] = (u8) (val >> 24);
  3878. dev->mac_addr[3] = (u8) (val >> 16);
  3879. dev->mac_addr[4] = (u8) (val >> 8);
  3880. dev->mac_addr[5] = (u8) val;
  3881. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3882. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3883. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3884. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3885. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3886. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3887. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3888. }
  3889. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3890. {
  3891. struct cnic_local *cp = dev->cnic_priv;
  3892. struct cnic_eth_dev *ethdev = cp->ethdev;
  3893. struct status_block *sblk = cp->status_blk.gen;
  3894. u32 val, kcq_cid_addr, kwq_cid_addr;
  3895. int err;
  3896. cnic_set_bnx2_mac(dev);
  3897. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3898. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3899. if (CNIC_PAGE_BITS > 12)
  3900. val |= (12 - 8) << 4;
  3901. else
  3902. val |= (CNIC_PAGE_BITS - 8) << 4;
  3903. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3904. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3905. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3906. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3907. err = cnic_setup_5709_context(dev, 1);
  3908. if (err)
  3909. return err;
  3910. cnic_init_context(dev, KWQ_CID);
  3911. cnic_init_context(dev, KCQ_CID);
  3912. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3913. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3914. cp->max_kwq_idx = MAX_KWQ_IDX;
  3915. cp->kwq_prod_idx = 0;
  3916. cp->kwq_con_idx = 0;
  3917. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3918. if (BNX2_CHIP(cp) == BNX2_CHIP_5706 || BNX2_CHIP(cp) == BNX2_CHIP_5708)
  3919. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3920. else
  3921. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3922. /* Initialize the kernel work queue context. */
  3923. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3924. (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3925. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3926. val = (CNIC_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3927. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3928. val = ((CNIC_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3929. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3930. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3931. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3932. val = (u32) cp->kwq_info.pgtbl_map;
  3933. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3934. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3935. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3936. cp->kcq1.sw_prod_idx = 0;
  3937. cp->kcq1.hw_prod_idx_ptr =
  3938. &sblk->status_completion_producer_index;
  3939. cp->kcq1.status_idx_ptr = &sblk->status_idx;
  3940. /* Initialize the kernel complete queue context. */
  3941. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3942. (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3943. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3944. val = (CNIC_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3945. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3946. val = ((CNIC_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3947. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3948. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3949. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3950. val = (u32) cp->kcq1.dma.pgtbl_map;
  3951. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3952. cp->int_num = 0;
  3953. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3954. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3955. u32 sb_id = cp->status_blk_num;
  3956. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3957. cp->kcq1.hw_prod_idx_ptr =
  3958. &msblk->status_completion_producer_index;
  3959. cp->kcq1.status_idx_ptr = &msblk->status_idx;
  3960. cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
  3961. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3962. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3963. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3964. }
  3965. /* Enable Commnad Scheduler notification when we write to the
  3966. * host producer index of the kernel contexts. */
  3967. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3968. /* Enable Command Scheduler notification when we write to either
  3969. * the Send Queue or Receive Queue producer indexes of the kernel
  3970. * bypass contexts. */
  3971. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3972. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3973. /* Notify COM when the driver post an application buffer. */
  3974. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3975. /* Set the CP and COM doorbells. These two processors polls the
  3976. * doorbell for a non zero value before running. This must be done
  3977. * after setting up the kernel queue contexts. */
  3978. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3979. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3980. cnic_init_bnx2_tx_ring(dev);
  3981. cnic_init_bnx2_rx_ring(dev);
  3982. err = cnic_init_bnx2_irq(dev);
  3983. if (err) {
  3984. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3985. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3986. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3987. return err;
  3988. }
  3989. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  3990. return 0;
  3991. }
  3992. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3993. {
  3994. struct cnic_local *cp = dev->cnic_priv;
  3995. struct cnic_eth_dev *ethdev = cp->ethdev;
  3996. u32 start_offset = ethdev->ctx_tbl_offset;
  3997. int i;
  3998. for (i = 0; i < cp->ctx_blks; i++) {
  3999. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  4000. dma_addr_t map = ctx->mapping;
  4001. if (cp->ctx_align) {
  4002. unsigned long mask = cp->ctx_align - 1;
  4003. map = (map + mask) & ~mask;
  4004. }
  4005. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  4006. }
  4007. }
  4008. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  4009. {
  4010. struct cnic_local *cp = dev->cnic_priv;
  4011. struct cnic_eth_dev *ethdev = cp->ethdev;
  4012. int err = 0;
  4013. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  4014. (unsigned long) dev);
  4015. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  4016. err = cnic_request_irq(dev);
  4017. return err;
  4018. }
  4019. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  4020. u16 sb_id, u8 sb_index,
  4021. u8 disable)
  4022. {
  4023. struct bnx2x *bp = netdev_priv(dev->netdev);
  4024. u32 addr = BAR_CSTRORM_INTMEM +
  4025. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4026. offsetof(struct hc_status_block_data_e1x, index_data) +
  4027. sizeof(struct hc_index_data)*sb_index +
  4028. offsetof(struct hc_index_data, flags);
  4029. u16 flags = CNIC_RD16(dev, addr);
  4030. /* clear and set */
  4031. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  4032. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  4033. HC_INDEX_DATA_HC_ENABLED);
  4034. CNIC_WR16(dev, addr, flags);
  4035. }
  4036. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  4037. {
  4038. struct cnic_local *cp = dev->cnic_priv;
  4039. struct bnx2x *bp = netdev_priv(dev->netdev);
  4040. u8 sb_id = cp->status_blk_num;
  4041. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4042. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4043. offsetof(struct hc_status_block_data_e1x, index_data) +
  4044. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  4045. offsetof(struct hc_index_data, timeout), 64 / 4);
  4046. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  4047. }
  4048. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  4049. {
  4050. }
  4051. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  4052. struct client_init_ramrod_data *data)
  4053. {
  4054. struct cnic_local *cp = dev->cnic_priv;
  4055. struct bnx2x *bp = netdev_priv(dev->netdev);
  4056. struct cnic_uio_dev *udev = cp->udev;
  4057. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  4058. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  4059. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4060. int i;
  4061. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4062. u32 val;
  4063. memset(txbd, 0, CNIC_PAGE_SIZE);
  4064. buf_map = udev->l2_buf_map;
  4065. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  4066. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  4067. struct eth_tx_parse_bd_e1x *pbd_e1x =
  4068. &((txbd + 1)->parse_bd_e1x);
  4069. struct eth_tx_parse_bd_e2 *pbd_e2 = &((txbd + 1)->parse_bd_e2);
  4070. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  4071. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4072. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4073. reg_bd->addr_hi = start_bd->addr_hi;
  4074. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  4075. start_bd->nbytes = cpu_to_le16(0x10);
  4076. start_bd->nbd = cpu_to_le16(3);
  4077. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  4078. start_bd->general_data &= ~ETH_TX_START_BD_PARSE_NBDS;
  4079. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  4080. if (BNX2X_CHIP_IS_E2_PLUS(bp))
  4081. pbd_e2->parsing_data = (UNICAST_ADDRESS <<
  4082. ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
  4083. else
  4084. pbd_e1x->global_data = (UNICAST_ADDRESS <<
  4085. ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT);
  4086. }
  4087. val = (u64) ring_map >> 32;
  4088. txbd->next_bd.addr_hi = cpu_to_le32(val);
  4089. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  4090. val = (u64) ring_map & 0xffffffff;
  4091. txbd->next_bd.addr_lo = cpu_to_le32(val);
  4092. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  4093. /* Other ramrod params */
  4094. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  4095. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  4096. /* reset xstorm per client statistics */
  4097. if (cli < MAX_STAT_COUNTER_ID) {
  4098. data->general.statistics_zero_flg = 1;
  4099. data->general.statistics_en_flg = 1;
  4100. data->general.statistics_counter_id = cli;
  4101. }
  4102. cp->tx_cons_ptr =
  4103. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4104. }
  4105. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4106. struct client_init_ramrod_data *data)
  4107. {
  4108. struct cnic_local *cp = dev->cnic_priv;
  4109. struct bnx2x *bp = netdev_priv(dev->netdev);
  4110. struct cnic_uio_dev *udev = cp->udev;
  4111. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4112. CNIC_PAGE_SIZE);
  4113. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4114. (udev->l2_ring + (2 * CNIC_PAGE_SIZE));
  4115. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4116. int i;
  4117. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4118. int cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
  4119. u32 val;
  4120. dma_addr_t ring_map = udev->l2_ring_map;
  4121. /* General data */
  4122. data->general.client_id = cli;
  4123. data->general.activate_flg = 1;
  4124. data->general.sp_client_id = cli;
  4125. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4126. data->general.func_id = bp->pfid;
  4127. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4128. dma_addr_t buf_map;
  4129. int n = (i % cp->l2_rx_ring_size) + 1;
  4130. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4131. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4132. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4133. }
  4134. val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
  4135. rxbd->addr_hi = cpu_to_le32(val);
  4136. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4137. val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
  4138. rxbd->addr_lo = cpu_to_le32(val);
  4139. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4140. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4141. val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) >> 32;
  4142. rxcqe->addr_hi = cpu_to_le32(val);
  4143. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4144. val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) & 0xffffffff;
  4145. rxcqe->addr_lo = cpu_to_le32(val);
  4146. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4147. /* Other ramrod params */
  4148. data->rx.client_qzone_id = cl_qzone_id;
  4149. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4150. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4151. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4152. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4153. data->rx.outer_vlan_removal_enable_flg = 1;
  4154. data->rx.silent_vlan_removal_flg = 1;
  4155. data->rx.silent_vlan_value = 0;
  4156. data->rx.silent_vlan_mask = 0xffff;
  4157. cp->rx_cons_ptr =
  4158. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4159. cp->rx_cons = *cp->rx_cons_ptr;
  4160. }
  4161. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4162. {
  4163. struct cnic_local *cp = dev->cnic_priv;
  4164. struct bnx2x *bp = netdev_priv(dev->netdev);
  4165. u32 pfid = bp->pfid;
  4166. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4167. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4168. cp->kcq1.sw_prod_idx = 0;
  4169. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4170. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4171. cp->kcq1.hw_prod_idx_ptr =
  4172. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4173. cp->kcq1.status_idx_ptr =
  4174. &sb->sb.running_index[SM_RX_ID];
  4175. } else {
  4176. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4177. cp->kcq1.hw_prod_idx_ptr =
  4178. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4179. cp->kcq1.status_idx_ptr =
  4180. &sb->sb.running_index[SM_RX_ID];
  4181. }
  4182. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4183. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4184. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4185. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4186. cp->kcq2.sw_prod_idx = 0;
  4187. cp->kcq2.hw_prod_idx_ptr =
  4188. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4189. cp->kcq2.status_idx_ptr =
  4190. &sb->sb.running_index[SM_RX_ID];
  4191. }
  4192. }
  4193. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4194. {
  4195. struct cnic_local *cp = dev->cnic_priv;
  4196. struct bnx2x *bp = netdev_priv(dev->netdev);
  4197. struct cnic_eth_dev *ethdev = cp->ethdev;
  4198. int func, ret;
  4199. u32 pfid;
  4200. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4201. cp->func = bp->pf_num;
  4202. func = CNIC_FUNC(cp);
  4203. pfid = bp->pfid;
  4204. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4205. cp->iscsi_start_cid, 0);
  4206. if (ret)
  4207. return -ENOMEM;
  4208. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4209. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4210. cp->fcoe_start_cid, 0);
  4211. if (ret)
  4212. return -ENOMEM;
  4213. }
  4214. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4215. cnic_init_bnx2x_kcq(dev);
  4216. /* Only 1 EQ */
  4217. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4218. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4219. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4220. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4221. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4222. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4223. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4224. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4225. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4226. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4227. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4228. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4229. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4230. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4231. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4232. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4233. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4234. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4235. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4236. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4237. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4238. HC_INDEX_ISCSI_EQ_CONS);
  4239. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4240. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4241. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4242. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4243. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4244. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4245. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4246. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4247. cnic_setup_bnx2x_context(dev);
  4248. ret = cnic_init_bnx2x_irq(dev);
  4249. if (ret)
  4250. return ret;
  4251. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  4252. return 0;
  4253. }
  4254. static void cnic_init_rings(struct cnic_dev *dev)
  4255. {
  4256. struct cnic_local *cp = dev->cnic_priv;
  4257. struct bnx2x *bp = netdev_priv(dev->netdev);
  4258. struct cnic_uio_dev *udev = cp->udev;
  4259. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4260. return;
  4261. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4262. cnic_init_bnx2_tx_ring(dev);
  4263. cnic_init_bnx2_rx_ring(dev);
  4264. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4265. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4266. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4267. u32 cid = cp->ethdev->iscsi_l2_cid;
  4268. u32 cl_qzone_id;
  4269. struct client_init_ramrod_data *data;
  4270. union l5cm_specific_data l5_data;
  4271. struct ustorm_eth_rx_producers rx_prods = {0};
  4272. u32 off, i, *cid_ptr;
  4273. rx_prods.bd_prod = 0;
  4274. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4275. barrier();
  4276. cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
  4277. off = BAR_USTRORM_INTMEM +
  4278. (BNX2X_CHIP_IS_E2_PLUS(bp) ?
  4279. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4280. USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), cli));
  4281. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4282. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4283. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4284. data = udev->l2_buf;
  4285. cid_ptr = udev->l2_buf + 12;
  4286. memset(data, 0, sizeof(*data));
  4287. cnic_init_bnx2x_tx_ring(dev, data);
  4288. cnic_init_bnx2x_rx_ring(dev, data);
  4289. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4290. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4291. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4292. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4293. cid, ETH_CONNECTION_TYPE, &l5_data);
  4294. i = 0;
  4295. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4296. ++i < 10)
  4297. msleep(1);
  4298. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4299. netdev_err(dev->netdev,
  4300. "iSCSI CLIENT_SETUP did not complete\n");
  4301. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4302. cnic_ring_ctl(dev, cid, cli, 1);
  4303. *cid_ptr = cid >> 4;
  4304. *(cid_ptr + 1) = cid * bp->db_size;
  4305. *(cid_ptr + 2) = UIO_USE_TX_DOORBELL;
  4306. }
  4307. }
  4308. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4309. {
  4310. struct cnic_local *cp = dev->cnic_priv;
  4311. struct cnic_uio_dev *udev = cp->udev;
  4312. void *rx_ring;
  4313. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4314. return;
  4315. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4316. cnic_shutdown_bnx2_rx_ring(dev);
  4317. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4318. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4319. u32 cid = cp->ethdev->iscsi_l2_cid;
  4320. union l5cm_specific_data l5_data;
  4321. int i;
  4322. cnic_ring_ctl(dev, cid, cli, 0);
  4323. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4324. l5_data.phy_address.lo = cli;
  4325. l5_data.phy_address.hi = 0;
  4326. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4327. cid, ETH_CONNECTION_TYPE, &l5_data);
  4328. i = 0;
  4329. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4330. ++i < 10)
  4331. msleep(1);
  4332. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4333. netdev_err(dev->netdev,
  4334. "iSCSI CLIENT_HALT did not complete\n");
  4335. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4336. memset(&l5_data, 0, sizeof(l5_data));
  4337. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4338. cid, NONE_CONNECTION_TYPE, &l5_data);
  4339. msleep(10);
  4340. }
  4341. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4342. rx_ring = udev->l2_ring + CNIC_PAGE_SIZE;
  4343. memset(rx_ring, 0, CNIC_PAGE_SIZE);
  4344. }
  4345. static int cnic_register_netdev(struct cnic_dev *dev)
  4346. {
  4347. struct cnic_local *cp = dev->cnic_priv;
  4348. struct cnic_eth_dev *ethdev = cp->ethdev;
  4349. int err;
  4350. if (!ethdev)
  4351. return -ENODEV;
  4352. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4353. return 0;
  4354. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4355. if (err)
  4356. netdev_err(dev->netdev, "register_cnic failed\n");
  4357. /* Read iSCSI config again. On some bnx2x device, iSCSI config
  4358. * can change after firmware is downloaded.
  4359. */
  4360. dev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4361. if (ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  4362. dev->max_iscsi_conn = 0;
  4363. return err;
  4364. }
  4365. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4366. {
  4367. struct cnic_local *cp = dev->cnic_priv;
  4368. struct cnic_eth_dev *ethdev = cp->ethdev;
  4369. if (!ethdev)
  4370. return;
  4371. ethdev->drv_unregister_cnic(dev->netdev);
  4372. }
  4373. static int cnic_start_hw(struct cnic_dev *dev)
  4374. {
  4375. struct cnic_local *cp = dev->cnic_priv;
  4376. struct cnic_eth_dev *ethdev = cp->ethdev;
  4377. int err;
  4378. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4379. return -EALREADY;
  4380. dev->regview = ethdev->io_base;
  4381. pci_dev_get(dev->pcidev);
  4382. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4383. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4384. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4385. err = cp->alloc_resc(dev);
  4386. if (err) {
  4387. netdev_err(dev->netdev, "allocate resource failure\n");
  4388. goto err1;
  4389. }
  4390. err = cp->start_hw(dev);
  4391. if (err)
  4392. goto err1;
  4393. err = cnic_cm_open(dev);
  4394. if (err)
  4395. goto err1;
  4396. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4397. cp->enable_int(dev);
  4398. return 0;
  4399. err1:
  4400. if (ethdev->drv_state & CNIC_DRV_STATE_HANDLES_IRQ)
  4401. cp->stop_hw(dev);
  4402. else
  4403. cp->free_resc(dev);
  4404. pci_dev_put(dev->pcidev);
  4405. return err;
  4406. }
  4407. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4408. {
  4409. cnic_disable_bnx2_int_sync(dev);
  4410. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4411. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4412. cnic_init_context(dev, KWQ_CID);
  4413. cnic_init_context(dev, KCQ_CID);
  4414. cnic_setup_5709_context(dev, 0);
  4415. cnic_free_irq(dev);
  4416. cnic_free_resc(dev);
  4417. }
  4418. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4419. {
  4420. struct cnic_local *cp = dev->cnic_priv;
  4421. struct bnx2x *bp = netdev_priv(dev->netdev);
  4422. u32 hc_index = HC_INDEX_ISCSI_EQ_CONS;
  4423. u32 sb_id = cp->status_blk_num;
  4424. u32 idx_off, syn_off;
  4425. cnic_free_irq(dev);
  4426. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4427. idx_off = offsetof(struct hc_status_block_e2, index_values) +
  4428. (hc_index * sizeof(u16));
  4429. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hc_index, sb_id);
  4430. } else {
  4431. idx_off = offsetof(struct hc_status_block_e1x, index_values) +
  4432. (hc_index * sizeof(u16));
  4433. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hc_index, sb_id);
  4434. }
  4435. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + syn_off, 0);
  4436. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(sb_id) +
  4437. idx_off, 0);
  4438. *cp->kcq1.hw_prod_idx_ptr = 0;
  4439. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4440. CSTORM_ISCSI_EQ_CONS_OFFSET(bp->pfid, 0), 0);
  4441. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4442. cnic_free_resc(dev);
  4443. }
  4444. static void cnic_stop_hw(struct cnic_dev *dev)
  4445. {
  4446. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4447. struct cnic_local *cp = dev->cnic_priv;
  4448. int i = 0;
  4449. /* Need to wait for the ring shutdown event to complete
  4450. * before clearing the CNIC_UP flag.
  4451. */
  4452. while (cp->udev && cp->udev->uio_dev != -1 && i < 15) {
  4453. msleep(100);
  4454. i++;
  4455. }
  4456. cnic_shutdown_rings(dev);
  4457. cp->stop_cm(dev);
  4458. cp->ethdev->drv_state &= ~CNIC_DRV_STATE_HANDLES_IRQ;
  4459. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4460. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4461. synchronize_rcu();
  4462. cnic_cm_shutdown(dev);
  4463. cp->stop_hw(dev);
  4464. pci_dev_put(dev->pcidev);
  4465. }
  4466. }
  4467. static void cnic_free_dev(struct cnic_dev *dev)
  4468. {
  4469. int i = 0;
  4470. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4471. msleep(100);
  4472. i++;
  4473. }
  4474. if (atomic_read(&dev->ref_count) != 0)
  4475. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4476. netdev_info(dev->netdev, "Removed CNIC device\n");
  4477. dev_put(dev->netdev);
  4478. kfree(dev);
  4479. }
  4480. static int cnic_get_fc_npiv_tbl(struct cnic_dev *dev,
  4481. struct cnic_fc_npiv_tbl *npiv_tbl)
  4482. {
  4483. struct cnic_local *cp = dev->cnic_priv;
  4484. struct bnx2x *bp = netdev_priv(dev->netdev);
  4485. int ret;
  4486. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4487. return -EAGAIN; /* bnx2x is down */
  4488. if (!BNX2X_CHIP_IS_E2_PLUS(bp))
  4489. return -EINVAL;
  4490. ret = cp->ethdev->drv_get_fc_npiv_tbl(dev->netdev, npiv_tbl);
  4491. return ret;
  4492. }
  4493. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4494. struct pci_dev *pdev)
  4495. {
  4496. struct cnic_dev *cdev;
  4497. struct cnic_local *cp;
  4498. int alloc_size;
  4499. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4500. cdev = kzalloc(alloc_size, GFP_KERNEL);
  4501. if (cdev == NULL)
  4502. return NULL;
  4503. cdev->netdev = dev;
  4504. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4505. cdev->register_device = cnic_register_device;
  4506. cdev->unregister_device = cnic_unregister_device;
  4507. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4508. cdev->get_fc_npiv_tbl = cnic_get_fc_npiv_tbl;
  4509. cp = cdev->cnic_priv;
  4510. cp->dev = cdev;
  4511. cp->l2_single_buf_size = 0x400;
  4512. cp->l2_rx_ring_size = 3;
  4513. spin_lock_init(&cp->cnic_ulp_lock);
  4514. netdev_info(dev, "Added CNIC device\n");
  4515. return cdev;
  4516. }
  4517. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4518. {
  4519. struct pci_dev *pdev;
  4520. struct cnic_dev *cdev;
  4521. struct cnic_local *cp;
  4522. struct bnx2 *bp = netdev_priv(dev);
  4523. struct cnic_eth_dev *ethdev = NULL;
  4524. if (bp->cnic_probe)
  4525. ethdev = (bp->cnic_probe)(dev);
  4526. if (!ethdev)
  4527. return NULL;
  4528. pdev = ethdev->pdev;
  4529. if (!pdev)
  4530. return NULL;
  4531. dev_hold(dev);
  4532. pci_dev_get(pdev);
  4533. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4534. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4535. (pdev->revision < 0x10)) {
  4536. pci_dev_put(pdev);
  4537. goto cnic_err;
  4538. }
  4539. pci_dev_put(pdev);
  4540. cdev = cnic_alloc_dev(dev, pdev);
  4541. if (cdev == NULL)
  4542. goto cnic_err;
  4543. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4544. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4545. cp = cdev->cnic_priv;
  4546. cp->ethdev = ethdev;
  4547. cdev->pcidev = pdev;
  4548. cp->chip_id = ethdev->chip_id;
  4549. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4550. cp->cnic_ops = &cnic_bnx2_ops;
  4551. cp->start_hw = cnic_start_bnx2_hw;
  4552. cp->stop_hw = cnic_stop_bnx2_hw;
  4553. cp->setup_pgtbl = cnic_setup_page_tbl;
  4554. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4555. cp->free_resc = cnic_free_resc;
  4556. cp->start_cm = cnic_cm_init_bnx2_hw;
  4557. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4558. cp->enable_int = cnic_enable_bnx2_int;
  4559. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4560. cp->close_conn = cnic_close_bnx2_conn;
  4561. return cdev;
  4562. cnic_err:
  4563. dev_put(dev);
  4564. return NULL;
  4565. }
  4566. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4567. {
  4568. struct pci_dev *pdev;
  4569. struct cnic_dev *cdev;
  4570. struct cnic_local *cp;
  4571. struct bnx2x *bp = netdev_priv(dev);
  4572. struct cnic_eth_dev *ethdev = NULL;
  4573. if (bp->cnic_probe)
  4574. ethdev = bp->cnic_probe(dev);
  4575. if (!ethdev)
  4576. return NULL;
  4577. pdev = ethdev->pdev;
  4578. if (!pdev)
  4579. return NULL;
  4580. dev_hold(dev);
  4581. cdev = cnic_alloc_dev(dev, pdev);
  4582. if (cdev == NULL) {
  4583. dev_put(dev);
  4584. return NULL;
  4585. }
  4586. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4587. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4588. cp = cdev->cnic_priv;
  4589. cp->ethdev = ethdev;
  4590. cdev->pcidev = pdev;
  4591. cp->chip_id = ethdev->chip_id;
  4592. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4593. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4594. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4595. if (CNIC_SUPPORTS_FCOE(bp)) {
  4596. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4597. cdev->max_fcoe_exchanges = ethdev->max_fcoe_exchanges;
  4598. }
  4599. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4600. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4601. memcpy(cdev->mac_addr, ethdev->iscsi_mac, ETH_ALEN);
  4602. cp->cnic_ops = &cnic_bnx2x_ops;
  4603. cp->start_hw = cnic_start_bnx2x_hw;
  4604. cp->stop_hw = cnic_stop_bnx2x_hw;
  4605. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4606. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4607. cp->free_resc = cnic_free_resc;
  4608. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4609. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4610. cp->enable_int = cnic_enable_bnx2x_int;
  4611. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4612. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4613. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4614. cp->arm_int = cnic_arm_bnx2x_e2_msix;
  4615. } else {
  4616. cp->ack_int = cnic_ack_bnx2x_msix;
  4617. cp->arm_int = cnic_arm_bnx2x_msix;
  4618. }
  4619. cp->close_conn = cnic_close_bnx2x_conn;
  4620. return cdev;
  4621. }
  4622. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4623. {
  4624. struct ethtool_drvinfo drvinfo;
  4625. struct cnic_dev *cdev = NULL;
  4626. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4627. memset(&drvinfo, 0, sizeof(drvinfo));
  4628. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4629. if (!strcmp(drvinfo.driver, "bnx2"))
  4630. cdev = init_bnx2_cnic(dev);
  4631. if (!strcmp(drvinfo.driver, "bnx2x"))
  4632. cdev = init_bnx2x_cnic(dev);
  4633. if (cdev) {
  4634. write_lock(&cnic_dev_lock);
  4635. list_add(&cdev->list, &cnic_dev_list);
  4636. write_unlock(&cnic_dev_lock);
  4637. }
  4638. }
  4639. return cdev;
  4640. }
  4641. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4642. u16 vlan_id)
  4643. {
  4644. int if_type;
  4645. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4646. struct cnic_ulp_ops *ulp_ops;
  4647. void *ctx;
  4648. mutex_lock(&cnic_lock);
  4649. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  4650. lockdep_is_held(&cnic_lock));
  4651. if (!ulp_ops || !ulp_ops->indicate_netevent) {
  4652. mutex_unlock(&cnic_lock);
  4653. continue;
  4654. }
  4655. ctx = cp->ulp_handle[if_type];
  4656. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  4657. mutex_unlock(&cnic_lock);
  4658. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4659. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  4660. }
  4661. }
  4662. /* netdev event handler */
  4663. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4664. void *ptr)
  4665. {
  4666. struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
  4667. struct cnic_dev *dev;
  4668. int new_dev = 0;
  4669. dev = cnic_from_netdev(netdev);
  4670. if (!dev && event == NETDEV_REGISTER) {
  4671. /* Check for the hot-plug device */
  4672. dev = is_cnic_dev(netdev);
  4673. if (dev) {
  4674. new_dev = 1;
  4675. cnic_hold(dev);
  4676. }
  4677. }
  4678. if (dev) {
  4679. struct cnic_local *cp = dev->cnic_priv;
  4680. if (new_dev)
  4681. cnic_ulp_init(dev);
  4682. else if (event == NETDEV_UNREGISTER)
  4683. cnic_ulp_exit(dev);
  4684. if (event == NETDEV_UP) {
  4685. if (cnic_register_netdev(dev) != 0) {
  4686. cnic_put(dev);
  4687. goto done;
  4688. }
  4689. if (!cnic_start_hw(dev))
  4690. cnic_ulp_start(dev);
  4691. }
  4692. cnic_rcv_netevent(cp, event, 0);
  4693. if (event == NETDEV_GOING_DOWN) {
  4694. cnic_ulp_stop(dev);
  4695. cnic_stop_hw(dev);
  4696. cnic_unregister_netdev(dev);
  4697. } else if (event == NETDEV_UNREGISTER) {
  4698. write_lock(&cnic_dev_lock);
  4699. list_del_init(&dev->list);
  4700. write_unlock(&cnic_dev_lock);
  4701. cnic_put(dev);
  4702. cnic_free_dev(dev);
  4703. goto done;
  4704. }
  4705. cnic_put(dev);
  4706. } else {
  4707. struct net_device *realdev;
  4708. u16 vid;
  4709. vid = cnic_get_vlan(netdev, &realdev);
  4710. if (realdev) {
  4711. dev = cnic_from_netdev(realdev);
  4712. if (dev) {
  4713. vid |= VLAN_TAG_PRESENT;
  4714. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4715. cnic_put(dev);
  4716. }
  4717. }
  4718. }
  4719. done:
  4720. return NOTIFY_DONE;
  4721. }
  4722. static struct notifier_block cnic_netdev_notifier = {
  4723. .notifier_call = cnic_netdev_event
  4724. };
  4725. static void cnic_release(void)
  4726. {
  4727. struct cnic_uio_dev *udev;
  4728. while (!list_empty(&cnic_udev_list)) {
  4729. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4730. list);
  4731. cnic_free_uio(udev);
  4732. }
  4733. }
  4734. static int __init cnic_init(void)
  4735. {
  4736. int rc = 0;
  4737. pr_info("%s", version);
  4738. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4739. if (rc) {
  4740. cnic_release();
  4741. return rc;
  4742. }
  4743. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4744. if (!cnic_wq) {
  4745. cnic_release();
  4746. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4747. return -ENOMEM;
  4748. }
  4749. return 0;
  4750. }
  4751. static void __exit cnic_exit(void)
  4752. {
  4753. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4754. cnic_release();
  4755. destroy_workqueue(cnic_wq);
  4756. }
  4757. module_init(cnic_init);
  4758. module_exit(cnic_exit);