tps80031.c 16 KB

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  1. /*
  2. * tps80031.c -- TI TPS80031/TPS80032 mfd core driver.
  3. *
  4. * MFD core driver for TI TPS80031/TPS80032 Fully Integrated
  5. * Power Management with Power Path and Battery Charger
  6. *
  7. * Copyright (c) 2012, NVIDIA Corporation.
  8. *
  9. * Author: Laxman Dewangan <ldewangan@nvidia.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation version 2.
  14. *
  15. * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
  16. * whether express or implied; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  23. * 02111-1307, USA
  24. */
  25. #include <linux/err.h>
  26. #include <linux/i2c.h>
  27. #include <linux/init.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/irq.h>
  30. #include <linux/mfd/core.h>
  31. #include <linux/mfd/tps80031.h>
  32. #include <linux/module.h>
  33. #include <linux/pm.h>
  34. #include <linux/regmap.h>
  35. #include <linux/slab.h>
  36. static struct resource tps80031_rtc_resources[] = {
  37. {
  38. .start = TPS80031_INT_RTC_ALARM,
  39. .end = TPS80031_INT_RTC_ALARM,
  40. .flags = IORESOURCE_IRQ,
  41. },
  42. };
  43. /* TPS80031 sub mfd devices */
  44. static const struct mfd_cell tps80031_cell[] = {
  45. {
  46. .name = "tps80031-pmic",
  47. },
  48. {
  49. .name = "tps80031-clock",
  50. },
  51. {
  52. .name = "tps80031-rtc",
  53. .num_resources = ARRAY_SIZE(tps80031_rtc_resources),
  54. .resources = tps80031_rtc_resources,
  55. },
  56. {
  57. .name = "tps80031-gpadc",
  58. },
  59. {
  60. .name = "tps80031-fuel-gauge",
  61. },
  62. {
  63. .name = "tps80031-charger",
  64. },
  65. };
  66. static int tps80031_slave_address[TPS80031_NUM_SLAVES] = {
  67. TPS80031_I2C_ID0_ADDR,
  68. TPS80031_I2C_ID1_ADDR,
  69. TPS80031_I2C_ID2_ADDR,
  70. TPS80031_I2C_ID3_ADDR,
  71. };
  72. struct tps80031_pupd_data {
  73. u8 reg;
  74. u8 pullup_bit;
  75. u8 pulldown_bit;
  76. };
  77. #define TPS80031_IRQ(_reg, _mask) \
  78. { \
  79. .reg_offset = (TPS80031_INT_MSK_LINE_##_reg) - \
  80. TPS80031_INT_MSK_LINE_A, \
  81. .mask = BIT(_mask), \
  82. }
  83. static const struct regmap_irq tps80031_main_irqs[] = {
  84. [TPS80031_INT_PWRON] = TPS80031_IRQ(A, 0),
  85. [TPS80031_INT_RPWRON] = TPS80031_IRQ(A, 1),
  86. [TPS80031_INT_SYS_VLOW] = TPS80031_IRQ(A, 2),
  87. [TPS80031_INT_RTC_ALARM] = TPS80031_IRQ(A, 3),
  88. [TPS80031_INT_RTC_PERIOD] = TPS80031_IRQ(A, 4),
  89. [TPS80031_INT_HOT_DIE] = TPS80031_IRQ(A, 5),
  90. [TPS80031_INT_VXX_SHORT] = TPS80031_IRQ(A, 6),
  91. [TPS80031_INT_SPDURATION] = TPS80031_IRQ(A, 7),
  92. [TPS80031_INT_WATCHDOG] = TPS80031_IRQ(B, 0),
  93. [TPS80031_INT_BAT] = TPS80031_IRQ(B, 1),
  94. [TPS80031_INT_SIM] = TPS80031_IRQ(B, 2),
  95. [TPS80031_INT_MMC] = TPS80031_IRQ(B, 3),
  96. [TPS80031_INT_RES] = TPS80031_IRQ(B, 4),
  97. [TPS80031_INT_GPADC_RT] = TPS80031_IRQ(B, 5),
  98. [TPS80031_INT_GPADC_SW2_EOC] = TPS80031_IRQ(B, 6),
  99. [TPS80031_INT_CC_AUTOCAL] = TPS80031_IRQ(B, 7),
  100. [TPS80031_INT_ID_WKUP] = TPS80031_IRQ(C, 0),
  101. [TPS80031_INT_VBUSS_WKUP] = TPS80031_IRQ(C, 1),
  102. [TPS80031_INT_ID] = TPS80031_IRQ(C, 2),
  103. [TPS80031_INT_VBUS] = TPS80031_IRQ(C, 3),
  104. [TPS80031_INT_CHRG_CTRL] = TPS80031_IRQ(C, 4),
  105. [TPS80031_INT_EXT_CHRG] = TPS80031_IRQ(C, 5),
  106. [TPS80031_INT_INT_CHRG] = TPS80031_IRQ(C, 6),
  107. [TPS80031_INT_RES2] = TPS80031_IRQ(C, 7),
  108. };
  109. static struct regmap_irq_chip tps80031_irq_chip = {
  110. .name = "tps80031",
  111. .irqs = tps80031_main_irqs,
  112. .num_irqs = ARRAY_SIZE(tps80031_main_irqs),
  113. .num_regs = 3,
  114. .status_base = TPS80031_INT_STS_A,
  115. .mask_base = TPS80031_INT_MSK_LINE_A,
  116. };
  117. #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit) \
  118. { \
  119. .reg = TPS80031_CFG_INPUT_PUPD##_reg, \
  120. .pulldown_bit = _pulldown_bit, \
  121. .pullup_bit = _pullup_bit, \
  122. }
  123. static const struct tps80031_pupd_data tps80031_pupds[] = {
  124. [TPS80031_PREQ1] = PUPD_DATA(1, BIT(0), BIT(1)),
  125. [TPS80031_PREQ2A] = PUPD_DATA(1, BIT(2), BIT(3)),
  126. [TPS80031_PREQ2B] = PUPD_DATA(1, BIT(4), BIT(5)),
  127. [TPS80031_PREQ2C] = PUPD_DATA(1, BIT(6), BIT(7)),
  128. [TPS80031_PREQ3] = PUPD_DATA(2, BIT(0), BIT(1)),
  129. [TPS80031_NRES_WARM] = PUPD_DATA(2, 0, BIT(2)),
  130. [TPS80031_PWM_FORCE] = PUPD_DATA(2, BIT(5), 0),
  131. [TPS80031_CHRG_EXT_CHRG_STATZ] = PUPD_DATA(2, 0, BIT(6)),
  132. [TPS80031_SIM] = PUPD_DATA(3, BIT(0), BIT(1)),
  133. [TPS80031_MMC] = PUPD_DATA(3, BIT(2), BIT(3)),
  134. [TPS80031_GPADC_START] = PUPD_DATA(3, BIT(4), 0),
  135. [TPS80031_DVSI2C_SCL] = PUPD_DATA(4, 0, BIT(0)),
  136. [TPS80031_DVSI2C_SDA] = PUPD_DATA(4, 0, BIT(1)),
  137. [TPS80031_CTLI2C_SCL] = PUPD_DATA(4, 0, BIT(2)),
  138. [TPS80031_CTLI2C_SDA] = PUPD_DATA(4, 0, BIT(3)),
  139. };
  140. static struct tps80031 *tps80031_power_off_dev;
  141. int tps80031_ext_power_req_config(struct device *dev,
  142. unsigned long ext_ctrl_flag, int preq_bit,
  143. int state_reg_add, int trans_reg_add)
  144. {
  145. u8 res_ass_reg = 0;
  146. int preq_mask_bit = 0;
  147. int ret;
  148. if (!(ext_ctrl_flag & TPS80031_EXT_PWR_REQ))
  149. return 0;
  150. if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ1) {
  151. res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
  152. preq_mask_bit = 5;
  153. } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ2) {
  154. res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
  155. preq_mask_bit = 6;
  156. } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ3) {
  157. res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
  158. preq_mask_bit = 7;
  159. }
  160. /* Configure REQ_ASS registers */
  161. ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1, res_ass_reg,
  162. BIT(preq_bit & 0x7));
  163. if (ret < 0) {
  164. dev_err(dev, "reg 0x%02x setbit failed, err = %d\n",
  165. res_ass_reg, ret);
  166. return ret;
  167. }
  168. /* Unmask the PREQ */
  169. ret = tps80031_clr_bits(dev, TPS80031_SLAVE_ID1,
  170. TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
  171. if (ret < 0) {
  172. dev_err(dev, "reg 0x%02x clrbit failed, err = %d\n",
  173. TPS80031_PHOENIX_MSK_TRANSITION, ret);
  174. return ret;
  175. }
  176. /* Switch regulator control to resource now */
  177. if (ext_ctrl_flag & (TPS80031_PWR_REQ_INPUT_PREQ2 |
  178. TPS80031_PWR_REQ_INPUT_PREQ3)) {
  179. ret = tps80031_update(dev, TPS80031_SLAVE_ID1, state_reg_add,
  180. 0x0, TPS80031_STATE_MASK);
  181. if (ret < 0)
  182. dev_err(dev, "reg 0x%02x update failed, err = %d\n",
  183. state_reg_add, ret);
  184. } else {
  185. ret = tps80031_update(dev, TPS80031_SLAVE_ID1, trans_reg_add,
  186. TPS80031_TRANS_SLEEP_OFF,
  187. TPS80031_TRANS_SLEEP_MASK);
  188. if (ret < 0)
  189. dev_err(dev, "reg 0x%02x update failed, err = %d\n",
  190. trans_reg_add, ret);
  191. }
  192. return ret;
  193. }
  194. EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
  195. static void tps80031_power_off(void)
  196. {
  197. dev_info(tps80031_power_off_dev->dev, "switching off PMU\n");
  198. tps80031_write(tps80031_power_off_dev->dev, TPS80031_SLAVE_ID1,
  199. TPS80031_PHOENIX_DEV_ON, TPS80031_DEVOFF);
  200. }
  201. static void tps80031_pupd_init(struct tps80031 *tps80031,
  202. struct tps80031_platform_data *pdata)
  203. {
  204. struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data;
  205. int data_size = pdata->pupd_init_data_size;
  206. int i;
  207. for (i = 0; i < data_size; ++i) {
  208. struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i];
  209. const struct tps80031_pupd_data *pupd =
  210. &tps80031_pupds[pupd_init->input_pin];
  211. u8 update_value = 0;
  212. u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit;
  213. if (pupd_init->setting == TPS80031_PUPD_PULLDOWN)
  214. update_value = pupd->pulldown_bit;
  215. else if (pupd_init->setting == TPS80031_PUPD_PULLUP)
  216. update_value = pupd->pullup_bit;
  217. tps80031_update(tps80031->dev, TPS80031_SLAVE_ID1, pupd->reg,
  218. update_value, update_mask);
  219. }
  220. }
  221. static int tps80031_init_ext_control(struct tps80031 *tps80031,
  222. struct tps80031_platform_data *pdata)
  223. {
  224. struct device *dev = tps80031->dev;
  225. int ret;
  226. int i;
  227. /* Clear all external control for this rail */
  228. for (i = 0; i < 9; ++i) {
  229. ret = tps80031_write(dev, TPS80031_SLAVE_ID1,
  230. TPS80031_PREQ1_RES_ASS_A + i, 0);
  231. if (ret < 0) {
  232. dev_err(dev, "reg 0x%02x write failed, err = %d\n",
  233. TPS80031_PREQ1_RES_ASS_A + i, ret);
  234. return ret;
  235. }
  236. }
  237. /* Mask the PREQ */
  238. ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1,
  239. TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
  240. if (ret < 0) {
  241. dev_err(dev, "reg 0x%02x set_bits failed, err = %d\n",
  242. TPS80031_PHOENIX_MSK_TRANSITION, ret);
  243. return ret;
  244. }
  245. return ret;
  246. }
  247. static int tps80031_irq_init(struct tps80031 *tps80031, int irq, int irq_base)
  248. {
  249. struct device *dev = tps80031->dev;
  250. int i, ret;
  251. /*
  252. * The MASK register used for updating status register when
  253. * interrupt occurs and LINE register used to pass the status
  254. * to actual interrupt line. As per datasheet:
  255. * When INT_MSK_LINE [i] is set to 1, the associated interrupt
  256. * number i is INT line masked, which means that no interrupt is
  257. * generated on the INT line.
  258. * When INT_MSK_LINE [i] is set to 0, the associated interrupt
  259. * number i is line enabled: An interrupt is generated on the
  260. * INT line.
  261. * In any case, the INT_STS [i] status bit may or may not be updated,
  262. * only linked to the INT_MSK_STS [i] configuration register bit.
  263. *
  264. * When INT_MSK_STS [i] is set to 1, the associated interrupt number
  265. * i is status masked, which means that no interrupt is stored in
  266. * the INT_STS[i] status bit. Note that no interrupt number i is
  267. * generated on the INT line, even if the INT_MSK_LINE [i] register
  268. * bit is set to 0.
  269. * When INT_MSK_STS [i] is set to 0, the associated interrupt number i
  270. * is status enabled: An interrupt status is updated in the INT_STS [i]
  271. * register. The interrupt may or may not be generated on the INT line,
  272. * depending on the INT_MSK_LINE [i] configuration register bit.
  273. */
  274. for (i = 0; i < 3; i++)
  275. tps80031_write(dev, TPS80031_SLAVE_ID2,
  276. TPS80031_INT_MSK_STS_A + i, 0x00);
  277. ret = regmap_add_irq_chip(tps80031->regmap[TPS80031_SLAVE_ID2], irq,
  278. IRQF_ONESHOT, irq_base,
  279. &tps80031_irq_chip, &tps80031->irq_data);
  280. if (ret < 0) {
  281. dev_err(dev, "add irq failed, err = %d\n", ret);
  282. return ret;
  283. }
  284. return ret;
  285. }
  286. static bool rd_wr_reg_id0(struct device *dev, unsigned int reg)
  287. {
  288. switch (reg) {
  289. case TPS80031_SMPS1_CFG_FORCE ... TPS80031_SMPS2_CFG_VOLTAGE:
  290. return true;
  291. default:
  292. return false;
  293. }
  294. }
  295. static bool rd_wr_reg_id1(struct device *dev, unsigned int reg)
  296. {
  297. switch (reg) {
  298. case TPS80031_SECONDS_REG ... TPS80031_RTC_RESET_STATUS_REG:
  299. case TPS80031_VALIDITY0 ... TPS80031_VALIDITY7:
  300. case TPS80031_PHOENIX_START_CONDITION ... TPS80031_KEY_PRESS_DUR_CFG:
  301. case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE:
  302. case TPS80031_BROADCAST_ADDR_ALL ... TPS80031_BROADCAST_ADDR_CLK_RST:
  303. case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE:
  304. case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE:
  305. case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C:
  306. case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING:
  307. case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD:
  308. case TPS80031_BACKUP_REG:
  309. return true;
  310. default:
  311. return false;
  312. }
  313. }
  314. static bool is_volatile_reg_id1(struct device *dev, unsigned int reg)
  315. {
  316. switch (reg) {
  317. case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE:
  318. case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE:
  319. case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE:
  320. case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C:
  321. case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING:
  322. case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD:
  323. return true;
  324. default:
  325. return false;
  326. }
  327. }
  328. static bool rd_wr_reg_id2(struct device *dev, unsigned int reg)
  329. {
  330. switch (reg) {
  331. case TPS80031_USB_VENDOR_ID_LSB ... TPS80031_USB_OTG_REVISION:
  332. case TPS80031_GPADC_CTRL ... TPS80031_CTRL_P1:
  333. case TPS80031_RTCH0_LSB ... TPS80031_GPCH0_MSB:
  334. case TPS80031_TOGGLE1 ... TPS80031_VIBMODE:
  335. case TPS80031_PWM1ON ... TPS80031_PWM2OFF:
  336. case TPS80031_FG_REG_00 ... TPS80031_FG_REG_11:
  337. case TPS80031_INT_STS_A ... TPS80031_INT_MSK_STS_C:
  338. case TPS80031_CONTROLLER_CTRL2 ... TPS80031_LED_PWM_CTRL2:
  339. return true;
  340. default:
  341. return false;
  342. }
  343. }
  344. static bool rd_wr_reg_id3(struct device *dev, unsigned int reg)
  345. {
  346. switch (reg) {
  347. case TPS80031_GPADC_TRIM0 ... TPS80031_GPADC_TRIM18:
  348. return true;
  349. default:
  350. return false;
  351. }
  352. }
  353. static const struct regmap_config tps80031_regmap_configs[] = {
  354. {
  355. .reg_bits = 8,
  356. .val_bits = 8,
  357. .writeable_reg = rd_wr_reg_id0,
  358. .readable_reg = rd_wr_reg_id0,
  359. .max_register = TPS80031_MAX_REGISTER,
  360. },
  361. {
  362. .reg_bits = 8,
  363. .val_bits = 8,
  364. .writeable_reg = rd_wr_reg_id1,
  365. .readable_reg = rd_wr_reg_id1,
  366. .volatile_reg = is_volatile_reg_id1,
  367. .max_register = TPS80031_MAX_REGISTER,
  368. },
  369. {
  370. .reg_bits = 8,
  371. .val_bits = 8,
  372. .writeable_reg = rd_wr_reg_id2,
  373. .readable_reg = rd_wr_reg_id2,
  374. .max_register = TPS80031_MAX_REGISTER,
  375. },
  376. {
  377. .reg_bits = 8,
  378. .val_bits = 8,
  379. .writeable_reg = rd_wr_reg_id3,
  380. .readable_reg = rd_wr_reg_id3,
  381. .max_register = TPS80031_MAX_REGISTER,
  382. },
  383. };
  384. static int tps80031_probe(struct i2c_client *client,
  385. const struct i2c_device_id *id)
  386. {
  387. struct tps80031_platform_data *pdata = dev_get_platdata(&client->dev);
  388. struct tps80031 *tps80031;
  389. int ret;
  390. uint8_t es_version;
  391. uint8_t ep_ver;
  392. int i;
  393. if (!pdata) {
  394. dev_err(&client->dev, "tps80031 requires platform data\n");
  395. return -EINVAL;
  396. }
  397. tps80031 = devm_kzalloc(&client->dev, sizeof(*tps80031), GFP_KERNEL);
  398. if (!tps80031) {
  399. dev_err(&client->dev, "Malloc failed for tps80031\n");
  400. return -ENOMEM;
  401. }
  402. for (i = 0; i < TPS80031_NUM_SLAVES; i++) {
  403. if (tps80031_slave_address[i] == client->addr)
  404. tps80031->clients[i] = client;
  405. else
  406. tps80031->clients[i] = i2c_new_dummy(client->adapter,
  407. tps80031_slave_address[i]);
  408. if (!tps80031->clients[i]) {
  409. dev_err(&client->dev, "can't attach client %d\n", i);
  410. ret = -ENOMEM;
  411. goto fail_client_reg;
  412. }
  413. i2c_set_clientdata(tps80031->clients[i], tps80031);
  414. tps80031->regmap[i] = devm_regmap_init_i2c(tps80031->clients[i],
  415. &tps80031_regmap_configs[i]);
  416. if (IS_ERR(tps80031->regmap[i])) {
  417. ret = PTR_ERR(tps80031->regmap[i]);
  418. dev_err(&client->dev,
  419. "regmap %d init failed, err %d\n", i, ret);
  420. goto fail_client_reg;
  421. }
  422. }
  423. ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3,
  424. TPS80031_JTAGVERNUM, &es_version);
  425. if (ret < 0) {
  426. dev_err(&client->dev,
  427. "Silicon version number read failed: %d\n", ret);
  428. goto fail_client_reg;
  429. }
  430. ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3,
  431. TPS80031_EPROM_REV, &ep_ver);
  432. if (ret < 0) {
  433. dev_err(&client->dev,
  434. "Silicon eeprom version read failed: %d\n", ret);
  435. goto fail_client_reg;
  436. }
  437. dev_info(&client->dev, "ES version 0x%02x and EPROM version 0x%02x\n",
  438. es_version, ep_ver);
  439. tps80031->es_version = es_version;
  440. tps80031->dev = &client->dev;
  441. i2c_set_clientdata(client, tps80031);
  442. tps80031->chip_info = id->driver_data;
  443. ret = tps80031_irq_init(tps80031, client->irq, pdata->irq_base);
  444. if (ret) {
  445. dev_err(&client->dev, "IRQ init failed: %d\n", ret);
  446. goto fail_client_reg;
  447. }
  448. tps80031_pupd_init(tps80031, pdata);
  449. tps80031_init_ext_control(tps80031, pdata);
  450. ret = mfd_add_devices(tps80031->dev, -1,
  451. tps80031_cell, ARRAY_SIZE(tps80031_cell),
  452. NULL, 0,
  453. regmap_irq_get_domain(tps80031->irq_data));
  454. if (ret < 0) {
  455. dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret);
  456. goto fail_mfd_add;
  457. }
  458. if (pdata->use_power_off && !pm_power_off) {
  459. tps80031_power_off_dev = tps80031;
  460. pm_power_off = tps80031_power_off;
  461. }
  462. return 0;
  463. fail_mfd_add:
  464. regmap_del_irq_chip(client->irq, tps80031->irq_data);
  465. fail_client_reg:
  466. for (i = 0; i < TPS80031_NUM_SLAVES; i++) {
  467. if (tps80031->clients[i] && (tps80031->clients[i] != client))
  468. i2c_unregister_device(tps80031->clients[i]);
  469. }
  470. return ret;
  471. }
  472. static int tps80031_remove(struct i2c_client *client)
  473. {
  474. struct tps80031 *tps80031 = i2c_get_clientdata(client);
  475. int i;
  476. if (tps80031_power_off_dev == tps80031) {
  477. tps80031_power_off_dev = NULL;
  478. pm_power_off = NULL;
  479. }
  480. mfd_remove_devices(tps80031->dev);
  481. regmap_del_irq_chip(client->irq, tps80031->irq_data);
  482. for (i = 0; i < TPS80031_NUM_SLAVES; i++) {
  483. if (tps80031->clients[i] != client)
  484. i2c_unregister_device(tps80031->clients[i]);
  485. }
  486. return 0;
  487. }
  488. static const struct i2c_device_id tps80031_id_table[] = {
  489. { "tps80031", TPS80031 },
  490. { "tps80032", TPS80032 },
  491. { }
  492. };
  493. MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
  494. static struct i2c_driver tps80031_driver = {
  495. .driver = {
  496. .name = "tps80031",
  497. },
  498. .probe = tps80031_probe,
  499. .remove = tps80031_remove,
  500. .id_table = tps80031_id_table,
  501. };
  502. static int __init tps80031_init(void)
  503. {
  504. return i2c_add_driver(&tps80031_driver);
  505. }
  506. subsys_initcall(tps80031_init);
  507. static void __exit tps80031_exit(void)
  508. {
  509. i2c_del_driver(&tps80031_driver);
  510. }
  511. module_exit(tps80031_exit);
  512. MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
  513. MODULE_DESCRIPTION("TPS80031 core driver");
  514. MODULE_LICENSE("GPL v2");