da9052-irq.c 6.0 KB

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  1. /*
  2. * DA9052 interrupt support
  3. *
  4. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  5. * Based on arizona-irq.c, which is:
  6. *
  7. * Copyright 2012 Wolfson Microelectronics plc
  8. *
  9. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/device.h>
  16. #include <linux/delay.h>
  17. #include <linux/input.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/irq.h>
  20. #include <linux/irqdomain.h>
  21. #include <linux/slab.h>
  22. #include <linux/module.h>
  23. #include <linux/mfd/da9052/da9052.h>
  24. #include <linux/mfd/da9052/reg.h>
  25. #define DA9052_NUM_IRQ_REGS 4
  26. #define DA9052_IRQ_MASK_POS_1 0x01
  27. #define DA9052_IRQ_MASK_POS_2 0x02
  28. #define DA9052_IRQ_MASK_POS_3 0x04
  29. #define DA9052_IRQ_MASK_POS_4 0x08
  30. #define DA9052_IRQ_MASK_POS_5 0x10
  31. #define DA9052_IRQ_MASK_POS_6 0x20
  32. #define DA9052_IRQ_MASK_POS_7 0x40
  33. #define DA9052_IRQ_MASK_POS_8 0x80
  34. static const struct regmap_irq da9052_irqs[] = {
  35. [DA9052_IRQ_DCIN] = {
  36. .reg_offset = 0,
  37. .mask = DA9052_IRQ_MASK_POS_1,
  38. },
  39. [DA9052_IRQ_VBUS] = {
  40. .reg_offset = 0,
  41. .mask = DA9052_IRQ_MASK_POS_2,
  42. },
  43. [DA9052_IRQ_DCINREM] = {
  44. .reg_offset = 0,
  45. .mask = DA9052_IRQ_MASK_POS_3,
  46. },
  47. [DA9052_IRQ_VBUSREM] = {
  48. .reg_offset = 0,
  49. .mask = DA9052_IRQ_MASK_POS_4,
  50. },
  51. [DA9052_IRQ_VDDLOW] = {
  52. .reg_offset = 0,
  53. .mask = DA9052_IRQ_MASK_POS_5,
  54. },
  55. [DA9052_IRQ_ALARM] = {
  56. .reg_offset = 0,
  57. .mask = DA9052_IRQ_MASK_POS_6,
  58. },
  59. [DA9052_IRQ_SEQRDY] = {
  60. .reg_offset = 0,
  61. .mask = DA9052_IRQ_MASK_POS_7,
  62. },
  63. [DA9052_IRQ_COMP1V2] = {
  64. .reg_offset = 0,
  65. .mask = DA9052_IRQ_MASK_POS_8,
  66. },
  67. [DA9052_IRQ_NONKEY] = {
  68. .reg_offset = 1,
  69. .mask = DA9052_IRQ_MASK_POS_1,
  70. },
  71. [DA9052_IRQ_IDFLOAT] = {
  72. .reg_offset = 1,
  73. .mask = DA9052_IRQ_MASK_POS_2,
  74. },
  75. [DA9052_IRQ_IDGND] = {
  76. .reg_offset = 1,
  77. .mask = DA9052_IRQ_MASK_POS_3,
  78. },
  79. [DA9052_IRQ_CHGEND] = {
  80. .reg_offset = 1,
  81. .mask = DA9052_IRQ_MASK_POS_4,
  82. },
  83. [DA9052_IRQ_TBAT] = {
  84. .reg_offset = 1,
  85. .mask = DA9052_IRQ_MASK_POS_5,
  86. },
  87. [DA9052_IRQ_ADC_EOM] = {
  88. .reg_offset = 1,
  89. .mask = DA9052_IRQ_MASK_POS_6,
  90. },
  91. [DA9052_IRQ_PENDOWN] = {
  92. .reg_offset = 1,
  93. .mask = DA9052_IRQ_MASK_POS_7,
  94. },
  95. [DA9052_IRQ_TSIREADY] = {
  96. .reg_offset = 1,
  97. .mask = DA9052_IRQ_MASK_POS_8,
  98. },
  99. [DA9052_IRQ_GPI0] = {
  100. .reg_offset = 2,
  101. .mask = DA9052_IRQ_MASK_POS_1,
  102. },
  103. [DA9052_IRQ_GPI1] = {
  104. .reg_offset = 2,
  105. .mask = DA9052_IRQ_MASK_POS_2,
  106. },
  107. [DA9052_IRQ_GPI2] = {
  108. .reg_offset = 2,
  109. .mask = DA9052_IRQ_MASK_POS_3,
  110. },
  111. [DA9052_IRQ_GPI3] = {
  112. .reg_offset = 2,
  113. .mask = DA9052_IRQ_MASK_POS_4,
  114. },
  115. [DA9052_IRQ_GPI4] = {
  116. .reg_offset = 2,
  117. .mask = DA9052_IRQ_MASK_POS_5,
  118. },
  119. [DA9052_IRQ_GPI5] = {
  120. .reg_offset = 2,
  121. .mask = DA9052_IRQ_MASK_POS_6,
  122. },
  123. [DA9052_IRQ_GPI6] = {
  124. .reg_offset = 2,
  125. .mask = DA9052_IRQ_MASK_POS_7,
  126. },
  127. [DA9052_IRQ_GPI7] = {
  128. .reg_offset = 2,
  129. .mask = DA9052_IRQ_MASK_POS_8,
  130. },
  131. [DA9052_IRQ_GPI8] = {
  132. .reg_offset = 3,
  133. .mask = DA9052_IRQ_MASK_POS_1,
  134. },
  135. [DA9052_IRQ_GPI9] = {
  136. .reg_offset = 3,
  137. .mask = DA9052_IRQ_MASK_POS_2,
  138. },
  139. [DA9052_IRQ_GPI10] = {
  140. .reg_offset = 3,
  141. .mask = DA9052_IRQ_MASK_POS_3,
  142. },
  143. [DA9052_IRQ_GPI11] = {
  144. .reg_offset = 3,
  145. .mask = DA9052_IRQ_MASK_POS_4,
  146. },
  147. [DA9052_IRQ_GPI12] = {
  148. .reg_offset = 3,
  149. .mask = DA9052_IRQ_MASK_POS_5,
  150. },
  151. [DA9052_IRQ_GPI13] = {
  152. .reg_offset = 3,
  153. .mask = DA9052_IRQ_MASK_POS_6,
  154. },
  155. [DA9052_IRQ_GPI14] = {
  156. .reg_offset = 3,
  157. .mask = DA9052_IRQ_MASK_POS_7,
  158. },
  159. [DA9052_IRQ_GPI15] = {
  160. .reg_offset = 3,
  161. .mask = DA9052_IRQ_MASK_POS_8,
  162. },
  163. };
  164. static const struct regmap_irq_chip da9052_regmap_irq_chip = {
  165. .name = "da9052_irq",
  166. .status_base = DA9052_EVENT_A_REG,
  167. .mask_base = DA9052_IRQ_MASK_A_REG,
  168. .ack_base = DA9052_EVENT_A_REG,
  169. .num_regs = DA9052_NUM_IRQ_REGS,
  170. .irqs = da9052_irqs,
  171. .num_irqs = ARRAY_SIZE(da9052_irqs),
  172. };
  173. static int da9052_map_irq(struct da9052 *da9052, int irq)
  174. {
  175. return regmap_irq_get_virq(da9052->irq_data, irq);
  176. }
  177. int da9052_enable_irq(struct da9052 *da9052, int irq)
  178. {
  179. irq = da9052_map_irq(da9052, irq);
  180. if (irq < 0)
  181. return irq;
  182. enable_irq(irq);
  183. return 0;
  184. }
  185. EXPORT_SYMBOL_GPL(da9052_enable_irq);
  186. int da9052_disable_irq(struct da9052 *da9052, int irq)
  187. {
  188. irq = da9052_map_irq(da9052, irq);
  189. if (irq < 0)
  190. return irq;
  191. disable_irq(irq);
  192. return 0;
  193. }
  194. EXPORT_SYMBOL_GPL(da9052_disable_irq);
  195. int da9052_disable_irq_nosync(struct da9052 *da9052, int irq)
  196. {
  197. irq = da9052_map_irq(da9052, irq);
  198. if (irq < 0)
  199. return irq;
  200. disable_irq_nosync(irq);
  201. return 0;
  202. }
  203. EXPORT_SYMBOL_GPL(da9052_disable_irq_nosync);
  204. int da9052_request_irq(struct da9052 *da9052, int irq, char *name,
  205. irq_handler_t handler, void *data)
  206. {
  207. irq = da9052_map_irq(da9052, irq);
  208. if (irq < 0)
  209. return irq;
  210. return request_threaded_irq(irq, NULL, handler,
  211. IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  212. name, data);
  213. }
  214. EXPORT_SYMBOL_GPL(da9052_request_irq);
  215. void da9052_free_irq(struct da9052 *da9052, int irq, void *data)
  216. {
  217. irq = da9052_map_irq(da9052, irq);
  218. if (irq < 0)
  219. return;
  220. free_irq(irq, data);
  221. }
  222. EXPORT_SYMBOL_GPL(da9052_free_irq);
  223. static irqreturn_t da9052_auxadc_irq(int irq, void *irq_data)
  224. {
  225. struct da9052 *da9052 = irq_data;
  226. complete(&da9052->done);
  227. return IRQ_HANDLED;
  228. }
  229. int da9052_irq_init(struct da9052 *da9052)
  230. {
  231. int ret;
  232. ret = regmap_add_irq_chip(da9052->regmap, da9052->chip_irq,
  233. IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  234. -1, &da9052_regmap_irq_chip,
  235. &da9052->irq_data);
  236. if (ret < 0) {
  237. dev_err(da9052->dev, "regmap_add_irq_chip failed: %d\n", ret);
  238. goto regmap_err;
  239. }
  240. enable_irq_wake(da9052->chip_irq);
  241. ret = da9052_request_irq(da9052, DA9052_IRQ_ADC_EOM, "adc-irq",
  242. da9052_auxadc_irq, da9052);
  243. if (ret != 0) {
  244. dev_err(da9052->dev, "DA9052_IRQ_ADC_EOM failed: %d\n", ret);
  245. goto request_irq_err;
  246. }
  247. return 0;
  248. request_irq_err:
  249. regmap_del_irq_chip(da9052->chip_irq, da9052->irq_data);
  250. regmap_err:
  251. return ret;
  252. }
  253. int da9052_irq_exit(struct da9052 *da9052)
  254. {
  255. da9052_free_irq(da9052, DA9052_IRQ_ADC_EOM, da9052);
  256. regmap_del_irq_chip(da9052->chip_irq, da9052->irq_data);
  257. return 0;
  258. }