arm_mhu.c 4.4 KB

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  1. /*
  2. * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
  3. * Copyright (C) 2015 Linaro Ltd.
  4. * Author: Jassi Brar <jaswinder.singh@linaro.org>
  5. *
  6. * This program is free software: you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation, version 2 of the License.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/interrupt.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/mutex.h>
  18. #include <linux/delay.h>
  19. #include <linux/slab.h>
  20. #include <linux/err.h>
  21. #include <linux/io.h>
  22. #include <linux/module.h>
  23. #include <linux/amba/bus.h>
  24. #include <linux/mailbox_controller.h>
  25. #define INTR_STAT_OFS 0x0
  26. #define INTR_SET_OFS 0x8
  27. #define INTR_CLR_OFS 0x10
  28. #define MHU_LP_OFFSET 0x0
  29. #define MHU_HP_OFFSET 0x20
  30. #define MHU_SEC_OFFSET 0x200
  31. #define TX_REG_OFFSET 0x100
  32. #define MHU_CHANS 3
  33. struct mhu_link {
  34. unsigned irq;
  35. void __iomem *tx_reg;
  36. void __iomem *rx_reg;
  37. };
  38. struct arm_mhu {
  39. void __iomem *base;
  40. struct mhu_link mlink[MHU_CHANS];
  41. struct mbox_chan chan[MHU_CHANS];
  42. struct mbox_controller mbox;
  43. };
  44. static irqreturn_t mhu_rx_interrupt(int irq, void *p)
  45. {
  46. struct mbox_chan *chan = p;
  47. struct mhu_link *mlink = chan->con_priv;
  48. u32 val;
  49. val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
  50. if (!val)
  51. return IRQ_NONE;
  52. mbox_chan_received_data(chan, (void *)&val);
  53. writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
  54. return IRQ_HANDLED;
  55. }
  56. static bool mhu_last_tx_done(struct mbox_chan *chan)
  57. {
  58. struct mhu_link *mlink = chan->con_priv;
  59. u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
  60. return (val == 0);
  61. }
  62. static int mhu_send_data(struct mbox_chan *chan, void *data)
  63. {
  64. struct mhu_link *mlink = chan->con_priv;
  65. u32 *arg = data;
  66. writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
  67. return 0;
  68. }
  69. static int mhu_startup(struct mbox_chan *chan)
  70. {
  71. struct mhu_link *mlink = chan->con_priv;
  72. u32 val;
  73. int ret;
  74. val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
  75. writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
  76. ret = request_irq(mlink->irq, mhu_rx_interrupt,
  77. IRQF_SHARED, "mhu_link", chan);
  78. if (ret) {
  79. dev_err(chan->mbox->dev,
  80. "Unable to acquire IRQ %d\n", mlink->irq);
  81. return ret;
  82. }
  83. return 0;
  84. }
  85. static void mhu_shutdown(struct mbox_chan *chan)
  86. {
  87. struct mhu_link *mlink = chan->con_priv;
  88. free_irq(mlink->irq, chan);
  89. }
  90. static const struct mbox_chan_ops mhu_ops = {
  91. .send_data = mhu_send_data,
  92. .startup = mhu_startup,
  93. .shutdown = mhu_shutdown,
  94. .last_tx_done = mhu_last_tx_done,
  95. };
  96. static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
  97. {
  98. int i, err;
  99. struct arm_mhu *mhu;
  100. struct device *dev = &adev->dev;
  101. int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
  102. /* Allocate memory for device */
  103. mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
  104. if (!mhu)
  105. return -ENOMEM;
  106. mhu->base = devm_ioremap_resource(dev, &adev->res);
  107. if (IS_ERR(mhu->base)) {
  108. dev_err(dev, "ioremap failed\n");
  109. return PTR_ERR(mhu->base);
  110. }
  111. for (i = 0; i < MHU_CHANS; i++) {
  112. mhu->chan[i].con_priv = &mhu->mlink[i];
  113. mhu->mlink[i].irq = adev->irq[i];
  114. mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];
  115. mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
  116. }
  117. mhu->mbox.dev = dev;
  118. mhu->mbox.chans = &mhu->chan[0];
  119. mhu->mbox.num_chans = MHU_CHANS;
  120. mhu->mbox.ops = &mhu_ops;
  121. mhu->mbox.txdone_irq = false;
  122. mhu->mbox.txdone_poll = true;
  123. mhu->mbox.txpoll_period = 1;
  124. amba_set_drvdata(adev, mhu);
  125. err = mbox_controller_register(&mhu->mbox);
  126. if (err) {
  127. dev_err(dev, "Failed to register mailboxes %d\n", err);
  128. return err;
  129. }
  130. dev_info(dev, "ARM MHU Mailbox registered\n");
  131. return 0;
  132. }
  133. static int mhu_remove(struct amba_device *adev)
  134. {
  135. struct arm_mhu *mhu = amba_get_drvdata(adev);
  136. mbox_controller_unregister(&mhu->mbox);
  137. return 0;
  138. }
  139. static struct amba_id mhu_ids[] = {
  140. {
  141. .id = 0x1bb098,
  142. .mask = 0xffffff,
  143. },
  144. { 0, 0 },
  145. };
  146. MODULE_DEVICE_TABLE(amba, mhu_ids);
  147. static struct amba_driver arm_mhu_driver = {
  148. .drv = {
  149. .name = "mhu",
  150. },
  151. .id_table = mhu_ids,
  152. .probe = mhu_probe,
  153. .remove = mhu_remove,
  154. };
  155. module_amba_driver(arm_mhu_driver);
  156. MODULE_LICENSE("GPL v2");
  157. MODULE_DESCRIPTION("ARM MHU Driver");
  158. MODULE_AUTHOR("Jassi Brar <jassisinghbrar@gmail.com>");