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omap_ssi_regs.h

omap_ssi_regs.h 6.2 KB
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  1. /* Hardware definitions for SSI.
    2. 

  2.  *
    3. 

  3.  * Copyright (C) 2010 Nokia Corporation. All rights reserved.
    4. 

  4.  *
    5. 

  5.  * Contact: Carlos Chinea <carlos.chinea@nokia.com>
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or
    8. 

  8.  * modify it under the terms of the GNU General Public License
    9. 

  9.  * version 2 as published by the Free Software Foundation.
    10. 

  10.  *
    11. 

  11.  * This program is distributed in the hope that it will be useful, but
    12. 

  12.  * WITHOUT ANY WARRANTY; without even the implied warranty of
    13. 

  13.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
    14. 

  14.  * General Public License for more details.
    15. 

  15.  *
    16. 

  16.  * You should have received a copy of the GNU General Public License
    17. 

  17.  * along with this program; if not, write to the Free Software
    18. 

  18.  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
    19. 

  19.  * 02110-1301 USA
    20. 

  20.  */
    21. 

  21. 

  22. #ifndef __OMAP_SSI_REGS_H__
    23. 

  23. #define __OMAP_SSI_REGS_H__
    24. 

  24. 

  25. /*
    26. 

  26.  * SSI SYS registers
    27. 

  27.  */
    28. 

  28. #define SSI_REVISION_REG    0
    29. 

  29. #  define SSI_REV_MAJOR    0xf0
    30. 

  30. #  define SSI_REV_MINOR    0xf
    31. 

  31. #define SSI_SYSCONFIG_REG    0x10
    32. 

  32. #  define SSI_AUTOIDLE    (1 << 0)
    33. 

  33. #  define SSI_SOFTRESET    (1 << 1)
    34. 

  34. #  define SSI_SIDLEMODE_FORCE  0
    35. 

  35. #  define SSI_SIDLEMODE_NO    (1 << 3)
    36. 

  36. #  define SSI_SIDLEMODE_SMART  (1 << 4)
    37. 

  37. #  define SSI_SIDLEMODE_MASK  0x18
    38. 

  38. #  define SSI_MIDLEMODE_FORCE  0
    39. 

  39. #  define SSI_MIDLEMODE_NO    (1 << 12)
    40. 

  40. #  define SSI_MIDLEMODE_SMART  (1 << 13)
    41. 

  41. #  define SSI_MIDLEMODE_MASK  0x3000
    42. 

  42. #define SSI_SYSSTATUS_REG    0x14
    43. 

  43. #  define SSI_RESETDONE    1
    44. 

  44. #define SSI_MPU_STATUS_REG(port, irq)  (0x808 + ((port) * 0x10) + ((irq) * 2))
    45. 

  45. #define SSI_MPU_ENABLE_REG(port, irq)  (0x80c + ((port) * 0x10) + ((irq) * 8))
    46. 

  46. #  define SSI_DATAACCEPT(channel)    (1 << (channel))
    47. 

  47. #  define SSI_DATAAVAILABLE(channel)  (1 << ((channel) + 8))
    48. 

  48. #  define SSI_DATAOVERRUN(channel)    (1 << ((channel) + 16))
    49. 

  49. #  define SSI_ERROROCCURED      (1 << 24)
    50. 

  50. #  define SSI_BREAKDETECTED    (1 << 25)
    51. 

  51. #define SSI_GDD_MPU_IRQ_STATUS_REG  0x0800
    52. 

  52. #define SSI_GDD_MPU_IRQ_ENABLE_REG  0x0804
    53. 

  53. #  define SSI_GDD_LCH(channel)  (1 << (channel))
    54. 

  54. #define SSI_WAKE_REG(port)    (0xc00 + ((port) * 0x10))
    55. 

  55. #define SSI_CLEAR_WAKE_REG(port)  (0xc04 + ((port) * 0x10))
    56. 

  56. #define SSI_SET_WAKE_REG(port)    (0xc08 + ((port) * 0x10))
    57. 

  57. #  define SSI_WAKE(channel)  (1 << (channel))
    58. 

  58. #  define SSI_WAKE_MASK    0xff
    59. 

  59. 

  60. /*
    61. 

  61.  * SSI SST registers
    62. 

  62.  */
    63. 

  63. #define SSI_SST_ID_REG      0
    64. 

  64. #define SSI_SST_MODE_REG    4
    65. 

  65. #  define SSI_MODE_VAL_MASK  3
    66. 

  66. #  define SSI_MODE_SLEEP    0
    67. 

  67. #  define SSI_MODE_STREAM    1
    68. 

  68. #  define SSI_MODE_FRAME    2
    69. 

  69. #  define SSI_MODE_MULTIPOINTS  3
    70. 

  70. #define SSI_SST_FRAMESIZE_REG    8
    71. 

  71. #  define SSI_FRAMESIZE_DEFAULT  31
    72. 

  72. #define SSI_SST_TXSTATE_REG    0xc
    73. 

  73. #  define  SSI_TXSTATE_IDLE  0
    74. 

  74. #define SSI_SST_BUFSTATE_REG    0x10
    75. 

  75. #  define  SSI_FULL(channel)  (1 << (channel))
    76. 

  76. #define SSI_SST_DIVISOR_REG    0x18
    77. 

  77. #  define SSI_MAX_DIVISOR    127
    78. 

  78. #define SSI_SST_BREAK_REG    0x20
    79. 

  79. #define SSI_SST_CHANNELS_REG    0x24
    80. 

  80. #  define SSI_CHANNELS_DEFAULT  4
    81. 

  81. #define SSI_SST_ARBMODE_REG    0x28
    82. 

  82. #  define SSI_ARBMODE_ROUNDROBIN  0
    83. 

  83. #  define SSI_ARBMODE_PRIORITY  1
    84. 

  84. #define SSI_SST_BUFFER_CH_REG(channel)  (0x80 + ((channel) * 4))
    85. 

  85. #define SSI_SST_SWAPBUF_CH_REG(channel)  (0xc0 + ((channel) * 4))
    86. 

  86. 

  87. /*
    88. 

  88.  * SSI SSR registers
    89. 

  89.  */
    90. 

  90. #define SSI_SSR_ID_REG      0
    91. 

  91. #define SSI_SSR_MODE_REG    4
    92. 

  92. #define SSI_SSR_FRAMESIZE_REG    8
    93. 

  93. #define SSI_SSR_RXSTATE_REG    0xc
    94. 

  94. #define SSI_SSR_BUFSTATE_REG    0x10
    95. 

  95. #  define SSI_NOTEMPTY(channel)  (1 << (channel))
    96. 

  96. #define SSI_SSR_BREAK_REG    0x1c
    97. 

  97. #define SSI_SSR_ERROR_REG    0x20
    98. 

  98. #define SSI_SSR_ERRORACK_REG    0x24
    99. 

  99. #define SSI_SSR_OVERRUN_REG    0x2c
    100. 

  100. #define SSI_SSR_OVERRUNACK_REG    0x30
    101. 

  101. #define SSI_SSR_TIMEOUT_REG    0x34
    102. 

  102. #  define SSI_TIMEOUT_DEFAULT  0
    103. 

  103. #define SSI_SSR_CHANNELS_REG    0x28
    104. 

  104. #define SSI_SSR_BUFFER_CH_REG(channel)  (0x80 + ((channel) * 4))
    105. 

  105. #define SSI_SSR_SWAPBUF_CH_REG(channel)  (0xc0 + ((channel) * 4))
    106. 

  106. 

  107. /*
    108. 

  108.  * SSI GDD registers
    109. 

  109.  */
    110. 

  110. #define SSI_GDD_HW_ID_REG    0
    111. 

  111. #define SSI_GDD_PPORT_ID_REG    0x10
    112. 

  112. #define SSI_GDD_MPORT_ID_REG    0x14
    113. 

  113. #define SSI_GDD_PPORT_SR_REG    0x20
    114. 

  114. #define SSI_GDD_MPORT_SR_REG    0x24
    115. 

  115. #  define SSI_ACTIVE_LCH_NUM_MASK  0xff
    116. 

  116. #define SSI_GDD_TEST_REG    0x40
    117. 

  117. #  define SSI_TEST      1
    118. 

  118. #define SSI_GDD_GCR_REG      0x100
    119. 

  119. #  define  SSI_CLK_AUTOGATING_ON  (1 << 3)
    120. 

  120. #  define  SSI_FREE    (1 << 2)
    121. 

  121. #  define  SSI_SWITCH_OFF    (1 << 0)
    122. 

  122. #define SSI_GDD_GRST_REG    0x200
    123. 

  123. #  define SSI_SWRESET    1
    124. 

  124. #define SSI_GDD_CSDP_REG(channel)  (0x800 + ((channel) * 0x40))
    125. 

  125. #  define SSI_DST_BURST_EN_MASK  0xc000
    126. 

  126. #  define SSI_DST_SINGLE_ACCESS0  0
    127. 

  127. #  define SSI_DST_SINGLE_ACCESS  (1 << 14)
    128. 

  128. #  define SSI_DST_BURST_4x32_BIT  (2 << 14)
    129. 

  129. #  define SSI_DST_BURST_8x32_BIT  (3 << 14)
    130. 

  130. #  define SSI_DST_MASK    0x1e00
    131. 

  131. #  define SSI_DST_MEMORY_PORT  (8 << 9)
    132. 

  132. #  define SSI_DST_PERIPHERAL_PORT  (9 << 9)
    133. 

  133. #  define SSI_SRC_BURST_EN_MASK  0x180
    134. 

  134. #  define SSI_SRC_SINGLE_ACCESS0  0
    135. 

  135. #  define SSI_SRC_SINGLE_ACCESS  (1 << 7)
    136. 

  136. #  define SSI_SRC_BURST_4x32_BIT  (2 << 7)
    137. 

  137. #  define SSI_SRC_BURST_8x32_BIT  (3 << 7)
    138. 

  138. #  define SSI_SRC_MASK    0x3c
    139. 

  139. #  define SSI_SRC_MEMORY_PORT  (8 << 2)
    140. 

  140. #  define SSI_SRC_PERIPHERAL_PORT  (9 << 2)
    141. 

  141. #  define SSI_DATA_TYPE_MASK  3
    142. 

  142. #  define SSI_DATA_TYPE_S32  2
    143. 

  143. #define SSI_GDD_CCR_REG(channel)  (0x802 + ((channel) * 0x40))
    144. 

  144. #  define SSI_DST_AMODE_MASK  (3 << 14)
    145. 

  145. #  define SSI_DST_AMODE_CONST  0
    146. 

  146. #  define SSI_DST_AMODE_POSTINC  (1 << 12)
    147. 

  147. #  define SSI_SRC_AMODE_MASK  (3 << 12)
    148. 

  148. #  define SSI_SRC_AMODE_CONST  0
    149. 

  149. #  define SSI_SRC_AMODE_POSTINC  (1 << 12)
    150. 

  150. #  define SSI_CCR_ENABLE    (1 << 7)
    151. 

  151. #  define SSI_CCR_SYNC_MASK  0x1f
    152. 

  152. #define SSI_GDD_CICR_REG(channel)  (0x804 + ((channel) * 0x40))
    153. 

  153. #  define SSI_BLOCK_IE    (1 << 5)
    154. 

  154. #  define SSI_HALF_IE    (1 << 2)
    155. 

  155. #  define SSI_TOUT_IE    (1 << 0)
    156. 

  156. #define SSI_GDD_CSR_REG(channel)  (0x806 + ((channel) * 0x40))
    157. 

  157. #  define SSI_CSR_SYNC    (1 << 6)
    158. 

  158. #  define SSI_CSR_BLOCK    (1 << 5)
    159. 

  159. #  define SSI_CSR_HALF    (1 << 2)
    160. 

  160. #  define SSI_CSR_TOUR    (1 << 0)
    161. 

  161. #define SSI_GDD_CSSA_REG(channel)  (0x808 + ((channel) * 0x40))
    162. 

  162. #define SSI_GDD_CDSA_REG(channel)  (0x80c + ((channel) * 0x40))
    163. 

  163. #define SSI_GDD_CEN_REG(channel)  (0x810 + ((channel) * 0x40))
    164. 

  164. #define SSI_GDD_CSAC_REG(channel)  (0x818 + ((channel) * 0x40))
    165. 

  165. #define SSI_GDD_CDAC_REG(channel)  (0x81a + ((channel) * 0x40))
    166. 

  166. #define SSI_GDD_CLNK_CTRL_REG(channel)  (0x828 + ((channel) * 0x40))
    167. 

  167. #  define SSI_ENABLE_LNK    (1 << 15)
    168. 

  168. #  define SSI_STOP_LNK    (1 << 14)
    169. 

  169. #  define SSI_NEXT_CH_ID_MASK  0xf
    170. 

  170. 

  171. #endif /* __OMAP_SSI_REGS_H__ */
    172. 

  172.