regs_64.S 4.0 KB

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  1. /*
  2. * Copyright 2011 Tilera Corporation. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation, version 2.
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11. * NON INFRINGEMENT. See the GNU General Public License for
  12. * more details.
  13. */
  14. #include <linux/linkage.h>
  15. #include <asm/ptrace.h>
  16. #include <asm/asm-offsets.h>
  17. #include <arch/spr_def.h>
  18. #include <asm/processor.h>
  19. #include <asm/switch_to.h>
  20. /*
  21. * See <asm/switch_to.h>; called with prev and next task_struct pointers.
  22. * "prev" is returned in r0 for _switch_to and also for ret_from_fork.
  23. *
  24. * We want to save pc/sp in "prev", and get the new pc/sp from "next".
  25. * We also need to save all the callee-saved registers on the stack.
  26. *
  27. * Intel enables/disables access to the hardware cycle counter in
  28. * seccomp (secure computing) environments if necessary, based on
  29. * has_secure_computing(). We might want to do this at some point,
  30. * though it would require virtualizing the other SPRs under WORLD_ACCESS.
  31. *
  32. * Since we're saving to the stack, we omit sp from this list.
  33. * And for parallels with other architectures, we save lr separately,
  34. * in the thread_struct itself (as the "pc" field).
  35. *
  36. * This code also needs to be aligned with process.c copy_thread()
  37. */
  38. #if CALLEE_SAVED_REGS_COUNT != 24
  39. # error Mismatch between <asm/switch_to.h> and kernel/entry.S
  40. #endif
  41. #define FRAME_SIZE ((2 + CALLEE_SAVED_REGS_COUNT) * 8)
  42. #define SAVE_REG(r) { st r12, r; addi r12, r12, 8 }
  43. #define LOAD_REG(r) { ld r, r12; addi r12, r12, 8 }
  44. #define FOR_EACH_CALLEE_SAVED_REG(f) \
  45. f(r30); f(r31); \
  46. f(r32); f(r33); f(r34); f(r35); f(r36); f(r37); f(r38); f(r39); \
  47. f(r40); f(r41); f(r42); f(r43); f(r44); f(r45); f(r46); f(r47); \
  48. f(r48); f(r49); f(r50); f(r51); f(r52);
  49. STD_ENTRY_SECTION(__switch_to, .sched.text)
  50. {
  51. move r10, sp
  52. st sp, lr
  53. }
  54. {
  55. addli r11, sp, -FRAME_SIZE + 8
  56. addli sp, sp, -FRAME_SIZE
  57. }
  58. {
  59. st r11, r10
  60. addli r4, r1, TASK_STRUCT_THREAD_KSP_OFFSET
  61. }
  62. {
  63. ld r13, r4 /* Load new sp to a temp register early. */
  64. addi r12, sp, 16
  65. }
  66. FOR_EACH_CALLEE_SAVED_REG(SAVE_REG)
  67. addli r3, r0, TASK_STRUCT_THREAD_KSP_OFFSET
  68. {
  69. st r3, sp
  70. addli r3, r0, TASK_STRUCT_THREAD_PC_OFFSET
  71. }
  72. {
  73. st r3, lr
  74. addli r4, r1, TASK_STRUCT_THREAD_PC_OFFSET
  75. }
  76. {
  77. ld lr, r4
  78. addi r12, r13, 16
  79. }
  80. {
  81. /* Update sp and ksp0 simultaneously to avoid backtracer warnings. */
  82. move sp, r13
  83. mtspr SPR_SYSTEM_SAVE_K_0, r2
  84. }
  85. FOR_EACH_CALLEE_SAVED_REG(LOAD_REG)
  86. .L__switch_to_pc:
  87. {
  88. addli sp, sp, FRAME_SIZE
  89. jrp lr /* r0 is still valid here, so return it */
  90. }
  91. STD_ENDPROC(__switch_to)
  92. /* Return a suitable address for the backtracer for suspended threads */
  93. STD_ENTRY_SECTION(get_switch_to_pc, .sched.text)
  94. lnk r0
  95. {
  96. addli r0, r0, .L__switch_to_pc - .
  97. jrp lr
  98. }
  99. STD_ENDPROC(get_switch_to_pc)
  100. STD_ENTRY(get_pt_regs)
  101. .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
  102. r8, r9, r10, r11, r12, r13, r14, r15, \
  103. r16, r17, r18, r19, r20, r21, r22, r23, \
  104. r24, r25, r26, r27, r28, r29, r30, r31, \
  105. r32, r33, r34, r35, r36, r37, r38, r39, \
  106. r40, r41, r42, r43, r44, r45, r46, r47, \
  107. r48, r49, r50, r51, r52, tp, sp
  108. {
  109. st r0, \reg
  110. addi r0, r0, 8
  111. }
  112. .endr
  113. {
  114. st r0, lr
  115. addi r0, r0, PTREGS_OFFSET_PC - PTREGS_OFFSET_LR
  116. }
  117. lnk r1
  118. {
  119. st r0, r1
  120. addi r0, r0, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
  121. }
  122. mfspr r1, INTERRUPT_CRITICAL_SECTION
  123. shli r1, r1, SPR_EX_CONTEXT_1_1__ICS_SHIFT
  124. ori r1, r1, KERNEL_PL
  125. {
  126. st r0, r1
  127. addi r0, r0, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
  128. }
  129. {
  130. st r0, zero /* clear faultnum */
  131. addi r0, r0, PTREGS_OFFSET_ORIG_R0 - PTREGS_OFFSET_FAULTNUM
  132. }
  133. {
  134. st r0, zero /* clear orig_r0 */
  135. addli r0, r0, -PTREGS_OFFSET_ORIG_R0 /* restore r0 to base */
  136. }
  137. jrp lr
  138. STD_ENDPROC(get_pt_regs)