cache.c 9.5 KB

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  1. /*
  2. * arch/sh/mm/cache.c
  3. *
  4. * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
  5. * Copyright (C) 2002 - 2010 Paul Mundt
  6. *
  7. * Released under the terms of the GNU GPL v2.0.
  8. */
  9. #include <linux/mm.h>
  10. #include <linux/init.h>
  11. #include <linux/mutex.h>
  12. #include <linux/fs.h>
  13. #include <linux/smp.h>
  14. #include <linux/highmem.h>
  15. #include <linux/module.h>
  16. #include <asm/mmu_context.h>
  17. #include <asm/cacheflush.h>
  18. void (*local_flush_cache_all)(void *args) = cache_noop;
  19. void (*local_flush_cache_mm)(void *args) = cache_noop;
  20. void (*local_flush_cache_dup_mm)(void *args) = cache_noop;
  21. void (*local_flush_cache_page)(void *args) = cache_noop;
  22. void (*local_flush_cache_range)(void *args) = cache_noop;
  23. void (*local_flush_dcache_page)(void *args) = cache_noop;
  24. void (*local_flush_icache_range)(void *args) = cache_noop;
  25. void (*local_flush_icache_page)(void *args) = cache_noop;
  26. void (*local_flush_cache_sigtramp)(void *args) = cache_noop;
  27. void (*__flush_wback_region)(void *start, int size);
  28. EXPORT_SYMBOL(__flush_wback_region);
  29. void (*__flush_purge_region)(void *start, int size);
  30. EXPORT_SYMBOL(__flush_purge_region);
  31. void (*__flush_invalidate_region)(void *start, int size);
  32. EXPORT_SYMBOL(__flush_invalidate_region);
  33. static inline void noop__flush_region(void *start, int size)
  34. {
  35. }
  36. static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info,
  37. int wait)
  38. {
  39. preempt_disable();
  40. /* Needing IPI for cross-core flush is SHX3-specific. */
  41. #ifdef CONFIG_CPU_SHX3
  42. /*
  43. * It's possible that this gets called early on when IRQs are
  44. * still disabled due to ioremapping by the boot CPU, so don't
  45. * even attempt IPIs unless there are other CPUs online.
  46. */
  47. if (num_online_cpus() > 1)
  48. smp_call_function(func, info, wait);
  49. #endif
  50. func(info);
  51. preempt_enable();
  52. }
  53. void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
  54. unsigned long vaddr, void *dst, const void *src,
  55. unsigned long len)
  56. {
  57. if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
  58. test_bit(PG_dcache_clean, &page->flags)) {
  59. void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
  60. memcpy(vto, src, len);
  61. kunmap_coherent(vto);
  62. } else {
  63. memcpy(dst, src, len);
  64. if (boot_cpu_data.dcache.n_aliases)
  65. clear_bit(PG_dcache_clean, &page->flags);
  66. }
  67. if (vma->vm_flags & VM_EXEC)
  68. flush_cache_page(vma, vaddr, page_to_pfn(page));
  69. }
  70. void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
  71. unsigned long vaddr, void *dst, const void *src,
  72. unsigned long len)
  73. {
  74. if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
  75. test_bit(PG_dcache_clean, &page->flags)) {
  76. void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
  77. memcpy(dst, vfrom, len);
  78. kunmap_coherent(vfrom);
  79. } else {
  80. memcpy(dst, src, len);
  81. if (boot_cpu_data.dcache.n_aliases)
  82. clear_bit(PG_dcache_clean, &page->flags);
  83. }
  84. }
  85. void copy_user_highpage(struct page *to, struct page *from,
  86. unsigned long vaddr, struct vm_area_struct *vma)
  87. {
  88. void *vfrom, *vto;
  89. vto = kmap_atomic(to);
  90. if (boot_cpu_data.dcache.n_aliases && page_mapcount(from) &&
  91. test_bit(PG_dcache_clean, &from->flags)) {
  92. vfrom = kmap_coherent(from, vaddr);
  93. copy_page(vto, vfrom);
  94. kunmap_coherent(vfrom);
  95. } else {
  96. vfrom = kmap_atomic(from);
  97. copy_page(vto, vfrom);
  98. kunmap_atomic(vfrom);
  99. }
  100. if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK) ||
  101. (vma->vm_flags & VM_EXEC))
  102. __flush_purge_region(vto, PAGE_SIZE);
  103. kunmap_atomic(vto);
  104. /* Make sure this page is cleared on other CPU's too before using it */
  105. smp_wmb();
  106. }
  107. EXPORT_SYMBOL(copy_user_highpage);
  108. void clear_user_highpage(struct page *page, unsigned long vaddr)
  109. {
  110. void *kaddr = kmap_atomic(page);
  111. clear_page(kaddr);
  112. if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK))
  113. __flush_purge_region(kaddr, PAGE_SIZE);
  114. kunmap_atomic(kaddr);
  115. }
  116. EXPORT_SYMBOL(clear_user_highpage);
  117. void __update_cache(struct vm_area_struct *vma,
  118. unsigned long address, pte_t pte)
  119. {
  120. struct page *page;
  121. unsigned long pfn = pte_pfn(pte);
  122. if (!boot_cpu_data.dcache.n_aliases)
  123. return;
  124. page = pfn_to_page(pfn);
  125. if (pfn_valid(pfn)) {
  126. int dirty = !test_and_set_bit(PG_dcache_clean, &page->flags);
  127. if (dirty)
  128. __flush_purge_region(page_address(page), PAGE_SIZE);
  129. }
  130. }
  131. void __flush_anon_page(struct page *page, unsigned long vmaddr)
  132. {
  133. unsigned long addr = (unsigned long) page_address(page);
  134. if (pages_do_alias(addr, vmaddr)) {
  135. if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
  136. test_bit(PG_dcache_clean, &page->flags)) {
  137. void *kaddr;
  138. kaddr = kmap_coherent(page, vmaddr);
  139. /* XXX.. For now kunmap_coherent() does a purge */
  140. /* __flush_purge_region((void *)kaddr, PAGE_SIZE); */
  141. kunmap_coherent(kaddr);
  142. } else
  143. __flush_purge_region((void *)addr, PAGE_SIZE);
  144. }
  145. }
  146. void flush_cache_all(void)
  147. {
  148. cacheop_on_each_cpu(local_flush_cache_all, NULL, 1);
  149. }
  150. EXPORT_SYMBOL(flush_cache_all);
  151. void flush_cache_mm(struct mm_struct *mm)
  152. {
  153. if (boot_cpu_data.dcache.n_aliases == 0)
  154. return;
  155. cacheop_on_each_cpu(local_flush_cache_mm, mm, 1);
  156. }
  157. void flush_cache_dup_mm(struct mm_struct *mm)
  158. {
  159. if (boot_cpu_data.dcache.n_aliases == 0)
  160. return;
  161. cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1);
  162. }
  163. void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
  164. unsigned long pfn)
  165. {
  166. struct flusher_data data;
  167. data.vma = vma;
  168. data.addr1 = addr;
  169. data.addr2 = pfn;
  170. cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1);
  171. }
  172. void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
  173. unsigned long end)
  174. {
  175. struct flusher_data data;
  176. data.vma = vma;
  177. data.addr1 = start;
  178. data.addr2 = end;
  179. cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1);
  180. }
  181. EXPORT_SYMBOL(flush_cache_range);
  182. void flush_dcache_page(struct page *page)
  183. {
  184. cacheop_on_each_cpu(local_flush_dcache_page, page, 1);
  185. }
  186. EXPORT_SYMBOL(flush_dcache_page);
  187. void flush_icache_range(unsigned long start, unsigned long end)
  188. {
  189. struct flusher_data data;
  190. data.vma = NULL;
  191. data.addr1 = start;
  192. data.addr2 = end;
  193. cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
  194. }
  195. EXPORT_SYMBOL(flush_icache_range);
  196. void flush_icache_page(struct vm_area_struct *vma, struct page *page)
  197. {
  198. /* Nothing uses the VMA, so just pass the struct page along */
  199. cacheop_on_each_cpu(local_flush_icache_page, page, 1);
  200. }
  201. void flush_cache_sigtramp(unsigned long address)
  202. {
  203. cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1);
  204. }
  205. static void compute_alias(struct cache_info *c)
  206. {
  207. #ifdef CONFIG_MMU
  208. c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
  209. #else
  210. c->alias_mask = 0;
  211. #endif
  212. c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
  213. }
  214. static void __init emit_cache_params(void)
  215. {
  216. printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
  217. boot_cpu_data.icache.ways,
  218. boot_cpu_data.icache.sets,
  219. boot_cpu_data.icache.way_incr);
  220. printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
  221. boot_cpu_data.icache.entry_mask,
  222. boot_cpu_data.icache.alias_mask,
  223. boot_cpu_data.icache.n_aliases);
  224. printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
  225. boot_cpu_data.dcache.ways,
  226. boot_cpu_data.dcache.sets,
  227. boot_cpu_data.dcache.way_incr);
  228. printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
  229. boot_cpu_data.dcache.entry_mask,
  230. boot_cpu_data.dcache.alias_mask,
  231. boot_cpu_data.dcache.n_aliases);
  232. /*
  233. * Emit Secondary Cache parameters if the CPU has a probed L2.
  234. */
  235. if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
  236. printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
  237. boot_cpu_data.scache.ways,
  238. boot_cpu_data.scache.sets,
  239. boot_cpu_data.scache.way_incr);
  240. printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
  241. boot_cpu_data.scache.entry_mask,
  242. boot_cpu_data.scache.alias_mask,
  243. boot_cpu_data.scache.n_aliases);
  244. }
  245. }
  246. void __init cpu_cache_init(void)
  247. {
  248. unsigned int cache_disabled = 0;
  249. #ifdef SH_CCR
  250. cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE);
  251. #endif
  252. compute_alias(&boot_cpu_data.icache);
  253. compute_alias(&boot_cpu_data.dcache);
  254. compute_alias(&boot_cpu_data.scache);
  255. __flush_wback_region = noop__flush_region;
  256. __flush_purge_region = noop__flush_region;
  257. __flush_invalidate_region = noop__flush_region;
  258. /*
  259. * No flushing is necessary in the disabled cache case so we can
  260. * just keep the noop functions in local_flush_..() and __flush_..()
  261. */
  262. if (unlikely(cache_disabled))
  263. goto skip;
  264. if (boot_cpu_data.type == CPU_J2) {
  265. extern void __weak j2_cache_init(void);
  266. j2_cache_init();
  267. } else if (boot_cpu_data.family == CPU_FAMILY_SH2) {
  268. extern void __weak sh2_cache_init(void);
  269. sh2_cache_init();
  270. }
  271. if (boot_cpu_data.family == CPU_FAMILY_SH2A) {
  272. extern void __weak sh2a_cache_init(void);
  273. sh2a_cache_init();
  274. }
  275. if (boot_cpu_data.family == CPU_FAMILY_SH3) {
  276. extern void __weak sh3_cache_init(void);
  277. sh3_cache_init();
  278. if ((boot_cpu_data.type == CPU_SH7705) &&
  279. (boot_cpu_data.dcache.sets == 512)) {
  280. extern void __weak sh7705_cache_init(void);
  281. sh7705_cache_init();
  282. }
  283. }
  284. if ((boot_cpu_data.family == CPU_FAMILY_SH4) ||
  285. (boot_cpu_data.family == CPU_FAMILY_SH4A) ||
  286. (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
  287. extern void __weak sh4_cache_init(void);
  288. sh4_cache_init();
  289. if ((boot_cpu_data.type == CPU_SH7786) ||
  290. (boot_cpu_data.type == CPU_SHX3)) {
  291. extern void __weak shx3_cache_init(void);
  292. shx3_cache_init();
  293. }
  294. }
  295. if (boot_cpu_data.family == CPU_FAMILY_SH5) {
  296. extern void __weak sh5_cache_init(void);
  297. sh5_cache_init();
  298. }
  299. skip:
  300. emit_cache_params();
  301. }