tlb-miss.S 4.0 KB

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  1. /*
  2. * arch/score/mm/tlbex.S
  3. *
  4. * Score Processor version.
  5. *
  6. * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
  7. * Lennox Wu <lennox.wu@sunplusct.com>
  8. * Chen Liqin <liqin.chen@sunplusct.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, see the file COPYING, or write
  22. * to the Free Software Foundation, Inc.,
  23. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  24. */
  25. #include <asm/asmmacro.h>
  26. #include <asm/pgtable-bits.h>
  27. #include <asm/scoreregs.h>
  28. /*
  29. * After this macro runs, the pte faulted on is
  30. * in register PTE, a ptr into the table in which
  31. * the pte belongs is in PTR.
  32. */
  33. .macro load_pte, pte, ptr
  34. la \ptr, pgd_current
  35. lw \ptr, [\ptr, 0]
  36. mfcr \pte, cr6
  37. srli \pte, \pte, 22
  38. slli \pte, \pte, 2
  39. add \ptr, \ptr, \pte
  40. lw \ptr, [\ptr, 0]
  41. mfcr \pte, cr6
  42. srli \pte, \pte, 10
  43. andi \pte, 0xffc
  44. add \ptr, \ptr, \pte
  45. lw \pte, [\ptr, 0]
  46. .endm
  47. .macro pte_reload, ptr
  48. lw \ptr, [\ptr, 0]
  49. mtcr \ptr, cr12
  50. nop
  51. nop
  52. nop
  53. nop
  54. nop
  55. .endm
  56. .macro do_fault, write
  57. SAVE_ALL
  58. mfcr r6, cr6
  59. mv r4, r0
  60. ldi r5, \write
  61. la r8, do_page_fault
  62. brl r8
  63. j ret_from_exception
  64. .endm
  65. .macro pte_writable, pte, ptr, label
  66. andi \pte, 0x280
  67. cmpi.c \pte, 0x280
  68. bne \label
  69. lw \pte, [\ptr, 0] /*reload PTE*/
  70. .endm
  71. /*
  72. * Make PTE writable, update software status bits as well,
  73. * then store at PTR.
  74. */
  75. .macro pte_makewrite, pte, ptr
  76. ori \pte, 0x426
  77. sw \pte, [\ptr, 0]
  78. .endm
  79. .text
  80. ENTRY(score7_FTLB_refill_Handler)
  81. la r31, pgd_current /* get pgd pointer */
  82. lw r31, [r31, 0] /* get the address of PGD */
  83. mfcr r30, cr6
  84. srli r30, r30, 22 /* PGDIR_SHIFT = 22*/
  85. slli r30, r30, 2
  86. add r31, r31, r30
  87. lw r31, [r31, 0] /* get the address of the start address of PTE table */
  88. mfcr r30, cr9
  89. andi r30, 0xfff /* equivalent to get PET index and right shift 2 bits */
  90. add r31, r31, r30
  91. lw r30, [r31, 0] /* load pte entry */
  92. mtcr r30, cr12
  93. nop
  94. nop
  95. nop
  96. nop
  97. nop
  98. mtrtlb
  99. nop
  100. nop
  101. nop
  102. nop
  103. nop
  104. rte /* 6 cycles to make sure tlb entry works */
  105. ENTRY(score7_KSEG_refill_Handler)
  106. la r31, pgd_current /* get pgd pointer */
  107. lw r31, [r31, 0] /* get the address of PGD */
  108. mfcr r30, cr6
  109. srli r30, r30, 22 /* PGDIR_SHIFT = 22 */
  110. slli r30, r30, 2
  111. add r31, r31, r30
  112. lw r31, [r31, 0] /* get the address of the start address of PTE table */
  113. mfcr r30, cr6 /* get Bad VPN */
  114. srli r30, r30, 10
  115. andi r30, 0xffc /* PTE VPN mask (bit 11~2) */
  116. add r31, r31, r30
  117. lw r30, [r31, 0] /* load pte entry */
  118. mtcr r30, cr12
  119. nop
  120. nop
  121. nop
  122. nop
  123. nop
  124. mtrtlb
  125. nop
  126. nop
  127. nop
  128. nop
  129. nop
  130. rte /* 6 cycles to make sure tlb entry works */
  131. nopage_tlbl:
  132. do_fault 0 /* Read */
  133. ENTRY(handle_tlb_refill)
  134. load_pte r30, r31
  135. pte_writable r30, r31, handle_tlb_refill_nopage
  136. pte_makewrite r30, r31 /* Access|Modify|Dirty|Valid */
  137. pte_reload r31
  138. mtrtlb
  139. nop
  140. nop
  141. nop
  142. nop
  143. nop
  144. rte
  145. handle_tlb_refill_nopage:
  146. do_fault 0 /* Read */
  147. ENTRY(handle_tlb_invaild)
  148. load_pte r30, r31
  149. stlb /* find faulting entry */
  150. pte_writable r30, r31, handle_tlb_invaild_nopage
  151. pte_makewrite r30, r31 /* Access|Modify|Dirty|Valid */
  152. pte_reload r31
  153. mtptlb
  154. nop
  155. nop
  156. nop
  157. nop
  158. nop
  159. rte
  160. handle_tlb_invaild_nopage:
  161. do_fault 0 /* Read */
  162. ENTRY(handle_mod)
  163. load_pte r30, r31
  164. stlb /* find faulting entry */
  165. andi r30, _PAGE_WRITE /* Writable? */
  166. cmpz.c r30
  167. beq nowrite_mod
  168. lw r30, [r31, 0] /* reload into r30 */
  169. /* Present and writable bits set, set accessed and dirty bits. */
  170. pte_makewrite r30, r31
  171. /* Now reload the entry into the tlb. */
  172. pte_reload r31
  173. mtptlb
  174. nop
  175. nop
  176. nop
  177. nop
  178. nop
  179. rte
  180. nowrite_mod:
  181. do_fault 1 /* Write */