pci-common.c 48 KB

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  1. /*
  2. * Contains common pci routines for ALL ppc platform
  3. * (based on pci_32.c and pci_64.c)
  4. *
  5. * Port for PPC64 David Engebretsen, IBM Corp.
  6. * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
  7. *
  8. * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
  9. * Rework, based on alpha PCI code.
  10. *
  11. * Common pmac/prep/chrp pci routines. -- Cort
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License
  15. * as published by the Free Software Foundation; either version
  16. * 2 of the License, or (at your option) any later version.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/pci.h>
  20. #include <linux/string.h>
  21. #include <linux/init.h>
  22. #include <linux/delay.h>
  23. #include <linux/export.h>
  24. #include <linux/of_address.h>
  25. #include <linux/of_pci.h>
  26. #include <linux/mm.h>
  27. #include <linux/list.h>
  28. #include <linux/syscalls.h>
  29. #include <linux/irq.h>
  30. #include <linux/vmalloc.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include <asm/processor.h>
  34. #include <asm/io.h>
  35. #include <asm/prom.h>
  36. #include <asm/pci-bridge.h>
  37. #include <asm/byteorder.h>
  38. #include <asm/machdep.h>
  39. #include <asm/ppc-pci.h>
  40. #include <asm/eeh.h>
  41. /* hose_spinlock protects accesses to the the phb_bitmap. */
  42. static DEFINE_SPINLOCK(hose_spinlock);
  43. LIST_HEAD(hose_list);
  44. /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
  45. #define MAX_PHBS 0x10000
  46. /*
  47. * For dynamic PHB numbering: used/free PHBs tracking bitmap.
  48. * Accesses to this bitmap should be protected by hose_spinlock.
  49. */
  50. static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
  51. /* ISA Memory physical address */
  52. resource_size_t isa_mem_base;
  53. EXPORT_SYMBOL(isa_mem_base);
  54. static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
  55. void set_pci_dma_ops(struct dma_map_ops *dma_ops)
  56. {
  57. pci_dma_ops = dma_ops;
  58. }
  59. struct dma_map_ops *get_pci_dma_ops(void)
  60. {
  61. return pci_dma_ops;
  62. }
  63. EXPORT_SYMBOL(get_pci_dma_ops);
  64. /*
  65. * This function should run under locking protection, specifically
  66. * hose_spinlock.
  67. */
  68. static int get_phb_number(struct device_node *dn)
  69. {
  70. int ret, phb_id = -1;
  71. u32 prop_32;
  72. u64 prop;
  73. /*
  74. * Try fixed PHB numbering first, by checking archs and reading
  75. * the respective device-tree properties. Firstly, try powernv by
  76. * reading "ibm,opal-phbid", only present in OPAL environment.
  77. */
  78. ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
  79. if (ret) {
  80. ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
  81. prop = prop_32;
  82. }
  83. if (!ret)
  84. phb_id = (int)(prop & (MAX_PHBS - 1));
  85. /* We need to be sure to not use the same PHB number twice. */
  86. if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
  87. return phb_id;
  88. /*
  89. * If not pseries nor powernv, or if fixed PHB numbering tried to add
  90. * the same PHB number twice, then fallback to dynamic PHB numbering.
  91. */
  92. phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
  93. BUG_ON(phb_id >= MAX_PHBS);
  94. set_bit(phb_id, phb_bitmap);
  95. return phb_id;
  96. }
  97. struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
  98. {
  99. struct pci_controller *phb;
  100. phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
  101. if (phb == NULL)
  102. return NULL;
  103. spin_lock(&hose_spinlock);
  104. phb->global_number = get_phb_number(dev);
  105. list_add_tail(&phb->list_node, &hose_list);
  106. spin_unlock(&hose_spinlock);
  107. phb->dn = dev;
  108. phb->is_dynamic = slab_is_available();
  109. #ifdef CONFIG_PPC64
  110. if (dev) {
  111. int nid = of_node_to_nid(dev);
  112. if (nid < 0 || !node_online(nid))
  113. nid = -1;
  114. PHB_SET_NODE(phb, nid);
  115. }
  116. #endif
  117. return phb;
  118. }
  119. EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
  120. void pcibios_free_controller(struct pci_controller *phb)
  121. {
  122. spin_lock(&hose_spinlock);
  123. /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
  124. if (phb->global_number < MAX_PHBS)
  125. clear_bit(phb->global_number, phb_bitmap);
  126. list_del(&phb->list_node);
  127. spin_unlock(&hose_spinlock);
  128. if (phb->is_dynamic)
  129. kfree(phb);
  130. }
  131. EXPORT_SYMBOL_GPL(pcibios_free_controller);
  132. /*
  133. * This function is used to call pcibios_free_controller()
  134. * in a deferred manner: a callback from the PCI subsystem.
  135. *
  136. * _*DO NOT*_ call pcibios_free_controller() explicitly if
  137. * this is used (or it may access an invalid *phb pointer).
  138. *
  139. * The callback occurs when all references to the root bus
  140. * are dropped (e.g., child buses/devices and their users).
  141. *
  142. * It's called as .release_fn() of 'struct pci_host_bridge'
  143. * which is associated with the 'struct pci_controller.bus'
  144. * (root bus) - it expects .release_data to hold a pointer
  145. * to 'struct pci_controller'.
  146. *
  147. * In order to use it, register .release_fn()/release_data
  148. * like this:
  149. *
  150. * pci_set_host_bridge_release(bridge,
  151. * pcibios_free_controller_deferred
  152. * (void *) phb);
  153. *
  154. * e.g. in the pcibios_root_bridge_prepare() callback from
  155. * pci_create_root_bus().
  156. */
  157. void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
  158. {
  159. struct pci_controller *phb = (struct pci_controller *)
  160. bridge->release_data;
  161. pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
  162. pcibios_free_controller(phb);
  163. }
  164. EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
  165. /*
  166. * The function is used to return the minimal alignment
  167. * for memory or I/O windows of the associated P2P bridge.
  168. * By default, 4KiB alignment for I/O windows and 1MiB for
  169. * memory windows.
  170. */
  171. resource_size_t pcibios_window_alignment(struct pci_bus *bus,
  172. unsigned long type)
  173. {
  174. struct pci_controller *phb = pci_bus_to_host(bus);
  175. if (phb->controller_ops.window_alignment)
  176. return phb->controller_ops.window_alignment(bus, type);
  177. /*
  178. * PCI core will figure out the default
  179. * alignment: 4KiB for I/O and 1MiB for
  180. * memory window.
  181. */
  182. return 1;
  183. }
  184. void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
  185. {
  186. struct pci_controller *hose = pci_bus_to_host(bus);
  187. if (hose->controller_ops.setup_bridge)
  188. hose->controller_ops.setup_bridge(bus, type);
  189. }
  190. void pcibios_reset_secondary_bus(struct pci_dev *dev)
  191. {
  192. struct pci_controller *phb = pci_bus_to_host(dev->bus);
  193. if (phb->controller_ops.reset_secondary_bus) {
  194. phb->controller_ops.reset_secondary_bus(dev);
  195. return;
  196. }
  197. pci_reset_secondary_bus(dev);
  198. }
  199. #ifdef CONFIG_PCI_IOV
  200. resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
  201. {
  202. if (ppc_md.pcibios_iov_resource_alignment)
  203. return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
  204. return pci_iov_resource_size(pdev, resno);
  205. }
  206. #endif /* CONFIG_PCI_IOV */
  207. static resource_size_t pcibios_io_size(const struct pci_controller *hose)
  208. {
  209. #ifdef CONFIG_PPC64
  210. return hose->pci_io_size;
  211. #else
  212. return resource_size(&hose->io_resource);
  213. #endif
  214. }
  215. int pcibios_vaddr_is_ioport(void __iomem *address)
  216. {
  217. int ret = 0;
  218. struct pci_controller *hose;
  219. resource_size_t size;
  220. spin_lock(&hose_spinlock);
  221. list_for_each_entry(hose, &hose_list, list_node) {
  222. size = pcibios_io_size(hose);
  223. if (address >= hose->io_base_virt &&
  224. address < (hose->io_base_virt + size)) {
  225. ret = 1;
  226. break;
  227. }
  228. }
  229. spin_unlock(&hose_spinlock);
  230. return ret;
  231. }
  232. unsigned long pci_address_to_pio(phys_addr_t address)
  233. {
  234. struct pci_controller *hose;
  235. resource_size_t size;
  236. unsigned long ret = ~0;
  237. spin_lock(&hose_spinlock);
  238. list_for_each_entry(hose, &hose_list, list_node) {
  239. size = pcibios_io_size(hose);
  240. if (address >= hose->io_base_phys &&
  241. address < (hose->io_base_phys + size)) {
  242. unsigned long base =
  243. (unsigned long)hose->io_base_virt - _IO_BASE;
  244. ret = base + (address - hose->io_base_phys);
  245. break;
  246. }
  247. }
  248. spin_unlock(&hose_spinlock);
  249. return ret;
  250. }
  251. EXPORT_SYMBOL_GPL(pci_address_to_pio);
  252. /*
  253. * Return the domain number for this bus.
  254. */
  255. int pci_domain_nr(struct pci_bus *bus)
  256. {
  257. struct pci_controller *hose = pci_bus_to_host(bus);
  258. return hose->global_number;
  259. }
  260. EXPORT_SYMBOL(pci_domain_nr);
  261. /* This routine is meant to be used early during boot, when the
  262. * PCI bus numbers have not yet been assigned, and you need to
  263. * issue PCI config cycles to an OF device.
  264. * It could also be used to "fix" RTAS config cycles if you want
  265. * to set pci_assign_all_buses to 1 and still use RTAS for PCI
  266. * config cycles.
  267. */
  268. struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
  269. {
  270. while(node) {
  271. struct pci_controller *hose, *tmp;
  272. list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  273. if (hose->dn == node)
  274. return hose;
  275. node = node->parent;
  276. }
  277. return NULL;
  278. }
  279. /*
  280. * Reads the interrupt pin to determine if interrupt is use by card.
  281. * If the interrupt is used, then gets the interrupt line from the
  282. * openfirmware and sets it in the pci_dev and pci_config line.
  283. */
  284. static int pci_read_irq_line(struct pci_dev *pci_dev)
  285. {
  286. struct of_phandle_args oirq;
  287. unsigned int virq;
  288. pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
  289. #ifdef DEBUG
  290. memset(&oirq, 0xff, sizeof(oirq));
  291. #endif
  292. /* Try to get a mapping from the device-tree */
  293. if (of_irq_parse_pci(pci_dev, &oirq)) {
  294. u8 line, pin;
  295. /* If that fails, lets fallback to what is in the config
  296. * space and map that through the default controller. We
  297. * also set the type to level low since that's what PCI
  298. * interrupts are. If your platform does differently, then
  299. * either provide a proper interrupt tree or don't use this
  300. * function.
  301. */
  302. if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
  303. return -1;
  304. if (pin == 0)
  305. return -1;
  306. if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
  307. line == 0xff || line == 0) {
  308. return -1;
  309. }
  310. pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
  311. line, pin);
  312. virq = irq_create_mapping(NULL, line);
  313. if (virq)
  314. irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
  315. } else {
  316. pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
  317. oirq.args_count, oirq.args[0], oirq.args[1],
  318. of_node_full_name(oirq.np));
  319. virq = irq_create_of_mapping(&oirq);
  320. }
  321. if (!virq) {
  322. pr_debug(" Failed to map !\n");
  323. return -1;
  324. }
  325. pr_debug(" Mapped to linux irq %d\n", virq);
  326. pci_dev->irq = virq;
  327. return 0;
  328. }
  329. /*
  330. * Platform support for /proc/bus/pci/X/Y mmap()s,
  331. * modelled on the sparc64 implementation by Dave Miller.
  332. * -- paulus.
  333. */
  334. /*
  335. * Adjust vm_pgoff of VMA such that it is the physical page offset
  336. * corresponding to the 32-bit pci bus offset for DEV requested by the user.
  337. *
  338. * Basically, the user finds the base address for his device which he wishes
  339. * to mmap. They read the 32-bit value from the config space base register,
  340. * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
  341. * offset parameter of mmap on /proc/bus/pci/XXX for that device.
  342. *
  343. * Returns negative error code on failure, zero on success.
  344. */
  345. static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
  346. resource_size_t *offset,
  347. enum pci_mmap_state mmap_state)
  348. {
  349. struct pci_controller *hose = pci_bus_to_host(dev->bus);
  350. unsigned long io_offset = 0;
  351. int i, res_bit;
  352. if (hose == NULL)
  353. return NULL; /* should never happen */
  354. /* If memory, add on the PCI bridge address offset */
  355. if (mmap_state == pci_mmap_mem) {
  356. #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
  357. *offset += hose->pci_mem_offset;
  358. #endif
  359. res_bit = IORESOURCE_MEM;
  360. } else {
  361. io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
  362. *offset += io_offset;
  363. res_bit = IORESOURCE_IO;
  364. }
  365. /*
  366. * Check that the offset requested corresponds to one of the
  367. * resources of the device.
  368. */
  369. for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
  370. struct resource *rp = &dev->resource[i];
  371. int flags = rp->flags;
  372. /* treat ROM as memory (should be already) */
  373. if (i == PCI_ROM_RESOURCE)
  374. flags |= IORESOURCE_MEM;
  375. /* Active and same type? */
  376. if ((flags & res_bit) == 0)
  377. continue;
  378. /* In the range of this resource? */
  379. if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
  380. continue;
  381. /* found it! construct the final physical address */
  382. if (mmap_state == pci_mmap_io)
  383. *offset += hose->io_base_phys - io_offset;
  384. return rp;
  385. }
  386. return NULL;
  387. }
  388. /*
  389. * This one is used by /dev/mem and fbdev who have no clue about the
  390. * PCI device, it tries to find the PCI device first and calls the
  391. * above routine
  392. */
  393. pgprot_t pci_phys_mem_access_prot(struct file *file,
  394. unsigned long pfn,
  395. unsigned long size,
  396. pgprot_t prot)
  397. {
  398. struct pci_dev *pdev = NULL;
  399. struct resource *found = NULL;
  400. resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
  401. int i;
  402. if (page_is_ram(pfn))
  403. return prot;
  404. prot = pgprot_noncached(prot);
  405. for_each_pci_dev(pdev) {
  406. for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
  407. struct resource *rp = &pdev->resource[i];
  408. int flags = rp->flags;
  409. /* Active and same type? */
  410. if ((flags & IORESOURCE_MEM) == 0)
  411. continue;
  412. /* In the range of this resource? */
  413. if (offset < (rp->start & PAGE_MASK) ||
  414. offset > rp->end)
  415. continue;
  416. found = rp;
  417. break;
  418. }
  419. if (found)
  420. break;
  421. }
  422. if (found) {
  423. if (found->flags & IORESOURCE_PREFETCH)
  424. prot = pgprot_noncached_wc(prot);
  425. pci_dev_put(pdev);
  426. }
  427. pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
  428. (unsigned long long)offset, pgprot_val(prot));
  429. return prot;
  430. }
  431. /*
  432. * Perform the actual remap of the pages for a PCI device mapping, as
  433. * appropriate for this architecture. The region in the process to map
  434. * is described by vm_start and vm_end members of VMA, the base physical
  435. * address is found in vm_pgoff.
  436. * The pci device structure is provided so that architectures may make mapping
  437. * decisions on a per-device or per-bus basis.
  438. *
  439. * Returns a negative error code on failure, zero on success.
  440. */
  441. int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  442. enum pci_mmap_state mmap_state, int write_combine)
  443. {
  444. resource_size_t offset =
  445. ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
  446. struct resource *rp;
  447. int ret;
  448. rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
  449. if (rp == NULL)
  450. return -EINVAL;
  451. vma->vm_pgoff = offset >> PAGE_SHIFT;
  452. if (write_combine)
  453. vma->vm_page_prot = pgprot_noncached_wc(vma->vm_page_prot);
  454. else
  455. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  456. ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  457. vma->vm_end - vma->vm_start, vma->vm_page_prot);
  458. return ret;
  459. }
  460. /* This provides legacy IO read access on a bus */
  461. int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
  462. {
  463. unsigned long offset;
  464. struct pci_controller *hose = pci_bus_to_host(bus);
  465. struct resource *rp = &hose->io_resource;
  466. void __iomem *addr;
  467. /* Check if port can be supported by that bus. We only check
  468. * the ranges of the PHB though, not the bus itself as the rules
  469. * for forwarding legacy cycles down bridges are not our problem
  470. * here. So if the host bridge supports it, we do it.
  471. */
  472. offset = (unsigned long)hose->io_base_virt - _IO_BASE;
  473. offset += port;
  474. if (!(rp->flags & IORESOURCE_IO))
  475. return -ENXIO;
  476. if (offset < rp->start || (offset + size) > rp->end)
  477. return -ENXIO;
  478. addr = hose->io_base_virt + port;
  479. switch(size) {
  480. case 1:
  481. *((u8 *)val) = in_8(addr);
  482. return 1;
  483. case 2:
  484. if (port & 1)
  485. return -EINVAL;
  486. *((u16 *)val) = in_le16(addr);
  487. return 2;
  488. case 4:
  489. if (port & 3)
  490. return -EINVAL;
  491. *((u32 *)val) = in_le32(addr);
  492. return 4;
  493. }
  494. return -EINVAL;
  495. }
  496. /* This provides legacy IO write access on a bus */
  497. int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
  498. {
  499. unsigned long offset;
  500. struct pci_controller *hose = pci_bus_to_host(bus);
  501. struct resource *rp = &hose->io_resource;
  502. void __iomem *addr;
  503. /* Check if port can be supported by that bus. We only check
  504. * the ranges of the PHB though, not the bus itself as the rules
  505. * for forwarding legacy cycles down bridges are not our problem
  506. * here. So if the host bridge supports it, we do it.
  507. */
  508. offset = (unsigned long)hose->io_base_virt - _IO_BASE;
  509. offset += port;
  510. if (!(rp->flags & IORESOURCE_IO))
  511. return -ENXIO;
  512. if (offset < rp->start || (offset + size) > rp->end)
  513. return -ENXIO;
  514. addr = hose->io_base_virt + port;
  515. /* WARNING: The generic code is idiotic. It gets passed a pointer
  516. * to what can be a 1, 2 or 4 byte quantity and always reads that
  517. * as a u32, which means that we have to correct the location of
  518. * the data read within those 32 bits for size 1 and 2
  519. */
  520. switch(size) {
  521. case 1:
  522. out_8(addr, val >> 24);
  523. return 1;
  524. case 2:
  525. if (port & 1)
  526. return -EINVAL;
  527. out_le16(addr, val >> 16);
  528. return 2;
  529. case 4:
  530. if (port & 3)
  531. return -EINVAL;
  532. out_le32(addr, val);
  533. return 4;
  534. }
  535. return -EINVAL;
  536. }
  537. /* This provides legacy IO or memory mmap access on a bus */
  538. int pci_mmap_legacy_page_range(struct pci_bus *bus,
  539. struct vm_area_struct *vma,
  540. enum pci_mmap_state mmap_state)
  541. {
  542. struct pci_controller *hose = pci_bus_to_host(bus);
  543. resource_size_t offset =
  544. ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
  545. resource_size_t size = vma->vm_end - vma->vm_start;
  546. struct resource *rp;
  547. pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
  548. pci_domain_nr(bus), bus->number,
  549. mmap_state == pci_mmap_mem ? "MEM" : "IO",
  550. (unsigned long long)offset,
  551. (unsigned long long)(offset + size - 1));
  552. if (mmap_state == pci_mmap_mem) {
  553. /* Hack alert !
  554. *
  555. * Because X is lame and can fail starting if it gets an error trying
  556. * to mmap legacy_mem (instead of just moving on without legacy memory
  557. * access) we fake it here by giving it anonymous memory, effectively
  558. * behaving just like /dev/zero
  559. */
  560. if ((offset + size) > hose->isa_mem_size) {
  561. printk(KERN_DEBUG
  562. "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
  563. current->comm, current->pid, pci_domain_nr(bus), bus->number);
  564. if (vma->vm_flags & VM_SHARED)
  565. return shmem_zero_setup(vma);
  566. return 0;
  567. }
  568. offset += hose->isa_mem_phys;
  569. } else {
  570. unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
  571. unsigned long roffset = offset + io_offset;
  572. rp = &hose->io_resource;
  573. if (!(rp->flags & IORESOURCE_IO))
  574. return -ENXIO;
  575. if (roffset < rp->start || (roffset + size) > rp->end)
  576. return -ENXIO;
  577. offset += hose->io_base_phys;
  578. }
  579. pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
  580. vma->vm_pgoff = offset >> PAGE_SHIFT;
  581. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  582. return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  583. vma->vm_end - vma->vm_start,
  584. vma->vm_page_prot);
  585. }
  586. void pci_resource_to_user(const struct pci_dev *dev, int bar,
  587. const struct resource *rsrc,
  588. resource_size_t *start, resource_size_t *end)
  589. {
  590. struct pci_bus_region region;
  591. if (rsrc->flags & IORESOURCE_IO) {
  592. pcibios_resource_to_bus(dev->bus, &region,
  593. (struct resource *) rsrc);
  594. *start = region.start;
  595. *end = region.end;
  596. return;
  597. }
  598. /* We pass a CPU physical address to userland for MMIO instead of a
  599. * BAR value because X is lame and expects to be able to use that
  600. * to pass to /dev/mem!
  601. *
  602. * That means we may have 64-bit values where some apps only expect
  603. * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
  604. */
  605. *start = rsrc->start;
  606. *end = rsrc->end;
  607. }
  608. /**
  609. * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
  610. * @hose: newly allocated pci_controller to be setup
  611. * @dev: device node of the host bridge
  612. * @primary: set if primary bus (32 bits only, soon to be deprecated)
  613. *
  614. * This function will parse the "ranges" property of a PCI host bridge device
  615. * node and setup the resource mapping of a pci controller based on its
  616. * content.
  617. *
  618. * Life would be boring if it wasn't for a few issues that we have to deal
  619. * with here:
  620. *
  621. * - We can only cope with one IO space range and up to 3 Memory space
  622. * ranges. However, some machines (thanks Apple !) tend to split their
  623. * space into lots of small contiguous ranges. So we have to coalesce.
  624. *
  625. * - Some busses have IO space not starting at 0, which causes trouble with
  626. * the way we do our IO resource renumbering. The code somewhat deals with
  627. * it for 64 bits but I would expect problems on 32 bits.
  628. *
  629. * - Some 32 bits platforms such as 4xx can have physical space larger than
  630. * 32 bits so we need to use 64 bits values for the parsing
  631. */
  632. void pci_process_bridge_OF_ranges(struct pci_controller *hose,
  633. struct device_node *dev, int primary)
  634. {
  635. int memno = 0;
  636. struct resource *res;
  637. struct of_pci_range range;
  638. struct of_pci_range_parser parser;
  639. printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
  640. dev->full_name, primary ? "(primary)" : "");
  641. /* Check for ranges property */
  642. if (of_pci_range_parser_init(&parser, dev))
  643. return;
  644. /* Parse it */
  645. for_each_of_pci_range(&parser, &range) {
  646. /* If we failed translation or got a zero-sized region
  647. * (some FW try to feed us with non sensical zero sized regions
  648. * such as power3 which look like some kind of attempt at exposing
  649. * the VGA memory hole)
  650. */
  651. if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
  652. continue;
  653. /* Act based on address space type */
  654. res = NULL;
  655. switch (range.flags & IORESOURCE_TYPE_BITS) {
  656. case IORESOURCE_IO:
  657. printk(KERN_INFO
  658. " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
  659. range.cpu_addr, range.cpu_addr + range.size - 1,
  660. range.pci_addr);
  661. /* We support only one IO range */
  662. if (hose->pci_io_size) {
  663. printk(KERN_INFO
  664. " \\--> Skipped (too many) !\n");
  665. continue;
  666. }
  667. #ifdef CONFIG_PPC32
  668. /* On 32 bits, limit I/O space to 16MB */
  669. if (range.size > 0x01000000)
  670. range.size = 0x01000000;
  671. /* 32 bits needs to map IOs here */
  672. hose->io_base_virt = ioremap(range.cpu_addr,
  673. range.size);
  674. /* Expect trouble if pci_addr is not 0 */
  675. if (primary)
  676. isa_io_base =
  677. (unsigned long)hose->io_base_virt;
  678. #endif /* CONFIG_PPC32 */
  679. /* pci_io_size and io_base_phys always represent IO
  680. * space starting at 0 so we factor in pci_addr
  681. */
  682. hose->pci_io_size = range.pci_addr + range.size;
  683. hose->io_base_phys = range.cpu_addr - range.pci_addr;
  684. /* Build resource */
  685. res = &hose->io_resource;
  686. range.cpu_addr = range.pci_addr;
  687. break;
  688. case IORESOURCE_MEM:
  689. printk(KERN_INFO
  690. " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
  691. range.cpu_addr, range.cpu_addr + range.size - 1,
  692. range.pci_addr,
  693. (range.pci_space & 0x40000000) ?
  694. "Prefetch" : "");
  695. /* We support only 3 memory ranges */
  696. if (memno >= 3) {
  697. printk(KERN_INFO
  698. " \\--> Skipped (too many) !\n");
  699. continue;
  700. }
  701. /* Handles ISA memory hole space here */
  702. if (range.pci_addr == 0) {
  703. if (primary || isa_mem_base == 0)
  704. isa_mem_base = range.cpu_addr;
  705. hose->isa_mem_phys = range.cpu_addr;
  706. hose->isa_mem_size = range.size;
  707. }
  708. /* Build resource */
  709. hose->mem_offset[memno] = range.cpu_addr -
  710. range.pci_addr;
  711. res = &hose->mem_resources[memno++];
  712. break;
  713. }
  714. if (res != NULL) {
  715. res->name = dev->full_name;
  716. res->flags = range.flags;
  717. res->start = range.cpu_addr;
  718. res->end = range.cpu_addr + range.size - 1;
  719. res->parent = res->child = res->sibling = NULL;
  720. }
  721. }
  722. }
  723. /* Decide whether to display the domain number in /proc */
  724. int pci_proc_domain(struct pci_bus *bus)
  725. {
  726. struct pci_controller *hose = pci_bus_to_host(bus);
  727. if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
  728. return 0;
  729. if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
  730. return hose->global_number != 0;
  731. return 1;
  732. }
  733. int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
  734. {
  735. if (ppc_md.pcibios_root_bridge_prepare)
  736. return ppc_md.pcibios_root_bridge_prepare(bridge);
  737. return 0;
  738. }
  739. /* This header fixup will do the resource fixup for all devices as they are
  740. * probed, but not for bridge ranges
  741. */
  742. static void pcibios_fixup_resources(struct pci_dev *dev)
  743. {
  744. struct pci_controller *hose = pci_bus_to_host(dev->bus);
  745. int i;
  746. if (!hose) {
  747. printk(KERN_ERR "No host bridge for PCI dev %s !\n",
  748. pci_name(dev));
  749. return;
  750. }
  751. if (dev->is_virtfn)
  752. return;
  753. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  754. struct resource *res = dev->resource + i;
  755. struct pci_bus_region reg;
  756. if (!res->flags)
  757. continue;
  758. /* If we're going to re-assign everything, we mark all resources
  759. * as unset (and 0-base them). In addition, we mark BARs starting
  760. * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
  761. * since in that case, we don't want to re-assign anything
  762. */
  763. pcibios_resource_to_bus(dev->bus, &reg, res);
  764. if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
  765. (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
  766. /* Only print message if not re-assigning */
  767. if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
  768. pr_debug("PCI:%s Resource %d %pR is unassigned\n",
  769. pci_name(dev), i, res);
  770. res->end -= res->start;
  771. res->start = 0;
  772. res->flags |= IORESOURCE_UNSET;
  773. continue;
  774. }
  775. pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
  776. }
  777. /* Call machine specific resource fixup */
  778. if (ppc_md.pcibios_fixup_resources)
  779. ppc_md.pcibios_fixup_resources(dev);
  780. }
  781. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
  782. /* This function tries to figure out if a bridge resource has been initialized
  783. * by the firmware or not. It doesn't have to be absolutely bullet proof, but
  784. * things go more smoothly when it gets it right. It should covers cases such
  785. * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
  786. */
  787. static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
  788. struct resource *res)
  789. {
  790. struct pci_controller *hose = pci_bus_to_host(bus);
  791. struct pci_dev *dev = bus->self;
  792. resource_size_t offset;
  793. struct pci_bus_region region;
  794. u16 command;
  795. int i;
  796. /* We don't do anything if PCI_PROBE_ONLY is set */
  797. if (pci_has_flag(PCI_PROBE_ONLY))
  798. return 0;
  799. /* Job is a bit different between memory and IO */
  800. if (res->flags & IORESOURCE_MEM) {
  801. pcibios_resource_to_bus(dev->bus, &region, res);
  802. /* If the BAR is non-0 then it's probably been initialized */
  803. if (region.start != 0)
  804. return 0;
  805. /* The BAR is 0, let's check if memory decoding is enabled on
  806. * the bridge. If not, we consider it unassigned
  807. */
  808. pci_read_config_word(dev, PCI_COMMAND, &command);
  809. if ((command & PCI_COMMAND_MEMORY) == 0)
  810. return 1;
  811. /* Memory decoding is enabled and the BAR is 0. If any of the bridge
  812. * resources covers that starting address (0 then it's good enough for
  813. * us for memory space)
  814. */
  815. for (i = 0; i < 3; i++) {
  816. if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
  817. hose->mem_resources[i].start == hose->mem_offset[i])
  818. return 0;
  819. }
  820. /* Well, it starts at 0 and we know it will collide so we may as
  821. * well consider it as unassigned. That covers the Apple case.
  822. */
  823. return 1;
  824. } else {
  825. /* If the BAR is non-0, then we consider it assigned */
  826. offset = (unsigned long)hose->io_base_virt - _IO_BASE;
  827. if (((res->start - offset) & 0xfffffffful) != 0)
  828. return 0;
  829. /* Here, we are a bit different than memory as typically IO space
  830. * starting at low addresses -is- valid. What we do instead if that
  831. * we consider as unassigned anything that doesn't have IO enabled
  832. * in the PCI command register, and that's it.
  833. */
  834. pci_read_config_word(dev, PCI_COMMAND, &command);
  835. if (command & PCI_COMMAND_IO)
  836. return 0;
  837. /* It's starting at 0 and IO is disabled in the bridge, consider
  838. * it unassigned
  839. */
  840. return 1;
  841. }
  842. }
  843. /* Fixup resources of a PCI<->PCI bridge */
  844. static void pcibios_fixup_bridge(struct pci_bus *bus)
  845. {
  846. struct resource *res;
  847. int i;
  848. struct pci_dev *dev = bus->self;
  849. pci_bus_for_each_resource(bus, res, i) {
  850. if (!res || !res->flags)
  851. continue;
  852. if (i >= 3 && bus->self->transparent)
  853. continue;
  854. /* If we're going to reassign everything, we can
  855. * shrink the P2P resource to have size as being
  856. * of 0 in order to save space.
  857. */
  858. if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
  859. res->flags |= IORESOURCE_UNSET;
  860. res->start = 0;
  861. res->end = -1;
  862. continue;
  863. }
  864. pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
  865. /* Try to detect uninitialized P2P bridge resources,
  866. * and clear them out so they get re-assigned later
  867. */
  868. if (pcibios_uninitialized_bridge_resource(bus, res)) {
  869. res->flags = 0;
  870. pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
  871. }
  872. }
  873. }
  874. void pcibios_setup_bus_self(struct pci_bus *bus)
  875. {
  876. struct pci_controller *phb;
  877. /* Fix up the bus resources for P2P bridges */
  878. if (bus->self != NULL)
  879. pcibios_fixup_bridge(bus);
  880. /* Platform specific bus fixups. This is currently only used
  881. * by fsl_pci and I'm hoping to get rid of it at some point
  882. */
  883. if (ppc_md.pcibios_fixup_bus)
  884. ppc_md.pcibios_fixup_bus(bus);
  885. /* Setup bus DMA mappings */
  886. phb = pci_bus_to_host(bus);
  887. if (phb->controller_ops.dma_bus_setup)
  888. phb->controller_ops.dma_bus_setup(bus);
  889. }
  890. static void pcibios_setup_device(struct pci_dev *dev)
  891. {
  892. struct pci_controller *phb;
  893. /* Fixup NUMA node as it may not be setup yet by the generic
  894. * code and is needed by the DMA init
  895. */
  896. set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
  897. /* Hook up default DMA ops */
  898. set_dma_ops(&dev->dev, pci_dma_ops);
  899. set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
  900. /* Additional platform DMA/iommu setup */
  901. phb = pci_bus_to_host(dev->bus);
  902. if (phb->controller_ops.dma_dev_setup)
  903. phb->controller_ops.dma_dev_setup(dev);
  904. /* Read default IRQs and fixup if necessary */
  905. pci_read_irq_line(dev);
  906. if (ppc_md.pci_irq_fixup)
  907. ppc_md.pci_irq_fixup(dev);
  908. }
  909. int pcibios_add_device(struct pci_dev *dev)
  910. {
  911. /*
  912. * We can only call pcibios_setup_device() after bus setup is complete,
  913. * since some of the platform specific DMA setup code depends on it.
  914. */
  915. if (dev->bus->is_added)
  916. pcibios_setup_device(dev);
  917. #ifdef CONFIG_PCI_IOV
  918. if (ppc_md.pcibios_fixup_sriov)
  919. ppc_md.pcibios_fixup_sriov(dev);
  920. #endif /* CONFIG_PCI_IOV */
  921. return 0;
  922. }
  923. void pcibios_setup_bus_devices(struct pci_bus *bus)
  924. {
  925. struct pci_dev *dev;
  926. pr_debug("PCI: Fixup bus devices %d (%s)\n",
  927. bus->number, bus->self ? pci_name(bus->self) : "PHB");
  928. list_for_each_entry(dev, &bus->devices, bus_list) {
  929. /* Cardbus can call us to add new devices to a bus, so ignore
  930. * those who are already fully discovered
  931. */
  932. if (dev->is_added)
  933. continue;
  934. pcibios_setup_device(dev);
  935. }
  936. }
  937. void pcibios_set_master(struct pci_dev *dev)
  938. {
  939. /* No special bus mastering setup handling */
  940. }
  941. void pcibios_fixup_bus(struct pci_bus *bus)
  942. {
  943. /* When called from the generic PCI probe, read PCI<->PCI bridge
  944. * bases. This is -not- called when generating the PCI tree from
  945. * the OF device-tree.
  946. */
  947. pci_read_bridge_bases(bus);
  948. /* Now fixup the bus bus */
  949. pcibios_setup_bus_self(bus);
  950. /* Now fixup devices on that bus */
  951. pcibios_setup_bus_devices(bus);
  952. }
  953. EXPORT_SYMBOL(pcibios_fixup_bus);
  954. void pci_fixup_cardbus(struct pci_bus *bus)
  955. {
  956. /* Now fixup devices on that bus */
  957. pcibios_setup_bus_devices(bus);
  958. }
  959. static int skip_isa_ioresource_align(struct pci_dev *dev)
  960. {
  961. if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
  962. !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
  963. return 1;
  964. return 0;
  965. }
  966. /*
  967. * We need to avoid collisions with `mirrored' VGA ports
  968. * and other strange ISA hardware, so we always want the
  969. * addresses to be allocated in the 0x000-0x0ff region
  970. * modulo 0x400.
  971. *
  972. * Why? Because some silly external IO cards only decode
  973. * the low 10 bits of the IO address. The 0x00-0xff region
  974. * is reserved for motherboard devices that decode all 16
  975. * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  976. * but we want to try to avoid allocating at 0x2900-0x2bff
  977. * which might have be mirrored at 0x0100-0x03ff..
  978. */
  979. resource_size_t pcibios_align_resource(void *data, const struct resource *res,
  980. resource_size_t size, resource_size_t align)
  981. {
  982. struct pci_dev *dev = data;
  983. resource_size_t start = res->start;
  984. if (res->flags & IORESOURCE_IO) {
  985. if (skip_isa_ioresource_align(dev))
  986. return start;
  987. if (start & 0x300)
  988. start = (start + 0x3ff) & ~0x3ff;
  989. }
  990. return start;
  991. }
  992. EXPORT_SYMBOL(pcibios_align_resource);
  993. /*
  994. * Reparent resource children of pr that conflict with res
  995. * under res, and make res replace those children.
  996. */
  997. static int reparent_resources(struct resource *parent,
  998. struct resource *res)
  999. {
  1000. struct resource *p, **pp;
  1001. struct resource **firstpp = NULL;
  1002. for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
  1003. if (p->end < res->start)
  1004. continue;
  1005. if (res->end < p->start)
  1006. break;
  1007. if (p->start < res->start || p->end > res->end)
  1008. return -1; /* not completely contained */
  1009. if (firstpp == NULL)
  1010. firstpp = pp;
  1011. }
  1012. if (firstpp == NULL)
  1013. return -1; /* didn't find any conflicting entries? */
  1014. res->parent = parent;
  1015. res->child = *firstpp;
  1016. res->sibling = *pp;
  1017. *firstpp = res;
  1018. *pp = NULL;
  1019. for (p = res->child; p != NULL; p = p->sibling) {
  1020. p->parent = res;
  1021. pr_debug("PCI: Reparented %s %pR under %s\n",
  1022. p->name, p, res->name);
  1023. }
  1024. return 0;
  1025. }
  1026. /*
  1027. * Handle resources of PCI devices. If the world were perfect, we could
  1028. * just allocate all the resource regions and do nothing more. It isn't.
  1029. * On the other hand, we cannot just re-allocate all devices, as it would
  1030. * require us to know lots of host bridge internals. So we attempt to
  1031. * keep as much of the original configuration as possible, but tweak it
  1032. * when it's found to be wrong.
  1033. *
  1034. * Known BIOS problems we have to work around:
  1035. * - I/O or memory regions not configured
  1036. * - regions configured, but not enabled in the command register
  1037. * - bogus I/O addresses above 64K used
  1038. * - expansion ROMs left enabled (this may sound harmless, but given
  1039. * the fact the PCI specs explicitly allow address decoders to be
  1040. * shared between expansion ROMs and other resource regions, it's
  1041. * at least dangerous)
  1042. *
  1043. * Our solution:
  1044. * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
  1045. * This gives us fixed barriers on where we can allocate.
  1046. * (2) Allocate resources for all enabled devices. If there is
  1047. * a collision, just mark the resource as unallocated. Also
  1048. * disable expansion ROMs during this step.
  1049. * (3) Try to allocate resources for disabled devices. If the
  1050. * resources were assigned correctly, everything goes well,
  1051. * if they weren't, they won't disturb allocation of other
  1052. * resources.
  1053. * (4) Assign new addresses to resources which were either
  1054. * not configured at all or misconfigured. If explicitly
  1055. * requested by the user, configure expansion ROM address
  1056. * as well.
  1057. */
  1058. static void pcibios_allocate_bus_resources(struct pci_bus *bus)
  1059. {
  1060. struct pci_bus *b;
  1061. int i;
  1062. struct resource *res, *pr;
  1063. pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
  1064. pci_domain_nr(bus), bus->number);
  1065. pci_bus_for_each_resource(bus, res, i) {
  1066. if (!res || !res->flags || res->start > res->end || res->parent)
  1067. continue;
  1068. /* If the resource was left unset at this point, we clear it */
  1069. if (res->flags & IORESOURCE_UNSET)
  1070. goto clear_resource;
  1071. if (bus->parent == NULL)
  1072. pr = (res->flags & IORESOURCE_IO) ?
  1073. &ioport_resource : &iomem_resource;
  1074. else {
  1075. pr = pci_find_parent_resource(bus->self, res);
  1076. if (pr == res) {
  1077. /* this happens when the generic PCI
  1078. * code (wrongly) decides that this
  1079. * bridge is transparent -- paulus
  1080. */
  1081. continue;
  1082. }
  1083. }
  1084. pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
  1085. bus->self ? pci_name(bus->self) : "PHB", bus->number,
  1086. i, res, pr, (pr && pr->name) ? pr->name : "nil");
  1087. if (pr && !(pr->flags & IORESOURCE_UNSET)) {
  1088. struct pci_dev *dev = bus->self;
  1089. if (request_resource(pr, res) == 0)
  1090. continue;
  1091. /*
  1092. * Must be a conflict with an existing entry.
  1093. * Move that entry (or entries) under the
  1094. * bridge resource and try again.
  1095. */
  1096. if (reparent_resources(pr, res) == 0)
  1097. continue;
  1098. if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
  1099. pci_claim_bridge_resource(dev,
  1100. i + PCI_BRIDGE_RESOURCES) == 0)
  1101. continue;
  1102. }
  1103. pr_warning("PCI: Cannot allocate resource region "
  1104. "%d of PCI bridge %d, will remap\n", i, bus->number);
  1105. clear_resource:
  1106. /* The resource might be figured out when doing
  1107. * reassignment based on the resources required
  1108. * by the downstream PCI devices. Here we set
  1109. * the size of the resource to be 0 in order to
  1110. * save more space.
  1111. */
  1112. res->start = 0;
  1113. res->end = -1;
  1114. res->flags = 0;
  1115. }
  1116. list_for_each_entry(b, &bus->children, node)
  1117. pcibios_allocate_bus_resources(b);
  1118. }
  1119. static inline void alloc_resource(struct pci_dev *dev, int idx)
  1120. {
  1121. struct resource *pr, *r = &dev->resource[idx];
  1122. pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
  1123. pci_name(dev), idx, r);
  1124. pr = pci_find_parent_resource(dev, r);
  1125. if (!pr || (pr->flags & IORESOURCE_UNSET) ||
  1126. request_resource(pr, r) < 0) {
  1127. printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
  1128. " of device %s, will remap\n", idx, pci_name(dev));
  1129. if (pr)
  1130. pr_debug("PCI: parent is %p: %pR\n", pr, pr);
  1131. /* We'll assign a new address later */
  1132. r->flags |= IORESOURCE_UNSET;
  1133. r->end -= r->start;
  1134. r->start = 0;
  1135. }
  1136. }
  1137. static void __init pcibios_allocate_resources(int pass)
  1138. {
  1139. struct pci_dev *dev = NULL;
  1140. int idx, disabled;
  1141. u16 command;
  1142. struct resource *r;
  1143. for_each_pci_dev(dev) {
  1144. pci_read_config_word(dev, PCI_COMMAND, &command);
  1145. for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
  1146. r = &dev->resource[idx];
  1147. if (r->parent) /* Already allocated */
  1148. continue;
  1149. if (!r->flags || (r->flags & IORESOURCE_UNSET))
  1150. continue; /* Not assigned at all */
  1151. /* We only allocate ROMs on pass 1 just in case they
  1152. * have been screwed up by firmware
  1153. */
  1154. if (idx == PCI_ROM_RESOURCE )
  1155. disabled = 1;
  1156. if (r->flags & IORESOURCE_IO)
  1157. disabled = !(command & PCI_COMMAND_IO);
  1158. else
  1159. disabled = !(command & PCI_COMMAND_MEMORY);
  1160. if (pass == disabled)
  1161. alloc_resource(dev, idx);
  1162. }
  1163. if (pass)
  1164. continue;
  1165. r = &dev->resource[PCI_ROM_RESOURCE];
  1166. if (r->flags) {
  1167. /* Turn the ROM off, leave the resource region,
  1168. * but keep it unregistered.
  1169. */
  1170. u32 reg;
  1171. pci_read_config_dword(dev, dev->rom_base_reg, &reg);
  1172. if (reg & PCI_ROM_ADDRESS_ENABLE) {
  1173. pr_debug("PCI: Switching off ROM of %s\n",
  1174. pci_name(dev));
  1175. r->flags &= ~IORESOURCE_ROM_ENABLE;
  1176. pci_write_config_dword(dev, dev->rom_base_reg,
  1177. reg & ~PCI_ROM_ADDRESS_ENABLE);
  1178. }
  1179. }
  1180. }
  1181. }
  1182. static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
  1183. {
  1184. struct pci_controller *hose = pci_bus_to_host(bus);
  1185. resource_size_t offset;
  1186. struct resource *res, *pres;
  1187. int i;
  1188. pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
  1189. /* Check for IO */
  1190. if (!(hose->io_resource.flags & IORESOURCE_IO))
  1191. goto no_io;
  1192. offset = (unsigned long)hose->io_base_virt - _IO_BASE;
  1193. res = kzalloc(sizeof(struct resource), GFP_KERNEL);
  1194. BUG_ON(res == NULL);
  1195. res->name = "Legacy IO";
  1196. res->flags = IORESOURCE_IO;
  1197. res->start = offset;
  1198. res->end = (offset + 0xfff) & 0xfffffffful;
  1199. pr_debug("Candidate legacy IO: %pR\n", res);
  1200. if (request_resource(&hose->io_resource, res)) {
  1201. printk(KERN_DEBUG
  1202. "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
  1203. pci_domain_nr(bus), bus->number, res);
  1204. kfree(res);
  1205. }
  1206. no_io:
  1207. /* Check for memory */
  1208. for (i = 0; i < 3; i++) {
  1209. pres = &hose->mem_resources[i];
  1210. offset = hose->mem_offset[i];
  1211. if (!(pres->flags & IORESOURCE_MEM))
  1212. continue;
  1213. pr_debug("hose mem res: %pR\n", pres);
  1214. if ((pres->start - offset) <= 0xa0000 &&
  1215. (pres->end - offset) >= 0xbffff)
  1216. break;
  1217. }
  1218. if (i >= 3)
  1219. return;
  1220. res = kzalloc(sizeof(struct resource), GFP_KERNEL);
  1221. BUG_ON(res == NULL);
  1222. res->name = "Legacy VGA memory";
  1223. res->flags = IORESOURCE_MEM;
  1224. res->start = 0xa0000 + offset;
  1225. res->end = 0xbffff + offset;
  1226. pr_debug("Candidate VGA memory: %pR\n", res);
  1227. if (request_resource(pres, res)) {
  1228. printk(KERN_DEBUG
  1229. "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
  1230. pci_domain_nr(bus), bus->number, res);
  1231. kfree(res);
  1232. }
  1233. }
  1234. void __init pcibios_resource_survey(void)
  1235. {
  1236. struct pci_bus *b;
  1237. /* Allocate and assign resources */
  1238. list_for_each_entry(b, &pci_root_buses, node)
  1239. pcibios_allocate_bus_resources(b);
  1240. if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
  1241. pcibios_allocate_resources(0);
  1242. pcibios_allocate_resources(1);
  1243. }
  1244. /* Before we start assigning unassigned resource, we try to reserve
  1245. * the low IO area and the VGA memory area if they intersect the
  1246. * bus available resources to avoid allocating things on top of them
  1247. */
  1248. if (!pci_has_flag(PCI_PROBE_ONLY)) {
  1249. list_for_each_entry(b, &pci_root_buses, node)
  1250. pcibios_reserve_legacy_regions(b);
  1251. }
  1252. /* Now, if the platform didn't decide to blindly trust the firmware,
  1253. * we proceed to assigning things that were left unassigned
  1254. */
  1255. if (!pci_has_flag(PCI_PROBE_ONLY)) {
  1256. pr_debug("PCI: Assigning unassigned resources...\n");
  1257. pci_assign_unassigned_resources();
  1258. }
  1259. /* Call machine dependent fixup */
  1260. if (ppc_md.pcibios_fixup)
  1261. ppc_md.pcibios_fixup();
  1262. }
  1263. /* This is used by the PCI hotplug driver to allocate resource
  1264. * of newly plugged busses. We can try to consolidate with the
  1265. * rest of the code later, for now, keep it as-is as our main
  1266. * resource allocation function doesn't deal with sub-trees yet.
  1267. */
  1268. void pcibios_claim_one_bus(struct pci_bus *bus)
  1269. {
  1270. struct pci_dev *dev;
  1271. struct pci_bus *child_bus;
  1272. list_for_each_entry(dev, &bus->devices, bus_list) {
  1273. int i;
  1274. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  1275. struct resource *r = &dev->resource[i];
  1276. if (r->parent || !r->start || !r->flags)
  1277. continue;
  1278. pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
  1279. pci_name(dev), i, r);
  1280. if (pci_claim_resource(dev, i) == 0)
  1281. continue;
  1282. pci_claim_bridge_resource(dev, i);
  1283. }
  1284. }
  1285. list_for_each_entry(child_bus, &bus->children, node)
  1286. pcibios_claim_one_bus(child_bus);
  1287. }
  1288. EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
  1289. /* pcibios_finish_adding_to_bus
  1290. *
  1291. * This is to be called by the hotplug code after devices have been
  1292. * added to a bus, this include calling it for a PHB that is just
  1293. * being added
  1294. */
  1295. void pcibios_finish_adding_to_bus(struct pci_bus *bus)
  1296. {
  1297. pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
  1298. pci_domain_nr(bus), bus->number);
  1299. /* Allocate bus and devices resources */
  1300. pcibios_allocate_bus_resources(bus);
  1301. pcibios_claim_one_bus(bus);
  1302. if (!pci_has_flag(PCI_PROBE_ONLY)) {
  1303. if (bus->self)
  1304. pci_assign_unassigned_bridge_resources(bus->self);
  1305. else
  1306. pci_assign_unassigned_bus_resources(bus);
  1307. }
  1308. /* Fixup EEH */
  1309. eeh_add_device_tree_late(bus);
  1310. /* Add new devices to global lists. Register in proc, sysfs. */
  1311. pci_bus_add_devices(bus);
  1312. /* sysfs files should only be added after devices are added */
  1313. eeh_add_sysfs_files(bus);
  1314. }
  1315. EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
  1316. int pcibios_enable_device(struct pci_dev *dev, int mask)
  1317. {
  1318. struct pci_controller *phb = pci_bus_to_host(dev->bus);
  1319. if (phb->controller_ops.enable_device_hook)
  1320. if (!phb->controller_ops.enable_device_hook(dev))
  1321. return -EINVAL;
  1322. return pci_enable_resources(dev, mask);
  1323. }
  1324. void pcibios_disable_device(struct pci_dev *dev)
  1325. {
  1326. struct pci_controller *phb = pci_bus_to_host(dev->bus);
  1327. if (phb->controller_ops.disable_device)
  1328. phb->controller_ops.disable_device(dev);
  1329. }
  1330. resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
  1331. {
  1332. return (unsigned long) hose->io_base_virt - _IO_BASE;
  1333. }
  1334. static void pcibios_setup_phb_resources(struct pci_controller *hose,
  1335. struct list_head *resources)
  1336. {
  1337. struct resource *res;
  1338. resource_size_t offset;
  1339. int i;
  1340. /* Hookup PHB IO resource */
  1341. res = &hose->io_resource;
  1342. if (!res->flags) {
  1343. pr_debug("PCI: I/O resource not set for host"
  1344. " bridge %s (domain %d)\n",
  1345. hose->dn->full_name, hose->global_number);
  1346. } else {
  1347. offset = pcibios_io_space_offset(hose);
  1348. pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
  1349. res, (unsigned long long)offset);
  1350. pci_add_resource_offset(resources, res, offset);
  1351. }
  1352. /* Hookup PHB Memory resources */
  1353. for (i = 0; i < 3; ++i) {
  1354. res = &hose->mem_resources[i];
  1355. if (!res->flags) {
  1356. if (i == 0)
  1357. printk(KERN_ERR "PCI: Memory resource 0 not set for "
  1358. "host bridge %s (domain %d)\n",
  1359. hose->dn->full_name, hose->global_number);
  1360. continue;
  1361. }
  1362. offset = hose->mem_offset[i];
  1363. pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
  1364. res, (unsigned long long)offset);
  1365. pci_add_resource_offset(resources, res, offset);
  1366. }
  1367. }
  1368. /*
  1369. * Null PCI config access functions, for the case when we can't
  1370. * find a hose.
  1371. */
  1372. #define NULL_PCI_OP(rw, size, type) \
  1373. static int \
  1374. null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
  1375. { \
  1376. return PCIBIOS_DEVICE_NOT_FOUND; \
  1377. }
  1378. static int
  1379. null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
  1380. int len, u32 *val)
  1381. {
  1382. return PCIBIOS_DEVICE_NOT_FOUND;
  1383. }
  1384. static int
  1385. null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
  1386. int len, u32 val)
  1387. {
  1388. return PCIBIOS_DEVICE_NOT_FOUND;
  1389. }
  1390. static struct pci_ops null_pci_ops =
  1391. {
  1392. .read = null_read_config,
  1393. .write = null_write_config,
  1394. };
  1395. /*
  1396. * These functions are used early on before PCI scanning is done
  1397. * and all of the pci_dev and pci_bus structures have been created.
  1398. */
  1399. static struct pci_bus *
  1400. fake_pci_bus(struct pci_controller *hose, int busnr)
  1401. {
  1402. static struct pci_bus bus;
  1403. if (hose == NULL) {
  1404. printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
  1405. }
  1406. bus.number = busnr;
  1407. bus.sysdata = hose;
  1408. bus.ops = hose? hose->ops: &null_pci_ops;
  1409. return &bus;
  1410. }
  1411. #define EARLY_PCI_OP(rw, size, type) \
  1412. int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
  1413. int devfn, int offset, type value) \
  1414. { \
  1415. return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
  1416. devfn, offset, value); \
  1417. }
  1418. EARLY_PCI_OP(read, byte, u8 *)
  1419. EARLY_PCI_OP(read, word, u16 *)
  1420. EARLY_PCI_OP(read, dword, u32 *)
  1421. EARLY_PCI_OP(write, byte, u8)
  1422. EARLY_PCI_OP(write, word, u16)
  1423. EARLY_PCI_OP(write, dword, u32)
  1424. int early_find_capability(struct pci_controller *hose, int bus, int devfn,
  1425. int cap)
  1426. {
  1427. return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
  1428. }
  1429. struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
  1430. {
  1431. struct pci_controller *hose = bus->sysdata;
  1432. return of_node_get(hose->dn);
  1433. }
  1434. /**
  1435. * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
  1436. * @hose: Pointer to the PCI host controller instance structure
  1437. */
  1438. void pcibios_scan_phb(struct pci_controller *hose)
  1439. {
  1440. LIST_HEAD(resources);
  1441. struct pci_bus *bus;
  1442. struct device_node *node = hose->dn;
  1443. int mode;
  1444. pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
  1445. /* Get some IO space for the new PHB */
  1446. pcibios_setup_phb_io_space(hose);
  1447. /* Wire up PHB bus resources */
  1448. pcibios_setup_phb_resources(hose, &resources);
  1449. hose->busn.start = hose->first_busno;
  1450. hose->busn.end = hose->last_busno;
  1451. hose->busn.flags = IORESOURCE_BUS;
  1452. pci_add_resource(&resources, &hose->busn);
  1453. /* Create an empty bus for the toplevel */
  1454. bus = pci_create_root_bus(hose->parent, hose->first_busno,
  1455. hose->ops, hose, &resources);
  1456. if (bus == NULL) {
  1457. pr_err("Failed to create bus for PCI domain %04x\n",
  1458. hose->global_number);
  1459. pci_free_resource_list(&resources);
  1460. return;
  1461. }
  1462. hose->bus = bus;
  1463. /* Get probe mode and perform scan */
  1464. mode = PCI_PROBE_NORMAL;
  1465. if (node && hose->controller_ops.probe_mode)
  1466. mode = hose->controller_ops.probe_mode(bus);
  1467. pr_debug(" probe mode: %d\n", mode);
  1468. if (mode == PCI_PROBE_DEVTREE)
  1469. of_scan_bus(node, bus);
  1470. if (mode == PCI_PROBE_NORMAL) {
  1471. pci_bus_update_busn_res_end(bus, 255);
  1472. hose->last_busno = pci_scan_child_bus(bus);
  1473. pci_bus_update_busn_res_end(bus, hose->last_busno);
  1474. }
  1475. /* Platform gets a chance to do some global fixups before
  1476. * we proceed to resource allocation
  1477. */
  1478. if (ppc_md.pcibios_fixup_phb)
  1479. ppc_md.pcibios_fixup_phb(hose);
  1480. /* Configure PCI Express settings */
  1481. if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
  1482. struct pci_bus *child;
  1483. list_for_each_entry(child, &bus->children, node)
  1484. pcie_bus_configure_settings(child);
  1485. }
  1486. }
  1487. EXPORT_SYMBOL_GPL(pcibios_scan_phb);
  1488. static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
  1489. {
  1490. int i, class = dev->class >> 8;
  1491. /* When configured as agent, programing interface = 1 */
  1492. int prog_if = dev->class & 0xf;
  1493. if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
  1494. class == PCI_CLASS_BRIDGE_OTHER) &&
  1495. (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
  1496. (prog_if == 0) &&
  1497. (dev->bus->parent == NULL)) {
  1498. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  1499. dev->resource[i].start = 0;
  1500. dev->resource[i].end = 0;
  1501. dev->resource[i].flags = 0;
  1502. }
  1503. }
  1504. }
  1505. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
  1506. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
  1507. static void fixup_vga(struct pci_dev *pdev)
  1508. {
  1509. u16 cmd;
  1510. pci_read_config_word(pdev, PCI_COMMAND, &cmd);
  1511. if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
  1512. vga_set_default_device(pdev);
  1513. }
  1514. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
  1515. PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);