cpu_setup_power.S 4.5 KB

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  1. /*
  2. * This file contains low level CPU setup functions.
  3. * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version
  8. * 2 of the License, or (at your option) any later version.
  9. *
  10. */
  11. #include <asm/processor.h>
  12. #include <asm/page.h>
  13. #include <asm/cputable.h>
  14. #include <asm/ppc_asm.h>
  15. #include <asm/asm-offsets.h>
  16. #include <asm/cache.h>
  17. #include <asm/book3s/64/mmu-hash.h>
  18. /* Entry: r3 = crap, r4 = ptr to cputable entry
  19. *
  20. * Note that we can be called twice for pseudo-PVRs
  21. */
  22. _GLOBAL(__setup_cpu_power7)
  23. mflr r11
  24. bl __init_hvmode_206
  25. mtlr r11
  26. beqlr
  27. li r0,0
  28. mtspr SPRN_LPID,r0
  29. mtspr SPRN_PCR,r0
  30. mfspr r3,SPRN_LPCR
  31. bl __init_LPCR
  32. bl __init_tlb_power7
  33. mtlr r11
  34. blr
  35. _GLOBAL(__restore_cpu_power7)
  36. mflr r11
  37. mfmsr r3
  38. rldicl. r0,r3,4,63
  39. beqlr
  40. li r0,0
  41. mtspr SPRN_LPID,r0
  42. mtspr SPRN_PCR,r0
  43. mfspr r3,SPRN_LPCR
  44. bl __init_LPCR
  45. bl __init_tlb_power7
  46. mtlr r11
  47. blr
  48. _GLOBAL(__setup_cpu_power8)
  49. mflr r11
  50. bl __init_FSCR
  51. bl __init_PMU
  52. bl __init_PMU_ISA207
  53. bl __init_hvmode_206
  54. mtlr r11
  55. beqlr
  56. li r0,0
  57. mtspr SPRN_LPID,r0
  58. mtspr SPRN_PCR,r0
  59. mfspr r3,SPRN_LPCR
  60. ori r3, r3, LPCR_PECEDH
  61. bl __init_LPCR
  62. bl __init_HFSCR
  63. bl __init_tlb_power8
  64. bl __init_PMU_HV
  65. bl __init_PMU_HV_ISA207
  66. mtlr r11
  67. blr
  68. _GLOBAL(__restore_cpu_power8)
  69. mflr r11
  70. bl __init_FSCR
  71. bl __init_PMU
  72. bl __init_PMU_ISA207
  73. mfmsr r3
  74. rldicl. r0,r3,4,63
  75. mtlr r11
  76. beqlr
  77. li r0,0
  78. mtspr SPRN_LPID,r0
  79. mtspr SPRN_PCR,r0
  80. mfspr r3,SPRN_LPCR
  81. ori r3, r3, LPCR_PECEDH
  82. bl __init_LPCR
  83. bl __init_HFSCR
  84. bl __init_tlb_power8
  85. bl __init_PMU_HV
  86. bl __init_PMU_HV_ISA207
  87. mtlr r11
  88. blr
  89. _GLOBAL(__setup_cpu_power9)
  90. mflr r11
  91. bl __init_FSCR
  92. bl __init_PMU
  93. bl __init_hvmode_206
  94. mtlr r11
  95. beqlr
  96. li r0,0
  97. mtspr SPRN_LPID,r0
  98. mtspr SPRN_PID,r0
  99. mtspr SPRN_PCR,r0
  100. mfspr r3,SPRN_LPCR
  101. LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
  102. or r3, r3, r4
  103. LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
  104. andc r3, r3, r4
  105. bl __init_LPCR
  106. bl __init_HFSCR
  107. bl __init_tlb_power9
  108. bl __init_PMU_HV
  109. mtlr r11
  110. blr
  111. _GLOBAL(__restore_cpu_power9)
  112. mflr r11
  113. bl __init_FSCR
  114. bl __init_PMU
  115. mfmsr r3
  116. rldicl. r0,r3,4,63
  117. mtlr r11
  118. beqlr
  119. li r0,0
  120. mtspr SPRN_LPID,r0
  121. mtspr SPRN_PID,r0
  122. mtspr SPRN_PCR,r0
  123. mfspr r3,SPRN_LPCR
  124. LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
  125. or r3, r3, r4
  126. LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
  127. andc r3, r3, r4
  128. bl __init_LPCR
  129. bl __init_HFSCR
  130. bl __init_tlb_power9
  131. bl __init_PMU_HV
  132. mtlr r11
  133. blr
  134. __init_hvmode_206:
  135. /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
  136. mfmsr r3
  137. rldicl. r0,r3,4,63
  138. bnelr
  139. ld r5,CPU_SPEC_FEATURES(r4)
  140. LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
  141. xor r5,r5,r6
  142. std r5,CPU_SPEC_FEATURES(r4)
  143. blr
  144. __init_LPCR:
  145. /* Setup a sane LPCR:
  146. * Called with initial LPCR in R3
  147. *
  148. * LPES = 0b01 (HSRR0/1 used for 0x500)
  149. * PECE = 0b111
  150. * DPFD = 4
  151. * HDICE = 0
  152. * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
  153. * VRMASD = 0b10000 (L=1, LP=00)
  154. *
  155. * Other bits untouched for now
  156. */
  157. li r5,1
  158. rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
  159. ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
  160. li r5,4
  161. rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
  162. clrrdi r3,r3,1 /* clear HDICE */
  163. li r5,4
  164. rldimi r3,r5, LPCR_VC_SH, 0
  165. li r5,0x10
  166. rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
  167. mtspr SPRN_LPCR,r3
  168. isync
  169. blr
  170. __init_FSCR:
  171. mfspr r3,SPRN_FSCR
  172. ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
  173. mtspr SPRN_FSCR,r3
  174. blr
  175. __init_HFSCR:
  176. mfspr r3,SPRN_HFSCR
  177. ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
  178. HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
  179. mtspr SPRN_HFSCR,r3
  180. blr
  181. /*
  182. * Clear the TLB using the specified IS form of tlbiel instruction
  183. * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
  184. */
  185. __init_tlb_power7:
  186. li r6,POWER7_TLB_SETS
  187. mtctr r6
  188. li r7,0xc00 /* IS field = 0b11 */
  189. ptesync
  190. 2: tlbiel r7
  191. addi r7,r7,0x1000
  192. bdnz 2b
  193. ptesync
  194. 1: blr
  195. __init_tlb_power8:
  196. li r6,POWER8_TLB_SETS
  197. mtctr r6
  198. li r7,0xc00 /* IS field = 0b11 */
  199. ptesync
  200. 2: tlbiel r7
  201. addi r7,r7,0x1000
  202. bdnz 2b
  203. ptesync
  204. 1: blr
  205. __init_tlb_power9:
  206. li r6,POWER9_TLB_SETS_HASH
  207. mtctr r6
  208. li r7,0xc00 /* IS field = 0b11 */
  209. ptesync
  210. 2: tlbiel r7
  211. addi r7,r7,0x1000
  212. bdnz 2b
  213. ptesync
  214. 1: blr
  215. __init_PMU_HV:
  216. li r5,0
  217. mtspr SPRN_MMCRC,r5
  218. blr
  219. __init_PMU_HV_ISA207:
  220. li r5,0
  221. mtspr SPRN_MMCRH,r5
  222. blr
  223. __init_PMU:
  224. li r5,0
  225. mtspr SPRN_MMCRA,r5
  226. mtspr SPRN_MMCR0,r5
  227. mtspr SPRN_MMCR1,r5
  228. mtspr SPRN_MMCR2,r5
  229. blr
  230. __init_PMU_ISA207:
  231. li r5,0
  232. mtspr SPRN_MMCRS,r5
  233. blr