gamecube-head.S 2.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112
  1. /*
  2. * arch/powerpc/boot/gamecube-head.S
  3. *
  4. * Nintendo GameCube bootwrapper entry.
  5. * Copyright (C) 2004-2009 The GameCube Linux Team
  6. * Copyright (C) 2008,2009 Albert Herranz
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. *
  13. */
  14. #include "ppc_asm.h"
  15. /*
  16. * The entry code does no assumptions regarding:
  17. * - if the data and instruction caches are enabled or not
  18. * - if the MMU is enabled or not
  19. *
  20. * We enable the caches if not already enabled, enable the MMU with an
  21. * identity mapping scheme and jump to the start code.
  22. */
  23. .text
  24. .globl _zimage_start
  25. _zimage_start:
  26. /* turn the MMU off */
  27. mfmsr 9
  28. rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
  29. bcl 20, 31, 1f
  30. 1:
  31. mflr 8
  32. clrlwi 8, 8, 3 /* convert to a real address */
  33. addi 8, 8, _mmu_off - 1b
  34. mtsrr0 8
  35. mtsrr1 9
  36. rfi
  37. _mmu_off:
  38. /* MMU disabled */
  39. /* setup BATs */
  40. isync
  41. li 8, 0
  42. mtspr 0x210, 8 /* IBAT0U */
  43. mtspr 0x212, 8 /* IBAT1U */
  44. mtspr 0x214, 8 /* IBAT2U */
  45. mtspr 0x216, 8 /* IBAT3U */
  46. mtspr 0x218, 8 /* DBAT0U */
  47. mtspr 0x21a, 8 /* DBAT1U */
  48. mtspr 0x21c, 8 /* DBAT2U */
  49. mtspr 0x21e, 8 /* DBAT3U */
  50. li 8, 0x01ff /* first 16MiB */
  51. li 9, 0x0002 /* rw */
  52. mtspr 0x211, 9 /* IBAT0L */
  53. mtspr 0x210, 8 /* IBAT0U */
  54. mtspr 0x219, 9 /* DBAT0L */
  55. mtspr 0x218, 8 /* DBAT0U */
  56. lis 8, 0x0c00 /* I/O mem */
  57. ori 8, 8, 0x3ff /* 32MiB */
  58. lis 9, 0x0c00
  59. ori 9, 9, 0x002a /* uncached, guarded, rw */
  60. mtspr 0x21b, 9 /* DBAT1L */
  61. mtspr 0x21a, 8 /* DBAT1U */
  62. lis 8, 0x0100 /* next 8MiB */
  63. ori 8, 8, 0x00ff /* 8MiB */
  64. lis 9, 0x0100
  65. ori 9, 9, 0x0002 /* rw */
  66. mtspr 0x215, 9 /* IBAT2L */
  67. mtspr 0x214, 8 /* IBAT2U */
  68. mtspr 0x21d, 9 /* DBAT2L */
  69. mtspr 0x21c, 8 /* DBAT2U */
  70. /* enable and invalidate the caches if not already enabled */
  71. mfspr 8, 0x3f0 /* HID0 */
  72. andi. 0, 8, (1<<15) /* HID0_ICE */
  73. bne 1f
  74. ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/
  75. 1:
  76. andi. 0, 8, (1<<14) /* HID0_DCE */
  77. bne 1f
  78. ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/
  79. 1:
  80. mtspr 0x3f0, 8 /* HID0 */
  81. isync
  82. /* initialize arguments */
  83. li 3, 0
  84. li 4, 0
  85. li 5, 0
  86. /* turn the MMU on */
  87. bcl 20, 31, 1f
  88. 1:
  89. mflr 8
  90. addi 8, 8, _mmu_on - 1b
  91. mfmsr 9
  92. ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */
  93. mtsrr0 8
  94. mtsrr1 9
  95. sync
  96. rfi
  97. _mmu_on:
  98. b _zimage_start_lib