mvme5100.dts 4.4 KB

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  1. /*
  2. * Device Tree Source for Motorola/Emerson MVME5100.
  3. *
  4. * Copyright 2013 CSC Australia Pty. Ltd.
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without
  8. * any warranty of any kind, whether express or implied.
  9. */
  10. /dts-v1/;
  11. / {
  12. model = "MVME5100";
  13. compatible = "MVME5100";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. aliases {
  17. serial0 = &serial0;
  18. pci0 = &pci0;
  19. };
  20. cpus {
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. PowerPC,7410 {
  24. device_type = "cpu";
  25. reg = <0x0>;
  26. /* Following required by dtc but not used */
  27. d-cache-line-size = <32>;
  28. i-cache-line-size = <32>;
  29. i-cache-size = <32768>;
  30. d-cache-size = <32768>;
  31. timebase-frequency = <25000000>;
  32. clock-frequency = <500000000>;
  33. bus-frequency = <100000000>;
  34. };
  35. };
  36. memory {
  37. device_type = "memory";
  38. reg = <0x0 0x20000000>;
  39. };
  40. hawk@fef80000 {
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. compatible = "hawk-bridge", "simple-bus";
  44. ranges = <0x0 0xfef80000 0x10000>;
  45. reg = <0xfef80000 0x10000>;
  46. serial0: serial@8000 {
  47. device_type = "serial";
  48. compatible = "ns16550";
  49. reg = <0x8000 0x80>;
  50. reg-shift = <4>;
  51. clock-frequency = <1843200>;
  52. current-speed = <9600>;
  53. interrupts = <1 1>; // IRQ1 Level Active Low.
  54. interrupt-parent = <&mpic>;
  55. };
  56. serial1: serial@8200 {
  57. device_type = "serial";
  58. compatible = "ns16550";
  59. reg = <0x8200 0x80>;
  60. reg-shift = <4>;
  61. clock-frequency = <1843200>;
  62. current-speed = <9600>;
  63. interrupts = <1 1>; // IRQ1 Level Active Low.
  64. interrupt-parent = <&mpic>;
  65. };
  66. mpic: interrupt-controller@f3f80000 {
  67. #interrupt-cells = <2>;
  68. #address-cells = <0>;
  69. device_type = "open-pic";
  70. compatible = "chrp,open-pic";
  71. interrupt-controller;
  72. reg = <0xf3f80000 0x40000>;
  73. };
  74. };
  75. pci0: pci@feff0000 {
  76. #address-cells = <3>;
  77. #size-cells = <2>;
  78. #interrupt-cells = <1>;
  79. device_type = "pci";
  80. compatible = "hawk-pci";
  81. reg = <0xfec00000 0x400000>;
  82. 8259-interrupt-acknowledge = <0xfeff0030>;
  83. ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0x800000
  84. 0x2000000 0x0 0x80000000 0x80000000 0x0 0x74000000>;
  85. bus-range = <0 255>;
  86. clock-frequency = <33333333>;
  87. interrupt-parent = <&mpic>;
  88. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  89. interrupt-map = <
  90. /*
  91. * This definition (IDSEL 11) duplicates the
  92. * interrupts definition in the i8259
  93. * interrupt controller below.
  94. *
  95. * Do not change the interrupt sense/polarity from
  96. * 0x2 to anything else, doing so will cause endless
  97. * "spurious" i8259 interrupts to be fielded.
  98. */
  99. // IDSEL 11 - iPMC712 PCI/ISA Bridge
  100. 0x5800 0x0 0x0 0x1 &mpic 0x0 0x2
  101. 0x5800 0x0 0x0 0x2 &mpic 0x0 0x2
  102. 0x5800 0x0 0x0 0x3 &mpic 0x0 0x2
  103. 0x5800 0x0 0x0 0x4 &mpic 0x0 0x2
  104. /* IDSEL 12 - Not Used */
  105. /* IDSEL 13 - Universe VME Bridge */
  106. 0x6800 0x0 0x0 0x1 &mpic 0x5 0x1
  107. 0x6800 0x0 0x0 0x2 &mpic 0x6 0x1
  108. 0x6800 0x0 0x0 0x3 &mpic 0x7 0x1
  109. 0x6800 0x0 0x0 0x4 &mpic 0x8 0x1
  110. /* IDSEL 14 - ENET 1 */
  111. 0x7000 0x0 0x0 0x1 &mpic 0x2 0x1
  112. /* IDSEL 15 - Not Used */
  113. /* IDSEL 16 - PMC Slot 1 */
  114. 0x8000 0x0 0x0 0x1 &mpic 0x9 0x1
  115. 0x8000 0x0 0x0 0x2 &mpic 0xa 0x1
  116. 0x8000 0x0 0x0 0x3 &mpic 0xb 0x1
  117. 0x8000 0x0 0x0 0x4 &mpic 0xc 0x1
  118. /* IDSEL 17 - PMC Slot 2 */
  119. 0x8800 0x0 0x0 0x1 &mpic 0xc 0x1
  120. 0x8800 0x0 0x0 0x2 &mpic 0x9 0x1
  121. 0x8800 0x0 0x0 0x3 &mpic 0xa 0x1
  122. 0x8800 0x0 0x0 0x4 &mpic 0xb 0x1
  123. /* IDSEL 18 - Not Used */
  124. /* IDSEL 19 - ENET 2 */
  125. 0x9800 0x0 0x0 0x1 &mpic 0xd 0x1
  126. /* IDSEL 20 - PMCSPAN (PCI-X) */
  127. 0xa000 0x0 0x0 0x1 &mpic 0x9 0x1
  128. 0xa000 0x0 0x0 0x2 &mpic 0xa 0x1
  129. 0xa000 0x0 0x0 0x3 &mpic 0xb 0x1
  130. 0xa000 0x0 0x0 0x4 &mpic 0xc 0x1
  131. >;
  132. isa {
  133. #address-cells = <2>;
  134. #size-cells = <1>;
  135. #interrupt-cells = <2>;
  136. device_type = "isa";
  137. compatible = "isa";
  138. ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>;
  139. interrupt-parent = <&i8259>;
  140. i8259: interrupt-controller@20 {
  141. #interrupt-cells = <2>;
  142. #address-cells = <0>;
  143. interrupts = <0 2>;
  144. device_type = "interrupt-controller";
  145. compatible = "chrp,iic";
  146. interrupt-controller;
  147. reg = <1 0x00000020 0x00000002
  148. 1 0x000000a0 0x00000002
  149. 1 0x000004d0 0x00000002>;
  150. interrupt-parent = <&mpic>;
  151. };
  152. };
  153. };
  154. chosen {
  155. linux,stdout-path = &serial0;
  156. };
  157. };