mpc5121ads.dts 3.6 KB

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  1. /*
  2. * MPC5121E ADS Device Tree Source
  3. *
  4. * Copyright 2007-2008 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <mpc5121.dtsi>
  12. / {
  13. model = "mpc5121ads";
  14. compatible = "fsl,mpc5121ads", "fsl,mpc5121";
  15. nfc@40000000 {
  16. /*
  17. * ADS has two Hynix 512MB Nand flash chips in a single
  18. * stacked package.
  19. */
  20. chips = <2>;
  21. nand@0 {
  22. label = "nand";
  23. reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
  24. };
  25. };
  26. localbus@80000020 {
  27. ranges = <0x0 0x0 0xfc000000 0x04000000
  28. 0x2 0x0 0x82000000 0x00008000>;
  29. flash@0,0 {
  30. compatible = "cfi-flash";
  31. reg = <0 0x0 0x4000000>;
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. bank-width = <4>;
  35. device-width = <2>;
  36. protected@0 {
  37. label = "protected";
  38. reg = <0x00000000 0x00040000>; // first sector is protected
  39. read-only;
  40. };
  41. filesystem@40000 {
  42. label = "filesystem";
  43. reg = <0x00040000 0x03c00000>; // 60M for filesystem
  44. };
  45. kernel@3c40000 {
  46. label = "kernel";
  47. reg = <0x03c40000 0x00280000>; // 2.5M for kernel
  48. };
  49. device-tree@3ec0000 {
  50. label = "device-tree";
  51. reg = <0x03ec0000 0x00040000>; // one sector for device tree
  52. };
  53. u-boot@3f00000 {
  54. label = "u-boot";
  55. reg = <0x03f00000 0x00100000>; // 1M for u-boot
  56. read-only;
  57. };
  58. };
  59. board-control@2,0 {
  60. compatible = "fsl,mpc5121ads-cpld";
  61. reg = <0x2 0x0 0x8000>;
  62. };
  63. cpld_pic: pic@2,a {
  64. compatible = "fsl,mpc5121ads-cpld-pic";
  65. interrupt-controller;
  66. #interrupt-cells = <2>;
  67. reg = <0x2 0xa 0x5>;
  68. /* irq routing:
  69. * all irqs but touch screen are routed to irq0 (ipic 48)
  70. * touch screen is statically routed to irq1 (ipic 17)
  71. * so don't use it here
  72. */
  73. interrupts = <48 0x8>;
  74. };
  75. };
  76. soc@80000000 {
  77. i2c@1700 {
  78. fsl,preserve-clocking;
  79. hwmon@4a {
  80. compatible = "adi,ad7414";
  81. reg = <0x4a>;
  82. };
  83. eeprom@50 {
  84. compatible = "at,24c32";
  85. reg = <0x50>;
  86. };
  87. rtc@68 {
  88. compatible = "st,m41t62";
  89. reg = <0x68>;
  90. };
  91. };
  92. eth0: ethernet@2800 {
  93. phy-handle = <&phy0>;
  94. };
  95. can@2300 {
  96. status = "disabled";
  97. };
  98. can@2380 {
  99. status = "disabled";
  100. };
  101. viu@2400 {
  102. status = "disabled";
  103. };
  104. mdio@2800 {
  105. phy0: ethernet-phy@0 {
  106. reg = <1>;
  107. };
  108. };
  109. /* mpc5121ads only uses USB0 */
  110. usb@3000 {
  111. status = "disabled";
  112. };
  113. /* USB0 using internal UTMI PHY */
  114. usb@4000 {
  115. dr_mode = "host";
  116. fsl,invert-drvvbus;
  117. fsl,invert-pwr-fault;
  118. };
  119. /* PSC3 serial port A aka ttyPSC0 */
  120. psc@11300 {
  121. compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
  122. };
  123. /* PSC4 serial port B aka ttyPSC1 */
  124. psc@11400 {
  125. compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
  126. };
  127. /* PSC5 in ac97 mode */
  128. ac97: psc@11500 {
  129. compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
  130. fsl,mode = "ac97-slave";
  131. fsl,rx-fifo-size = <384>;
  132. fsl,tx-fifo-size = <384>;
  133. };
  134. };
  135. pci: pci@80008500 {
  136. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  137. interrupt-map = <
  138. /* IDSEL 0x15 - Slot 1 PCI */
  139. 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
  140. 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
  141. 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
  142. 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
  143. /* IDSEL 0x16 - Slot 2 MiniPCI */
  144. 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
  145. 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
  146. /* IDSEL 0x17 - Slot 3 MiniPCI */
  147. 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
  148. 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
  149. >;
  150. };
  151. };