t1024qds.dts 6.0 KB

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  1. /*
  2. * T1024 QDS Device Tree Source
  3. *
  4. * Copyright 2014 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. /include/ "t102xsi-pre.dtsi"
  35. / {
  36. model = "fsl,T1024QDS";
  37. compatible = "fsl,T1024QDS";
  38. #address-cells = <2>;
  39. #size-cells = <2>;
  40. interrupt-parent = <&mpic>;
  41. ifc: localbus@ffe124000 {
  42. reg = <0xf 0xfe124000 0 0x2000>;
  43. ranges = <0 0 0xf 0xe8000000 0x08000000
  44. 2 0 0xf 0xff800000 0x00010000
  45. 3 0 0xf 0xffdf0000 0x00008000>;
  46. nor@0,0 {
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. compatible = "cfi-flash";
  50. reg = <0x0 0x0 0x8000000>;
  51. bank-width = <2>;
  52. device-width = <1>;
  53. };
  54. nand@2,0 {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "fsl,ifc-nand";
  58. reg = <0x2 0x0 0x10000>;
  59. };
  60. board-control@3,0 {
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. compatible = "fsl,tetra-fpga", "fsl,fpga-qixis";
  64. reg = <3 0 0x300>;
  65. ranges = <0 3 0 0x300>;
  66. };
  67. };
  68. memory {
  69. device_type = "memory";
  70. };
  71. dcsr: dcsr@f00000000 {
  72. ranges = <0x00000000 0xf 0x00000000 0x01072000>;
  73. };
  74. soc: soc@ffe000000 {
  75. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  76. reg = <0xf 0xfe000000 0 0x00001000>;
  77. spi@110000 {
  78. flash@0 {
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
  82. reg = <0>;
  83. spi-max-frequency = <10000000>;
  84. };
  85. flash@1 {
  86. #address-cells = <1>;
  87. #size-cells = <1>;
  88. compatible = "sst,sst25wf040", "jedec,spi-nor"; /* 512KB */
  89. reg = <1>;
  90. spi-max-frequency = <10000000>;
  91. };
  92. flash@2 {
  93. #address-cells = <1>;
  94. #size-cells = <1>;
  95. compatible = "eon,en25s64", "jedec,spi-nor"; /* 8MB */
  96. reg = <2>;
  97. spi-max-frequency = <10000000>;
  98. };
  99. slic@2 {
  100. compatible = "maxim,ds26522";
  101. reg = <2>;
  102. spi-max-frequency = <2000000>;
  103. };
  104. slic@3 {
  105. compatible = "maxim,ds26522";
  106. reg = <3>;
  107. spi-max-frequency = <2000000>;
  108. };
  109. };
  110. i2c@118000 {
  111. pca9547@77 {
  112. compatible = "nxp,pca9547";
  113. reg = <0x77>;
  114. #address-cells = <1>;
  115. #size-cells = <0>;
  116. i2c@0 {
  117. #address-cells = <1>;
  118. #size-cells = <0>;
  119. reg = <0x0>;
  120. eeprom@50 {
  121. compatible = "atmel,24c512";
  122. reg = <0x50>;
  123. };
  124. eeprom@51 {
  125. compatible = "atmel,24c02";
  126. reg = <0x51>;
  127. };
  128. eeprom@57 {
  129. compatible = "atmel,24c02";
  130. reg = <0x57>;
  131. };
  132. };
  133. i2c@2 {
  134. #address-cells = <1>;
  135. #size-cells = <0>;
  136. reg = <0x2>;
  137. ina220@40 {
  138. compatible = "ti,ina220";
  139. reg = <0x40>;
  140. shunt-resistor = <1000>;
  141. };
  142. ina220@41 {
  143. compatible = "ti,ina220";
  144. reg = <0x41>;
  145. shunt-resistor = <1000>;
  146. };
  147. };
  148. i2c@3 {
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. reg = <0x3>;
  152. adt7461@4c {
  153. /* Thermal Monitor */
  154. compatible = "adi,adt7461";
  155. reg = <0x4c>;
  156. };
  157. eeprom@55 {
  158. compatible = "atmel,24c02";
  159. reg = <0x55>;
  160. };
  161. eeprom@56 {
  162. compatible = "atmel,24c512";
  163. reg = <0x56>;
  164. };
  165. eeprom@57 {
  166. compatible = "atmel,24c512";
  167. reg = <0x57>;
  168. };
  169. };
  170. };
  171. rtc@68 {
  172. compatible = "dallas,ds3232";
  173. reg = <0x68>;
  174. interrupts = <0x5 0x1 0 0>;
  175. };
  176. };
  177. };
  178. pci0: pcie@ffe240000 {
  179. reg = <0xf 0xfe240000 0 0x10000>;
  180. ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000
  181. 0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>;
  182. pcie@0 {
  183. ranges = <0x02000000 0 0xe0000000
  184. 0x02000000 0 0xe0000000
  185. 0 0x10000000
  186. 0x01000000 0 0x00000000
  187. 0x01000000 0 0x00000000
  188. 0 0x00010000>;
  189. };
  190. };
  191. pci1: pcie@ffe250000 {
  192. reg = <0xf 0xfe250000 0 0x10000>;
  193. ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
  194. 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
  195. pcie@0 {
  196. ranges = <0x02000000 0 0xe0000000
  197. 0x02000000 0 0xe0000000
  198. 0 0x10000000
  199. 0x01000000 0 0x00000000
  200. 0x01000000 0 0x00000000
  201. 0 0x00010000>;
  202. };
  203. };
  204. pci2: pcie@ffe260000 {
  205. reg = <0xf 0xfe260000 0 0x10000>;
  206. ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
  207. 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
  208. pcie@0 {
  209. ranges = <0x02000000 0 0xe0000000
  210. 0x02000000 0 0xe0000000
  211. 0 0x10000000
  212. 0x01000000 0 0x00000000
  213. 0x01000000 0 0x00000000
  214. 0 0x00010000>;
  215. };
  216. };
  217. };
  218. #include "t1024si-post.dtsi"