qoriq-sec4.0-0.dtsi 3.2 KB

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  1. /*
  2. * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. crypto: crypto@300000 {
  35. compatible = "fsl,sec-v4.0";
  36. fsl,sec-era = <1>;
  37. #address-cells = <1>;
  38. #size-cells = <1>;
  39. reg = <0x300000 0x10000>;
  40. ranges = <0 0x300000 0x10000>;
  41. interrupts = <92 2 0 0>;
  42. sec_jr0: jr@1000 {
  43. compatible = "fsl,sec-v4.0-job-ring";
  44. reg = <0x1000 0x1000>;
  45. interrupts = <88 2 0 0>;
  46. };
  47. sec_jr1: jr@2000 {
  48. compatible = "fsl,sec-v4.0-job-ring";
  49. reg = <0x2000 0x1000>;
  50. interrupts = <89 2 0 0>;
  51. };
  52. sec_jr2: jr@3000 {
  53. compatible = "fsl,sec-v4.0-job-ring";
  54. reg = <0x3000 0x1000>;
  55. interrupts = <90 2 0 0>;
  56. };
  57. sec_jr3: jr@4000 {
  58. compatible = "fsl,sec-v4.0-job-ring";
  59. reg = <0x4000 0x1000>;
  60. interrupts = <91 2 0 0>;
  61. };
  62. rtic@6000 {
  63. compatible = "fsl,sec-v4.0-rtic";
  64. #address-cells = <1>;
  65. #size-cells = <1>;
  66. reg = <0x6000 0x100>;
  67. ranges = <0x0 0x6100 0xe00>;
  68. rtic_a: rtic-a@0 {
  69. compatible = "fsl,sec-v4.0-rtic-memory";
  70. reg = <0x00 0x20 0x100 0x80>;
  71. };
  72. rtic_b: rtic-b@20 {
  73. compatible = "fsl,sec-v4.0-rtic-memory";
  74. reg = <0x20 0x20 0x200 0x80>;
  75. };
  76. rtic_c: rtic-c@40 {
  77. compatible = "fsl,sec-v4.0-rtic-memory";
  78. reg = <0x40 0x20 0x300 0x80>;
  79. };
  80. rtic_d: rtic-d@60 {
  81. compatible = "fsl,sec-v4.0-rtic-memory";
  82. reg = <0x60 0x20 0x500 0x80>;
  83. };
  84. };
  85. };
  86. sec_mon: sec_mon@314000 {
  87. compatible = "fsl,sec-v4.0-mon";
  88. reg = <0x314000 0x1000>;
  89. interrupts = <93 2 0 0>;
  90. };