qoriq-mpic.dtsi 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107
  1. /*
  2. * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. mpic: pic@40000 {
  35. interrupt-controller;
  36. #address-cells = <0>;
  37. #interrupt-cells = <4>;
  38. reg = <0x40000 0x40000>;
  39. compatible = "fsl,mpic", "chrp,open-pic";
  40. device_type = "open-pic";
  41. clock-frequency = <0x0>;
  42. };
  43. timer@41100 {
  44. compatible = "fsl,mpic-global-timer";
  45. reg = <0x41100 0x100 0x41300 4>;
  46. interrupts = <0 0 3 0
  47. 1 0 3 0
  48. 2 0 3 0
  49. 3 0 3 0>;
  50. };
  51. msi0: msi@41600 {
  52. compatible = "fsl,mpic-msi";
  53. reg = <0x41600 0x200 0x44140 4>;
  54. msi-available-ranges = <0 0x100>;
  55. interrupts = <
  56. 0xe0 0 0 0
  57. 0xe1 0 0 0
  58. 0xe2 0 0 0
  59. 0xe3 0 0 0
  60. 0xe4 0 0 0
  61. 0xe5 0 0 0
  62. 0xe6 0 0 0
  63. 0xe7 0 0 0>;
  64. };
  65. msi1: msi@41800 {
  66. compatible = "fsl,mpic-msi";
  67. reg = <0x41800 0x200 0x45140 4>;
  68. msi-available-ranges = <0 0x100>;
  69. interrupts = <
  70. 0xe8 0 0 0
  71. 0xe9 0 0 0
  72. 0xea 0 0 0
  73. 0xeb 0 0 0
  74. 0xec 0 0 0
  75. 0xed 0 0 0
  76. 0xee 0 0 0
  77. 0xef 0 0 0>;
  78. };
  79. msi2: msi@41a00 {
  80. compatible = "fsl,mpic-msi";
  81. reg = <0x41a00 0x200 0x46140 4>;
  82. msi-available-ranges = <0 0x100>;
  83. interrupts = <
  84. 0xf0 0 0 0
  85. 0xf1 0 0 0
  86. 0xf2 0 0 0
  87. 0xf3 0 0 0
  88. 0xf4 0 0 0
  89. 0xf5 0 0 0
  90. 0xf6 0 0 0
  91. 0xf7 0 0 0>;
  92. };
  93. timer@42100 {
  94. compatible = "fsl,mpic-global-timer";
  95. reg = <0x42100 0x100 0x42300 4>;
  96. interrupts = <4 0 3 0
  97. 5 0 3 0
  98. 6 0 3 0
  99. 7 0 3 0>;
  100. };