p5040si-post.dtsi 12 KB

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  1. /*
  2. * P5040 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2012 - 2015 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * This software is provided by Freescale Semiconductor "as is" and any
  24. * express or implied warranties, including, but not limited to, the implied
  25. * warranties of merchantability and fitness for a particular purpose are
  26. * disclaimed. In no event shall Freescale Semiconductor be liable for any
  27. * direct, indirect, incidental, special, exemplary, or consequential damages
  28. * (including, but not limited to, procurement of substitute goods or services;
  29. * loss of use, data, or profits; or business interruption) however caused and
  30. * on any theory of liability, whether in contract, strict liability, or tort
  31. * (including negligence or otherwise) arising in any way out of the use of this
  32. * software, even if advised of the possibility of such damage.
  33. */
  34. &bman_fbpr {
  35. compatible = "fsl,bman-fbpr";
  36. alloc-ranges = <0 0 0x10000 0>;
  37. };
  38. &qman_fqd {
  39. compatible = "fsl,qman-fqd";
  40. alloc-ranges = <0 0 0x10000 0>;
  41. };
  42. &qman_pfdr {
  43. compatible = "fsl,qman-pfdr";
  44. alloc-ranges = <0 0 0x10000 0>;
  45. };
  46. &lbc {
  47. compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
  48. interrupts = <25 2 0 0>;
  49. #address-cells = <2>;
  50. #size-cells = <1>;
  51. };
  52. /* controller at 0x200000 */
  53. &pci0 {
  54. compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
  55. device_type = "pci";
  56. #size-cells = <2>;
  57. #address-cells = <3>;
  58. bus-range = <0x0 0xff>;
  59. clock-frequency = <33333333>;
  60. interrupts = <16 2 1 15>;
  61. fsl,iommu-parent = <&pamu0>;
  62. pcie@0 {
  63. reg = <0 0 0 0 0>;
  64. #interrupt-cells = <1>;
  65. #size-cells = <2>;
  66. #address-cells = <3>;
  67. device_type = "pci";
  68. interrupts = <16 2 1 15>;
  69. interrupt-map-mask = <0xf800 0 0 7>;
  70. interrupt-map = <
  71. /* IDSEL 0x0 */
  72. 0000 0 0 1 &mpic 40 1 0 0
  73. 0000 0 0 2 &mpic 1 1 0 0
  74. 0000 0 0 3 &mpic 2 1 0 0
  75. 0000 0 0 4 &mpic 3 1 0 0
  76. >;
  77. };
  78. };
  79. /* controller at 0x201000 */
  80. &pci1 {
  81. compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
  82. device_type = "pci";
  83. #size-cells = <2>;
  84. #address-cells = <3>;
  85. bus-range = <0 0xff>;
  86. clock-frequency = <33333333>;
  87. interrupts = <16 2 1 14>;
  88. fsl,iommu-parent = <&pamu0>;
  89. pcie@0 {
  90. reg = <0 0 0 0 0>;
  91. #interrupt-cells = <1>;
  92. #size-cells = <2>;
  93. #address-cells = <3>;
  94. device_type = "pci";
  95. interrupts = <16 2 1 14>;
  96. interrupt-map-mask = <0xf800 0 0 7>;
  97. interrupt-map = <
  98. /* IDSEL 0x0 */
  99. 0000 0 0 1 &mpic 41 1 0 0
  100. 0000 0 0 2 &mpic 5 1 0 0
  101. 0000 0 0 3 &mpic 6 1 0 0
  102. 0000 0 0 4 &mpic 7 1 0 0
  103. >;
  104. };
  105. };
  106. /* controller at 0x202000 */
  107. &pci2 {
  108. compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
  109. device_type = "pci";
  110. #size-cells = <2>;
  111. #address-cells = <3>;
  112. bus-range = <0x0 0xff>;
  113. clock-frequency = <33333333>;
  114. interrupts = <16 2 1 13>;
  115. fsl,iommu-parent = <&pamu0>;
  116. pcie@0 {
  117. reg = <0 0 0 0 0>;
  118. #interrupt-cells = <1>;
  119. #size-cells = <2>;
  120. #address-cells = <3>;
  121. device_type = "pci";
  122. interrupts = <16 2 1 13>;
  123. interrupt-map-mask = <0xf800 0 0 7>;
  124. interrupt-map = <
  125. /* IDSEL 0x0 */
  126. 0000 0 0 1 &mpic 42 1 0 0
  127. 0000 0 0 2 &mpic 9 1 0 0
  128. 0000 0 0 3 &mpic 10 1 0 0
  129. 0000 0 0 4 &mpic 11 1 0 0
  130. >;
  131. };
  132. };
  133. &dcsr {
  134. #address-cells = <1>;
  135. #size-cells = <1>;
  136. compatible = "fsl,dcsr", "simple-bus";
  137. dcsr-epu@0 {
  138. compatible = "fsl,p5040-dcsr-epu", "fsl,dcsr-epu";
  139. interrupts = <52 2 0 0
  140. 84 2 0 0
  141. 85 2 0 0>;
  142. reg = <0x0 0x1000>;
  143. };
  144. dcsr-npc {
  145. compatible = "fsl,dcsr-npc";
  146. reg = <0x1000 0x1000 0x1000000 0x8000>;
  147. };
  148. dcsr-nxc@2000 {
  149. compatible = "fsl,dcsr-nxc";
  150. reg = <0x2000 0x1000>;
  151. };
  152. dcsr-corenet {
  153. compatible = "fsl,dcsr-corenet";
  154. reg = <0x8000 0x1000 0xB0000 0x1000>;
  155. };
  156. dcsr-dpaa@9000 {
  157. compatible = "fsl,p5040-dcsr-dpaa", "fsl,dcsr-dpaa";
  158. reg = <0x9000 0x1000>;
  159. };
  160. dcsr-ocn@11000 {
  161. compatible = "fsl,p5040-dcsr-ocn", "fsl,dcsr-ocn";
  162. reg = <0x11000 0x1000>;
  163. };
  164. dcsr-ddr@12000 {
  165. compatible = "fsl,dcsr-ddr";
  166. dev-handle = <&ddr1>;
  167. reg = <0x12000 0x1000>;
  168. };
  169. dcsr-ddr@13000 {
  170. compatible = "fsl,dcsr-ddr";
  171. dev-handle = <&ddr2>;
  172. reg = <0x13000 0x1000>;
  173. };
  174. dcsr-nal@18000 {
  175. compatible = "fsl,p5040-dcsr-nal", "fsl,dcsr-nal";
  176. reg = <0x18000 0x1000>;
  177. };
  178. dcsr-rcpm@22000 {
  179. compatible = "fsl,p5040-dcsr-rcpm", "fsl,dcsr-rcpm";
  180. reg = <0x22000 0x1000>;
  181. };
  182. dcsr-cpu-sb-proxy@40000 {
  183. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  184. cpu-handle = <&cpu0>;
  185. reg = <0x40000 0x1000>;
  186. };
  187. dcsr-cpu-sb-proxy@41000 {
  188. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  189. cpu-handle = <&cpu1>;
  190. reg = <0x41000 0x1000>;
  191. };
  192. dcsr-cpu-sb-proxy@42000 {
  193. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  194. cpu-handle = <&cpu2>;
  195. reg = <0x42000 0x1000>;
  196. };
  197. dcsr-cpu-sb-proxy@43000 {
  198. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  199. cpu-handle = <&cpu3>;
  200. reg = <0x43000 0x1000>;
  201. };
  202. };
  203. /include/ "qoriq-bman1-portals.dtsi"
  204. /include/ "qoriq-qman1-portals.dtsi"
  205. &soc {
  206. #address-cells = <1>;
  207. #size-cells = <1>;
  208. device_type = "soc";
  209. compatible = "simple-bus";
  210. soc-sram-error {
  211. compatible = "fsl,soc-sram-error";
  212. interrupts = <16 2 1 29>;
  213. };
  214. corenet-law@0 {
  215. compatible = "fsl,corenet-law";
  216. reg = <0x0 0x1000>;
  217. fsl,num-laws = <32>;
  218. };
  219. ddr1: memory-controller@8000 {
  220. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  221. reg = <0x8000 0x1000>;
  222. interrupts = <16 2 1 23>;
  223. };
  224. ddr2: memory-controller@9000 {
  225. compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
  226. reg = <0x9000 0x1000>;
  227. interrupts = <16 2 1 22>;
  228. };
  229. cpc: l3-cache-controller@10000 {
  230. compatible = "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
  231. reg = <0x10000 0x1000
  232. 0x11000 0x1000>;
  233. interrupts = <16 2 1 27
  234. 16 2 1 26>;
  235. };
  236. corenet-cf@18000 {
  237. compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
  238. reg = <0x18000 0x1000>;
  239. interrupts = <16 2 1 31>;
  240. fsl,ccf-num-csdids = <32>;
  241. fsl,ccf-num-snoopids = <32>;
  242. };
  243. iommu@20000 {
  244. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  245. reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */
  246. ranges = <0 0x20000 0x5000>;
  247. #address-cells = <1>;
  248. #size-cells = <1>;
  249. interrupts = <24 2 0 0
  250. 16 2 1 30>;
  251. fsl,portid-mapping = <0x0f800000>;
  252. pamu0: pamu@0 {
  253. reg = <0 0x1000>;
  254. fsl,primary-cache-geometry = <32 1>;
  255. fsl,secondary-cache-geometry = <128 2>;
  256. };
  257. pamu1: pamu@1000 {
  258. reg = <0x1000 0x1000>;
  259. fsl,primary-cache-geometry = <32 1>;
  260. fsl,secondary-cache-geometry = <128 2>;
  261. };
  262. pamu2: pamu@2000 {
  263. reg = <0x2000 0x1000>;
  264. fsl,primary-cache-geometry = <32 1>;
  265. fsl,secondary-cache-geometry = <128 2>;
  266. };
  267. pamu3: pamu@3000 {
  268. reg = <0x3000 0x1000>;
  269. fsl,primary-cache-geometry = <32 1>;
  270. fsl,secondary-cache-geometry = <128 2>;
  271. };
  272. pamu4: pamu@4000 {
  273. reg = <0x4000 0x1000>;
  274. fsl,primary-cache-geometry = <32 1>;
  275. fsl,secondary-cache-geometry = <128 2>;
  276. };
  277. };
  278. /include/ "qoriq-mpic.dtsi"
  279. guts: global-utilities@e0000 {
  280. compatible = "fsl,p5040-device-config", "fsl,qoriq-device-config-1.0";
  281. reg = <0xe0000 0xe00>;
  282. fsl,has-rstcr;
  283. #sleep-cells = <1>;
  284. fsl,liodn-bits = <12>;
  285. };
  286. pins: global-utilities@e0e00 {
  287. compatible = "fsl,p5040-pin-control", "fsl,qoriq-pin-control-1.0";
  288. reg = <0xe0e00 0x200>;
  289. #sleep-cells = <2>;
  290. };
  291. /include/ "qoriq-clockgen1.dtsi"
  292. global-utilities@e1000 {
  293. compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
  294. mux2: mux2@40 {
  295. #clock-cells = <0>;
  296. reg = <0x40 0x4>;
  297. compatible = "fsl,qoriq-core-mux-1.0";
  298. clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
  299. clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
  300. clock-output-names = "cmux2";
  301. };
  302. mux3: mux3@60 {
  303. #clock-cells = <0>;
  304. reg = <0x60 0x4>;
  305. compatible = "fsl,qoriq-core-mux-1.0";
  306. clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
  307. clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
  308. clock-output-names = "cmux3";
  309. };
  310. };
  311. rcpm: global-utilities@e2000 {
  312. compatible = "fsl,p5040-rcpm", "fsl,qoriq-rcpm-1.0";
  313. reg = <0xe2000 0x1000>;
  314. #sleep-cells = <1>;
  315. };
  316. sfp: sfp@e8000 {
  317. compatible = "fsl,p5040-sfp", "fsl,qoriq-sfp-1.0";
  318. reg = <0xe8000 0x1000>;
  319. };
  320. serdes: serdes@ea000 {
  321. compatible = "fsl,p5040-serdes";
  322. reg = <0xea000 0x1000>;
  323. };
  324. /include/ "qoriq-dma-0.dtsi"
  325. dma@100300 {
  326. fsl,iommu-parent = <&pamu0>;
  327. fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
  328. };
  329. /include/ "qoriq-dma-1.dtsi"
  330. dma@101300 {
  331. fsl,iommu-parent = <&pamu0>;
  332. fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
  333. };
  334. /include/ "qoriq-espi-0.dtsi"
  335. spi@110000 {
  336. fsl,espi-num-chipselects = <4>;
  337. };
  338. /include/ "qoriq-esdhc-0.dtsi"
  339. sdhc@114000 {
  340. compatible = "fsl,p5040-esdhc", "fsl,esdhc";
  341. fsl,iommu-parent = <&pamu2>;
  342. fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
  343. sdhci,auto-cmd12;
  344. };
  345. /include/ "qoriq-i2c-0.dtsi"
  346. /include/ "qoriq-i2c-1.dtsi"
  347. /include/ "qoriq-duart-0.dtsi"
  348. /include/ "qoriq-duart-1.dtsi"
  349. /include/ "qoriq-gpio-0.dtsi"
  350. /include/ "qoriq-usb2-mph-0.dtsi"
  351. usb0: usb@210000 {
  352. compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  353. fsl,iommu-parent = <&pamu4>;
  354. fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
  355. phy_type = "utmi";
  356. port0;
  357. };
  358. /include/ "qoriq-usb2-dr-0.dtsi"
  359. usb1: usb@211000 {
  360. compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  361. fsl,iommu-parent = <&pamu4>;
  362. fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
  363. dr_mode = "host";
  364. phy_type = "utmi";
  365. };
  366. /include/ "qoriq-sata2-0.dtsi"
  367. sata@220000 {
  368. fsl,iommu-parent = <&pamu4>;
  369. fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
  370. };
  371. /include/ "qoriq-sata2-1.dtsi"
  372. sata@221000 {
  373. fsl,iommu-parent = <&pamu4>;
  374. fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
  375. };
  376. /include/ "qoriq-sec5.2-0.dtsi"
  377. crypto@300000 {
  378. fsl,iommu-parent = <&pamu4>;
  379. };
  380. /include/ "qoriq-raid1.0-0.dtsi"
  381. /include/ "qoriq-qman1.dtsi"
  382. /include/ "qoriq-bman1.dtsi"
  383. /include/ "qoriq-fman-0.dtsi"
  384. /include/ "qoriq-fman-0-1g-0.dtsi"
  385. /include/ "qoriq-fman-0-1g-1.dtsi"
  386. /include/ "qoriq-fman-0-1g-2.dtsi"
  387. /include/ "qoriq-fman-0-1g-3.dtsi"
  388. /include/ "qoriq-fman-0-1g-4.dtsi"
  389. /include/ "qoriq-fman-0-10g-0.dtsi"
  390. fman@400000 {
  391. enet0: ethernet@e0000 {
  392. };
  393. enet1: ethernet@e2000 {
  394. };
  395. enet2: ethernet@e4000 {
  396. };
  397. enet3: ethernet@e6000 {
  398. };
  399. enet4: ethernet@e8000 {
  400. };
  401. enet5: ethernet@f0000 {
  402. };
  403. };
  404. /include/ "qoriq-fman-1.dtsi"
  405. /include/ "qoriq-fman-1-1g-0.dtsi"
  406. /include/ "qoriq-fman-1-1g-1.dtsi"
  407. /include/ "qoriq-fman-1-1g-2.dtsi"
  408. /include/ "qoriq-fman-1-1g-3.dtsi"
  409. /include/ "qoriq-fman-1-1g-4.dtsi"
  410. /include/ "qoriq-fman-1-10g-0.dtsi"
  411. fman@500000 {
  412. enet6: ethernet@e0000 {
  413. };
  414. enet7: ethernet@e2000 {
  415. };
  416. enet8: ethernet@e4000 {
  417. };
  418. enet9: ethernet@e6000 {
  419. };
  420. enet10: ethernet@e8000 {
  421. };
  422. enet11: ethernet@f0000 {
  423. };
  424. };
  425. };