p1023si-post.dtsi 7.5 KB

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  1. /*
  2. * P1023/P1017 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 - 2014 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &bman_fbpr {
  35. compatible = "fsl,bman-fbpr";
  36. alloc-ranges = <0 0 0x10 0>;
  37. };
  38. &qman_fqd {
  39. compatible = "fsl,qman-fqd";
  40. alloc-ranges = <0 0 0x10 0>;
  41. };
  42. &qman_pfdr {
  43. compatible = "fsl,qman-pfdr";
  44. alloc-ranges = <0 0 0x10 0>;
  45. };
  46. &lbc {
  47. #address-cells = <2>;
  48. #size-cells = <1>;
  49. compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
  50. interrupts = <19 2 0 0>,
  51. <16 2 0 0>;
  52. };
  53. /* controller at 0xa000 */
  54. &pci0 {
  55. compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
  56. device_type = "pci";
  57. #size-cells = <2>;
  58. #address-cells = <3>;
  59. bus-range = <0x0 0xff>;
  60. clock-frequency = <33333333>;
  61. interrupts = <16 2 0 0>;
  62. pcie@0 {
  63. reg = <0 0 0 0 0>;
  64. #interrupt-cells = <1>;
  65. #size-cells = <2>;
  66. #address-cells = <3>;
  67. device_type = "pci";
  68. interrupts = <16 2 0 0>;
  69. };
  70. };
  71. /* controller at 0x9000 */
  72. &pci1 {
  73. compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
  74. device_type = "pci";
  75. #size-cells = <2>;
  76. #address-cells = <3>;
  77. bus-range = <0 0xff>;
  78. clock-frequency = <33333333>;
  79. interrupts = <16 2 0 0>;
  80. pcie@0 {
  81. reg = <0 0 0 0 0>;
  82. #interrupt-cells = <1>;
  83. #size-cells = <2>;
  84. #address-cells = <3>;
  85. device_type = "pci";
  86. interrupts = <16 2 0 0>;
  87. };
  88. };
  89. /* controller at 0xb000 */
  90. &pci2 {
  91. compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
  92. device_type = "pci";
  93. #size-cells = <2>;
  94. #address-cells = <3>;
  95. bus-range = <0x0 0xff>;
  96. clock-frequency = <33333333>;
  97. interrupts = <16 2 0 0>;
  98. pcie@0 {
  99. reg = <0 0 0 0 0>;
  100. #interrupt-cells = <1>;
  101. #size-cells = <2>;
  102. #address-cells = <3>;
  103. device_type = "pci";
  104. interrupts = <16 2 0 0>;
  105. };
  106. };
  107. &qportals {
  108. #address-cells = <1>;
  109. #size-cells = <1>;
  110. compatible = "simple-bus";
  111. qportal0: qman-portal@0 {
  112. compatible = "fsl,qman-portal";
  113. reg = <0x0 0x4000>, <0x100000 0x1000>;
  114. interrupts = <29 2 0 0>;
  115. cell-index = <0>;
  116. };
  117. qportal1: qman-portal@4000 {
  118. compatible = "fsl,qman-portal";
  119. reg = <0x4000 0x4000>, <0x101000 0x1000>;
  120. interrupts = <31 2 0 0>;
  121. cell-index = <1>;
  122. };
  123. qportal2: qman-portal@8000 {
  124. compatible = "fsl,qman-portal";
  125. reg = <0x8000 0x4000>, <0x102000 0x1000>;
  126. interrupts = <33 2 0 0>;
  127. cell-index = <2>;
  128. };
  129. };
  130. &bportals {
  131. #address-cells = <1>;
  132. #size-cells = <1>;
  133. compatible = "simple-bus";
  134. bman-portal@0 {
  135. compatible = "fsl,bman-portal";
  136. reg = <0x0 0x4000>, <0x100000 0x1000>;
  137. interrupts = <30 2 0 0>;
  138. };
  139. bman-portal@4000 {
  140. compatible = "fsl,bman-portal";
  141. reg = <0x4000 0x4000>, <0x101000 0x1000>;
  142. interrupts = <32 2 0 0>;
  143. };
  144. bman-portal@8000 {
  145. compatible = "fsl,bman-portal";
  146. reg = <0x8000 0x4000>, <0x102000 0x1000>;
  147. interrupts = <34 2 0 0>;
  148. };
  149. };
  150. &soc {
  151. #address-cells = <1>;
  152. #size-cells = <1>;
  153. device_type = "soc";
  154. compatible = "fsl,p1023-immr", "simple-bus";
  155. bus-frequency = <0>; // Filled out by uboot.
  156. ecm-law@0 {
  157. compatible = "fsl,ecm-law";
  158. reg = <0x0 0x1000>;
  159. fsl,num-laws = <12>;
  160. };
  161. ecm@1000 {
  162. compatible = "fsl,p1023-ecm", "fsl,ecm";
  163. reg = <0x1000 0x1000>;
  164. interrupts = <16 2 0 0>;
  165. };
  166. memory-controller@2000 {
  167. compatible = "fsl,p1023-memory-controller";
  168. reg = <0x2000 0x1000>;
  169. interrupts = <16 2 0 0>;
  170. };
  171. /include/ "pq3-i2c-0.dtsi"
  172. /include/ "pq3-i2c-1.dtsi"
  173. /include/ "pq3-duart-0.dtsi"
  174. /include/ "pq3-espi-0.dtsi"
  175. spi@7000 {
  176. fsl,espi-num-chipselects = <4>;
  177. };
  178. /include/ "pq3-gpio-0.dtsi"
  179. L2: l2-cache-controller@20000 {
  180. compatible = "fsl,p1023-l2-cache-controller";
  181. reg = <0x20000 0x1000>;
  182. cache-line-size = <32>; // 32 bytes
  183. cache-size = <0x40000>; // L2,256K
  184. interrupts = <16 2 0 0>;
  185. };
  186. /include/ "pq3-dma-0.dtsi"
  187. /include/ "pq3-usb2-dr-0.dtsi"
  188. usb@22000 {
  189. compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
  190. };
  191. crypto: crypto@300000 {
  192. compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
  193. fsl,sec-era = <3>;
  194. #address-cells = <1>;
  195. #size-cells = <1>;
  196. reg = <0x30000 0x10000>;
  197. ranges = <0 0x30000 0x10000>;
  198. interrupts = <58 2 0 0>;
  199. sec_jr0: jr@1000 {
  200. compatible = "fsl,sec-v4.2-job-ring",
  201. "fsl,sec-v4.0-job-ring";
  202. reg = <0x1000 0x1000>;
  203. interrupts = <45 2 0 0>;
  204. };
  205. sec_jr1: jr@2000 {
  206. compatible = "fsl,sec-v4.2-job-ring",
  207. "fsl,sec-v4.0-job-ring";
  208. reg = <0x2000 0x1000>;
  209. interrupts = <45 2 0 0>;
  210. };
  211. sec_jr2: jr@3000 {
  212. compatible = "fsl,sec-v4.2-job-ring",
  213. "fsl,sec-v4.0-job-ring";
  214. reg = <0x3000 0x1000>;
  215. interrupts = <57 2 0 0>;
  216. };
  217. sec_jr3: jr@4000 {
  218. compatible = "fsl,sec-v4.2-job-ring",
  219. "fsl,sec-v4.0-job-ring";
  220. reg = <0x4000 0x1000>;
  221. interrupts = <57 2 0 0>;
  222. };
  223. rtic@6000 {
  224. compatible = "fsl,sec-v4.2-rtic",
  225. "fsl,sec-v4.0-rtic";
  226. #address-cells = <1>;
  227. #size-cells = <1>;
  228. reg = <0x6000 0x100>;
  229. ranges = <0x0 0x6100 0xe00>;
  230. rtic_a: rtic-a@0 {
  231. compatible = "fsl,sec-v4.2-rtic-memory",
  232. "fsl,sec-v4.0-rtic-memory";
  233. reg = <0x00 0x20 0x100 0x80>;
  234. };
  235. rtic_b: rtic-b@20 {
  236. compatible = "fsl,sec-v4.2-rtic-memory",
  237. "fsl,sec-v4.0-rtic-memory";
  238. reg = <0x20 0x20 0x200 0x80>;
  239. };
  240. rtic_c: rtic-c@40 {
  241. compatible = "fsl,sec-v4.2-rtic-memory",
  242. "fsl,sec-v4.0-rtic-memory";
  243. reg = <0x40 0x20 0x300 0x80>;
  244. };
  245. rtic_d: rtic-d@60 {
  246. compatible = "fsl,sec-v4.2-rtic-memory",
  247. "fsl,sec-v4.0-rtic-memory";
  248. reg = <0x60 0x20 0x500 0x80>;
  249. };
  250. };
  251. };
  252. /include/ "pq3-mpic.dtsi"
  253. /include/ "pq3-mpic-timer-B.dtsi"
  254. qman: qman@88000 {
  255. compatible = "fsl,qman";
  256. reg = <0x88000 0x1000>;
  257. interrupts = <16 2 0 0>;
  258. fsl,qman-portals = <&qportals>;
  259. memory-region = <&qman_fqd &qman_pfdr>;
  260. };
  261. bman: bman@8a000 {
  262. compatible = "fsl,bman";
  263. reg = <0x8a000 0x1000>;
  264. interrupts = <16 2 0 0>;
  265. fsl,bman-portals = <&bportals>;
  266. memory-region = <&bman_fbpr>;
  267. };
  268. global-utilities@e0000 {
  269. compatible = "fsl,p1023-guts";
  270. reg = <0xe0000 0x1000>;
  271. fsl,has-rstcr;
  272. };
  273. };