p1020si-post.dtsi 4.9 KB

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  1. /*
  2. * P1020/P1011 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &lbc {
  35. #address-cells = <2>;
  36. #size-cells = <1>;
  37. compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
  38. interrupts = <19 2 0 0>,
  39. <16 2 0 0>;
  40. };
  41. /* controller at 0x9000 */
  42. &pci0 {
  43. compatible = "fsl,mpc8548-pcie";
  44. device_type = "pci";
  45. #size-cells = <2>;
  46. #address-cells = <3>;
  47. bus-range = <0 255>;
  48. clock-frequency = <33333333>;
  49. interrupts = <16 2 0 0>;
  50. pcie@0 {
  51. reg = <0 0 0 0 0>;
  52. #interrupt-cells = <1>;
  53. #size-cells = <2>;
  54. #address-cells = <3>;
  55. device_type = "pci";
  56. interrupts = <16 2 0 0>;
  57. interrupt-map-mask = <0xf800 0 0 7>;
  58. interrupt-map = <
  59. /* IDSEL 0x0 */
  60. 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
  61. 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
  62. 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
  63. 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
  64. >;
  65. };
  66. };
  67. /* controller at 0xa000 */
  68. &pci1 {
  69. compatible = "fsl,mpc8548-pcie";
  70. device_type = "pci";
  71. #size-cells = <2>;
  72. #address-cells = <3>;
  73. bus-range = <0 255>;
  74. clock-frequency = <33333333>;
  75. interrupts = <16 2 0 0>;
  76. pcie@0 {
  77. reg = <0 0 0 0 0>;
  78. #interrupt-cells = <1>;
  79. #size-cells = <2>;
  80. #address-cells = <3>;
  81. device_type = "pci";
  82. interrupts = <16 2 0 0>;
  83. interrupt-map-mask = <0xf800 0 0 7>;
  84. interrupt-map = <
  85. /* IDSEL 0x0 */
  86. 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
  87. 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
  88. 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
  89. 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
  90. >;
  91. };
  92. };
  93. &soc {
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. device_type = "soc";
  97. compatible = "fsl,p1020-immr", "simple-bus";
  98. bus-frequency = <0>; // Filled out by uboot.
  99. ecm-law@0 {
  100. compatible = "fsl,ecm-law";
  101. reg = <0x0 0x1000>;
  102. fsl,num-laws = <12>;
  103. };
  104. ecm@1000 {
  105. compatible = "fsl,p1020-ecm", "fsl,ecm";
  106. reg = <0x1000 0x1000>;
  107. interrupts = <16 2 0 0>;
  108. };
  109. memory-controller@2000 {
  110. compatible = "fsl,p1020-memory-controller";
  111. reg = <0x2000 0x1000>;
  112. interrupts = <16 2 0 0>;
  113. };
  114. /include/ "pq3-i2c-0.dtsi"
  115. /include/ "pq3-i2c-1.dtsi"
  116. /include/ "pq3-duart-0.dtsi"
  117. /include/ "pq3-espi-0.dtsi"
  118. spi@7000 {
  119. fsl,espi-num-chipselects = <4>;
  120. };
  121. /include/ "pq3-gpio-0.dtsi"
  122. L2: l2-cache-controller@20000 {
  123. compatible = "fsl,p1020-l2-cache-controller";
  124. reg = <0x20000 0x1000>;
  125. cache-line-size = <32>; // 32 bytes
  126. cache-size = <0x40000>; // L2,256K
  127. interrupts = <16 2 0 0>;
  128. };
  129. /include/ "pq3-dma-0.dtsi"
  130. /include/ "pq3-usb2-dr-0.dtsi"
  131. usb@22000 {
  132. compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
  133. };
  134. /include/ "pq3-usb2-dr-1.dtsi"
  135. usb@23000 {
  136. compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
  137. };
  138. /include/ "pq3-esdhc-0.dtsi"
  139. sdhc@2e000 {
  140. compatible = "fsl,p1020-esdhc", "fsl,esdhc";
  141. sdhci,auto-cmd12;
  142. };
  143. /include/ "pq3-sec3.3-0.dtsi"
  144. /include/ "pq3-mpic.dtsi"
  145. /include/ "pq3-mpic-timer-B.dtsi"
  146. /include/ "pq3-etsec2-0.dtsi"
  147. enet0: enet0_grp2: ethernet@b0000 {
  148. };
  149. /include/ "pq3-etsec2-1.dtsi"
  150. enet1: enet1_grp2: ethernet@b1000 {
  151. };
  152. /include/ "pq3-etsec2-2.dtsi"
  153. enet2: enet2_grp2: ethernet@b2000 {
  154. };
  155. global-utilities@e0000 {
  156. compatible = "fsl,p1020-guts";
  157. reg = <0xe0000 0x1000>;
  158. fsl,has-rstcr;
  159. };
  160. };
  161. /include/ "pq3-etsec2-grp2-0.dtsi"
  162. /include/ "pq3-etsec2-grp2-1.dtsi"
  163. /include/ "pq3-etsec2-grp2-2.dtsi"